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6-Nested Miller Compensation in Low-Power CMOS Design

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6-Nested Miller Compensation in Low-Power CMOS Design 388 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 Transactions Briefs__________________________________________________________________ Nested Miller Compensation in Low-Power CMOS Design Ka N...

6-Nested Miller Compensation in Low-Power CMOS Design
388 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 Transactions Briefs__________________________________________________________________ Nested Miller Compensation in Low-Power CMOS Design Ka Nang Leung and Philip K. T. Mok Abstract—First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit complexity. Index Terms—Feedforward transconductance stage, nested Miller com- pensation, nulling resistor. I. INTRODUCTION Low-voltage low-power CMOS multistage amplifiers are increasing in demand today; therefore, a frequency compensation technique, which affects the frequency and transient responses of a multistage amplifier, becomes essential. One of the compensation topologies is nested Miller compensation (NMC), and the stability conditions have been analyzed by Eschauzier et al. [1], [2] and Huijsing et al. [3]. However, You et al. pointed out that the accuracy of their analyses is questionable as the zeros were not taken into consideration [4]. Thus, more accurate stability conditions, which take into account the effect of zeros, are derived and given in this brief. In addition, NMC amplifiers suffer bandwidth reduction [1]–[3]. To overcome this and further improve the stability, an improved structure using a feedforward transconductance stage and a nulling resistor on NMC (NMCFNR) [5] is presented. As will be shown with theoret- ical analysis and experimental results, the proposed structure improves the frequency response, transient response, and power supply rejection ratio (PSRR). In this brief, the structure discussed is limited to the three-stage am- plifier due to the good compromise of both the dc gain and power con- sumption. In Section II, a brief review on a three-stage NMC amplifier is included as a quick reference. The improved stability conditions for low-power CMOS design is given in Section III, and then the proposed structure is presented in Section IV. II. NESTED MILLER COMPENSATION The structure of a three-stage NMC amplifier is shown in Fig. 1, where g m(1; 2; 3) , R o(1; 2; 3) , C p(1; 2) , C m(1; 2) , and C L are the transconductances, output resistances, lumped parasitic capacitances at the outputs of the gain stages, compensation capacitances, and loading capacitance of the amplifier, respectively. To achieve the stability, Eschauzier et al. [1], [2] and Huijsing et al. [3] proposed that Manuscript received July 1999; revised March 2001. This work was supported by the Research Grant Council of Hong Kong, under Project HKUST6007/97E. This paper was recommended by Associate Editor B. Gilbert. The authors are with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong. Publisher Item Identifier S 1057-7130(01)05235-1. the NMC amplifier should have Butterworth unity-feedback frequency response, so the gain–bandwidth product (GBW) and the dimension conditions of C m1 and C m2 are given by [1]–[3], [5], [6] GBW = 1 4 g m3 C L = g m1 C m1 = g m2 2C m2 : (1) After compensation, the first pole is located at a low frequency and is given by p 1 = 1=(C m1 g m2 g m3 R o1 R o2 R o3 ). The second and third poles form a complex pole and are given by p 2; 3 = (g m3 =2C L ) � j(g m3 =2C L ). Moreover, the phase margin (PM) is about 60�. The above stability conditions are derived based on four assump- tions: 1) the gain of each stage is much greater than one; 2) C m1 ,C m2 and C L are greater than C p1 and C p2 ; 3) g m3 is much larger than g m1 and g m2 ; and 4) the zeros locate at much higher frequencies than the poles. A simulation using a BSim3v2 model of a 0.8-�m CMOS process from AMS1 is carried out to verify the theory. The test circuit is shown in Fig. 2 with a supply voltage of �1 V and a loading capacitance of 100 pF. The first, second, and third stages are formed by M101–M104, M201—M203 and M301, respectively. Ideal current sources, Ib01–Ib03, are used to simplify the circuit, and the values of C m1 and C m2 are calculated according to (1). The calculated and simulated results are tabulated in the dataset 1 of Table I. From the results, the positions of the poles, GBW, and PM of an NMC amplifier can be accurately predicted. Moreover, since the zeros locate at higher frequencies than the GBW and jp 2; 3 j, the previous assumption on neglecting the right-half-plane (RHP) and left-half-plane (LHP) zero is proven to be valid. From the simulation, the stability conditions provide good stability to an NMC amplifier when g m3 � g m1 and g m2 holds true. However, this assumption may not be valid and is difficult to achieve in low- power CMOS design. Although there are many circuit techniques to reduce the effective transconductance of the first and second stages, these techniques have some disadvantages. Small bias current reduces the slew rate [7]–[12]. The small size of the transistors introduces a large offset voltage [12]. Source degeneration technique reduces the input common-mode range. Moreover, self-cascode configuration has poorer frequency response compared with a simple transistor [13]. To show the effect when g m3 is not much larger than g m1 and g m2 , simulations are carried out using the circuit in Fig. 2 again, and the results are listed in Table I. Four conditions are simulated: 1) g m3 is much larger than g m1 and g m2 ; 2) g m3 is larger than g m2 only; 3) g m3 is larger than g m1 only; and 4) g m3 is not much larger than g m1 and g m2 . The values of C m1 and C m2 are obtained according to the conditions in (1). It is obvious that, when g m3 � g m1 and g m2 does not hold, the positions of the poles, GBW, and PM are not the same as the predicted ones. The most important thing is that the stability is degraded. This is due to the frequency “peak” of the complex pole, which has a small damping factor (�). Moreover, as shown in Fig. 3, the gain margin is reduced when the RHP zero locates at a frequency close to or before the complex pole. Thus, it is necessary to establish new stability conditions in low-power CMOS design and find the minimum value of g m3 . 1Austria Miko Systeme International AG, Schloss Premstätten, A-8141 Un- terpremstätten, Austria. 1057–7130/01$10.00 © 2001 IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 389 Fig. 1. Structure of a three-stage NMC amplifier. Fig. 2. Test circuit of a three-stage NMC amplifier. Fig. 3. Frequency response of an NMC amplifier when the RHP zero is near the GBW and the complex pole has a small damping factor. III. STABILITY CONDITIONS OF AN NMC AMPLIFIER IN LOW-POWER CMOS DESIGN The stability conditions, GBW, and PM of a low-power CMOS NMC amplifier are evaluated in this section. If g m3 is not always much larger than g m1 and g m2 , the transfer function is given by (2), shown at the bottom of the page. It is necessary that g m3 > g m2 to ensure that all poles are located in the LHP so that no oscillation occurs. By tem- porarily neglecting the zeros and setting a Butterworth unity-feedback frequency response, the GBW and dimension conditions of C m1 and C m2 are given by GBW = 1 4 g m3 � g m2 C L = g m1 C m1 = g m2 g m3 2(g m3 � g m2 )C m2 : (3) From (3), the effective output stage transconductance is reduced by g m2 . In fact, the actual compensation capacitances are larger than those stated in (1). Applying the dimension conditions (3) into (2), the low-frequency first pole is p 1 = 1=C m1 g m2 g m3 R o1 R o2 R o3 , and the second and third poles form a complex pole, which is given by p 2; 3 = g m3 � g m2 2C L � j g m3 � g m2 2C L : (4) The � of the second-order function stated in (2), which controls the second and third poles, is 1= p 2. The positions of the RHP zero and LHP zero are obtained by solving the numerator of (2) and are given by z RHP = g m2 2C m1 1� 4C m1 g m3 C m2 g m2 + 1 (5) and z LHP = g m2 2C m1 1 + 4C m1 g m3 C m2 g m2 + 1 : (6) The RHP zero locates at a lower frequency than the LHP zero since the s term at the numerator of (2) is negative. Since the stability is not guaranteed if z RHP locates before jp 2; 3 j, z RHP is constrained to be equal to or larger than jp 2; 3 j (i.e., jz RHP j � jp 2; 3 j). Substituting (4) and (5) into this constraint, a condition on g m3 is obtained as follows: g m3 � 4g m1 + p 2 + 1 g m2 : (7) With the above information, the PM is calculated by the following ex- pression [14]: PM =180 � � tan�1 GBW p 1 � tan �1 2� GBW jp j 1� GBW jp j 2 � tan �1 GBW jz RHP j + tan �1 GBW z LHP � 60 � � tan �1 GBW jz RHP j + tan �1 GBW z LHP : (8) The PM of a low-power CMOS NMC amplifier is less than 60� due to jz RHP j < z LHP . A v (s) = g m1 g m2 g m3 R o1 R o2 R o3 1� s C m2 g m3 � s 2 C m1 C m2 g m2 g m3 (1 + sC m1 g m2 g m3 R o1 R o2 R o3 ) 1 + s (g m3 � g m2 )C m2 g m2 g m3 + s 2 C L C m2 g m2 g m3 : (2) 390 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 TABLE I SIMULATED RESULTS OF AN NMC AMPLIFIER (SUPPLY VOLTAGE = �1 V AND C = 100 pF) Fig. 4. Structure of the three-stage NMCFNR amplifier. IV. NMC WITH FEEDFORWARD TRANSCONDUCTANCE STAGE AND NULLING RESISTOR Since an NMC amplifier suffers bandwidth reduction and stability degradation by the RHP zero, the proposed structure, which is shown in Fig. 4, is introduced in this section. The feedforward transconduc- tance stage (g mf2 ), which is similar to NGCC [4], is used to cancel the feedforward small-signal current through C m2 at high frequencies and also increase the effective output transconductance of the amplifier. It is noted that g mf2 is set to be larger than g m2 in this topology. More- over, the nulling resistor (R m ) is used to eliminate the RHP zero as is the case with the two-stage Miller compensated amplifier. The transfer function of the proposed structure is given by (9), shown at the bottom of the next page. The above transfer is derived based on two assump- tions: 1) the gain of each stage is much greater than one and 2) C m1 , C m2 , and C L are greater than C p1 and C p2 . From the numerator of (9), when g mf2 > g m2 and R m = 1=(g mf2 + g m3 ), the amplifier has one LHP zero only. The stability conditions can be obtained by first neglecting the effect of the LHP zero and then setting the amplifier to have a Butterworth unity-feed- back frequency response. Thus, the GBW and dimension conditions are as follows: GBW = 1 4 g m3 + g mf2 � g m2 C L = g m1 C m1 = g m2 g m3 2(g m3 + g mf2 � g m2 )C m2 : (10) Fig. 5. Push–pull output stage formed by the feedforward transconductance stage and third gain stage. Comparing (10) with (3), the required values of C m1 and C m2 (es- pecially for C m2 ) are much smaller than those in NMC by a factor of (g m3 +g mf2 �g m2 )=(g m3 �g m2 ) and [(g m3 +g mf2 �g m2 )=(g m3 � g m2 )] 2 , respectively. Furthermore, the GBW is increased by the pres- ence of g mf2 . By applying (10) in (9), the low-frequency first pole is p 1 = 1=C m1 g m2 g m3 R o1 R o2 R o3 . The second and third poles form a complex pole with � = 1= p 2 as follows: p 2; 3 = g m3 + g mf2 � g m2 2C L � j g m3 + g mf2 � g m2 2C L : (11) IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 391 Fig. 6. Circuit diagram of the NMC amplifier. The PM of the proposed structure is given by PM =180o � tan�1 GBW p 1 � tan �1 2� GBW jp 2; 3 j 1� GBW jp 2; 3 j 2 + tan �1 GBW z LHP � 60 � + tan �1 GBW z LHP (12) where z LHP = C m1 + C m2 g mf2 + g m3 + C m2 (g mf2 � g m2 ) g m2 g m3 �1 : From (12), the stability of the proposed structure is improved due to the presence of the LHP zero. The feedforward transconductance stage can be implemented as shown in Fig. 5. The feedforward stage and the third stage form a push–pull output stage. If additional control circuitry is added, the output stage can be changed to class-AB type. Since the quiescent current of the PMOS and NMOS are the same, g mf2 can be set equal to g m3 to double the GBW. The size of the PMOS is about three times that of the NMOS to compensate for the difference of the mobilities of carriers. Moreover, if a PM greater than 60� is not required in some applications, C m1 , which controls the GBW, can be reduced to obtain a larger GBW. The stability of the NMCFNR amplifier is rather insensitive to the global variations of the circuit parameters since the stability conditions in (10) depend on the ratio of transconductances and capacitances. An- other issue to be considered is the exact value of the nulling resistor. A v (s) = g m1 g m2 g m3 R o1 R o2 R o3 1 + s (C m1 + C m2 )R m + C m2 (g mf2 � g m2 ) g m2 g m3 + s 2 C m1 C m2 [(g mf2 + g m3 )R m � 1] g m2 g m3 (1 + sC m1 g m2 g m3 R o1 R o2 R o3 ) 1 + s C m2 (g m3 + g mf2 � g m2 ) g m2 g m3 + s 2 C L C m2 g m2 g m3 (9) A v (s) � g m1 g m2 g m3 R o1 R o2 R o3 1 + s(C m1 + C m2 )R m + s 2 C m1 C m2 R m g m2 (1 + sC m1 g m2 g m3 R o1 R o2 R o3 ) 1 + s C m2 g m2 � 1 + s(C m1 + C m2 )R m + s 2 C m1 C m2 R m g m2 s C m1 g m1 1 + s C m2 g m2 = 1 + s(C m1 + C m2 )R m + s 2 C m1 C m2 R m g m2 s GBW 1 + s p 0 2 (13) 392 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 Fig. 7. Circuit diagram of the NMCFNR amplifier. Fig. 8. Micrograph of the NMC and NMCFNR amplifier. Any process variation leads to incomplete elimination of the RHP zero. However, this is not a problem since a value close to 1=(g mf2 + g m3 ) makes the s2 term in the numerator of (9) small, and the RHP zero lo- cates at a very high frequency and has no effect on the stability. The slew rate (SR) is improved since the required compensation ca- pacitances are smaller [6]. The good PM provides a good settling time (T s ) [15]. Moreover, the PSRR is also improved due to the wider band- width [6]. In addition to the static-state stability of the NMCFNR amplifier, the dynamic-state stability of the amplifier should also be considered. When the load current increases, either g m3 or g mf2 will be increased. The effect on the stability of the NMCFNR amplifier under the change of g m3 and g mf2 is analyzed as follows: When g m3 is increased and is larger than g m2 and g mf2 , (9) is changed to (13), shown at the bottom of the previous page. Since, from (10), p0 2 is larger than the GBW by more than two times and the zeros locate after the GBW, the amplifier is always stable when g m3 is in- creased. Similarly, when g mf2 is increased and is larger than g m2 and g m3 , (9) is changed to (14), shown at the bottom of the next page. The second pole is canceled by a zero, and the other zero and the third pole locate at frequencies higher than the GBW, so the amplifier is also stable when g mf2 becomes large. V. EXPERIMENTAL RESULTS A low-power 2-V NMC amplifier and the NMCFNR counter- part shown in Figs. 6 and 7 were fabricated in AMS double-metal double-poly 0.8-�m CMOS process with respective optimum stability conditions. The micrograph of the amplifiers is shown in Fig. 8. The first, second, and third stages are implemented by M101–M109, M201–M204, and M301, respectively. For the NMCFNR amplifier, the feedforward transconductance stage is formed by M302 with signal input from the output of the first stage. As aforementioned, the output stage is the push–pull type, and it can be modified to class-AB by an additional control circuitry. Both amplifiers have a load of 100 pF connecting in parallel with 25 k . The frequency responses of the NMC and NMCFNR amplifier were measured by HP4194A impedance/gain-phase analyzer and are shown in Fig. 9 while the transient responses were measured by LeCroy 9354A oscilloscope and are shown in Fig. 10. The performances of both amplifiers are tabulated in Table II for comparison. The dc gain of both amplifiers are greater than 100 dB, and the power consumption of both is nearly the same. For the frequency response, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 393 Fig. 9. Measured frequency responses of the NMC (top) and NMCFNR (bottom) amplifier (only the frequencies near the unity-gain frequency are shown). when compared with the NMC amplifier, the NMCFNR amplifier has about three times improvement on the GBW and 8� increase on the PM. For the transient response, the SR and T s (1%) were measured in unity-feedback configuration with a 0.5-V step input, and there are Fig. 10. Measured transient responses of the NMC and NMCFNR amplifier in unity-feedback configuration with a 0.5-V step input. more than three times improvement on both performances. Moreover, NMCFNR improves the negative PSRR by at least 54 dB. The value of C m1 is 30 pF and that of C m2 is 5.3 pF in the NM- CFNR amplifier while those in the NMC amplifier are much larger with C m1 = 99 pF and C m2 = 27 pF, respectively. As the required values of the compensation capacitors are much smaller in the NMCFNR, the size of the NMCFNR amplifier is about half that of the NMC counter- part. Moreover, the nulling resistor of 288 can be easily integrated by poly resistor in any commercial CMOS process. VI. CONCLUSION Modified stability conditions for NMC, particularly in low-power CMOS design, have been presented. Then, NMC with a feedforward transconductance and a nulling resistor, which improves NMC on the frequency response, transient response, and PSRR, has been introduced, analyzed, and verified by experimental results. In addition, it is shown that the implementation of NMCFNR is simple and no extra power consumption is needed. A v (s) � g m1 g m2 g m3 R o1 R o2 R o3 1 + s C m2 g mf2 g m2 g m3 + s 2 C m1 C m2 g mf2 R m g m2 g m3 (1 + sC m1 g m2 g m3 R o1 R o2 R o3 ) 1 + s C m2 g mf2 g m2 g m3 + s 2 C L C m2 g m2 g m3 � g m1 g m2 g m3 R o1 R o2 R o3 1 + s C m2 g mf2 g m2 g m3 (1 + sC m1 R m ) (1 + sC m1 g m2 g m3 R o1 R o2 R o3 ) 1 + s C m2 g mf2 g m2 g m3 1 + s C L g mf2 = g m1 g m2 g m3 R o1 R o2 R o3 (1 + sC m1 R m ) (1 + sC m1 g m2 g m3 R o1 R o2 R o3 ) 1 + s C L g mf2 � 1 + sC m1 R m s GBW 1 + s C L g mf2 : (14) 394 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 TABLE II MEASURED RESULTS OF THE NMC AND NMCFNR AMPLIFIER WITH LOADING CONDITION 100 pF/25 k Note: slew rate and settling time were measured at unity-feedback configuration with a 0.5-V step input. ACKNOWLEDGMENT The authors would like to thank S. F. Luk and J. Chan from HKUST for their technical assistance. REFERENCES [1] R. G. H. Eschauzier and J. H. Huijsing, Frequency Compensation Tech- niques for Low-Power Operational Amplifiers. Boston, MA: Kluw
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