Fairchild RCD snubber design

Application Note AN4147Application Note AN4147Application Note AN4147Application Note AN4147 Design Guidelines for RCD Snubber of Flyback www.fairchildsemi.com REV. 1.00 6/3/05 Abstract When the MOSFET turns off, a high voltage spike occurs on the drain pin because of a resonance between the leakage inductor (Llk) of the main transformer and the output capacitor (COSS) of the MOSFET. The excessive voltage on the drain pin may lead to an avalanche breakdown and eventually damage of the MOSFET. Therefore, it is necessary to add an additional circuit to clamp the voltage. In this article, some design guidelines for RCD snubber of flyback converters are presented. 1. Introduction One of the most simple topologies is a flyback converter. It is derived from a buck-boost converter by replacing filter inductors with coupled inductors, i.e. gapped core transformers. When the main switch turns on, the energy is stored in the transformer as a flux form, and the energy is transferred to output during the main switch off-time. Since the transformer needs to store energy during the main switch on-time, the core should be gapped. Since flyback converters need very few components, it is a very popular topology for low and medium power applications such as battery chargers, adapters, and DVD players. Figure 1 shows that a flyback converter operates in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) with several parasitic components such as primary and secondary leakage inductors, an output capacitor of MOSFET, and a junction capacitor of a secondary diode. When the MOSFET turns off, the primary current, id, charges COSS of the MOSFET in short time. When the voltage across COSS, Vds, exceeds the input voltage plus reflected output voltage, Vin+nVo, the Figure 1. Flyback converter; (a) configuration with parasitic components, (b) CCM operation, (c) DCM operation. Vin Llk1 id Vds + + iD Vo n:1 Lm im Llk2 Cj Coss Vin+nVo iD id Vds resonance between Llk1 and Coss diode reverse recovery current Vin+nVo iD id Vds resonance between Lm and Coss resonance between Llk1 and Coss id id Vin id iD id iD t t t t (a) flyback converter with parasitic components (b) CCM operation (c) DCM operation AN4147 APPLICATION NOTE 2 REV. 1.00 6/3/05 secondary diode turns on, so that the voltage across the magnetizing inductor, Lm, is clamped to nVo. There is, therefore, a resonance between Llk1 and COSS with high frequency and high voltage surge. This excessive voltage on the MOSFET may be a main cause of its failure. In the case of the CCM operation, the secondary diode remains turned on until the MOSFET is gated on. Therefore, when the MOSFET turns on, a reverse recovery current of the secondary diode is added to the primary current, and thus, there is a large current surge on the primary current at the turn-on instance. Meanwhile, since the secondary current runs dry before the end of one switching period in the case of the DCM operation, there is a resonance between Lm and COSS of the MOSFET. 2. Snubber design The excessive voltage due to a resonance between Llk1 and COSS should be suppressed to an acceptable level by an additional circuit in order to protect the main switch. The RCD snubber circuit and key waveforms are shown in figures 2 and 3, respectively. The RCD snubber circuit absorbs the current in the leakage inductor by turning on the snubber diode, Dsn, when Vds exceeds Vin+nVo. It is assumed that the snubber capacitance is large enough that its voltage does not change during one switching period. When the MOSFET turns off and Vds is charged to Vin+nVo, the primary current flows to Csn through the snubber diode Dsn. The secondary diode turns on at the same time. Therefore, the voltage across Llk1 is Vsn-nVo. The slope of isn is as follows: Figure 2. Flyback converter with RCD snubber. Figure 3. Key waveforms of the flyback converter with RCD snubber in DCM operation. where isn is the current flows into the snubber circuit, Vsn is the voltage across the snubber capacitor Csn, n is the turns ratio of the main transformer, and Llk1 is the leakage inductance of the main transformer. Therefore, the time ts is obtained as follows: where ipeak is the peak current of the primary current. The snubber capacitor voltage, Vsn, should be determined at the minimum input voltage and full load condition. Once Vsn is determined, the power dissipated in the snubber circuit at the minimum input voltage and full load condition is obtained as follows: where fs is the switching frequency of the flyback converter. Vsn should be 2~2.5 times of nVo. Very small Vsn results in a severe loss in the snubber circuit as shown in the above equation. On the other hand, since the power consumed in the snubber resistor Rsn is Vsn 2/Rsn, we can obtain the resistance as       − −= 1lk osnsn L nVV dt di Vin Vsn Rsn Dsn Llk id Vds + + Csn isn + iD Vo n:1 ipeak ts Vin Vsn nVo iD id isn Vds peak osn lk s inVV Lt × − = 1 s osn sn peaklks speak snsn fnVV ViLf ti VP − = ⋅ = 2 2 1 2 APPLICATION NOTE AN4147 REV. 1.00 6/3/05 3 follows: Then, the snubber resistor with proper rated power should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as follows: In general, 5~10% ripple is reasonable. Therefore, the snubber capacitance is calculated using the above equation. When the converter is designed to operate in CCM, the peak drain current together with the snubber capacitor voltage decreases as the input voltage increases. The snubber capacitor voltage under maximum input voltage and full load condition is obtained as follows: where fs is the switching frequency of the flyback converter, Llk1 is the primary side leakage inductance, n is the turns ratio of the transformer, Rsn is the snubber resistance, and Ipeak2 is the primary peak current at the maximum input voltage and full load condition. When the converter operates in CCM at the maximum input voltage and full load condition, the Ipeak2 is obtained as follows: When the converter operates in DCM at the maximum input voltage and full load condition, the Ipeak2 is obtained as follows: where Pin is the input power, Lm is the magnetizing inductance of the transformer, and VDC max is the rectified maximum input voltage in dc value. Check if the maximum value of Vds is below 90% and 80% of the rated voltage of the MOSFET (BVdss), at the transient period and steady state period, respectively. The voltage rating of the snubber diode should be higher than BVdss. Usually an ultra-fast diode with a 1A current rating is used for the snubber circuit. 3. Example In this section, an example will be shown. An adapter using FSDM311 has the following specifications: 85 Vac to 265 Vac input voltage range, 10 W output power, 5 V output voltage, and 67 kHz switching frequency. In the case where the RCD snubber uses a 1nF snubber capacitor and a 480kΩ snubber resistor, Figure 4 shows several waveforms with 265 Vac at the instance of the AC switch turn-on. Figure 4. Startup waveforms with 1 nF snubber capacitor and 480 kΩ snubber resistor. There are the drain voltage (Vds, 200 V/div), the supply voltage (Vcc, 5 V/div), the feedback voltage (Vfb, 1 V/div), and the drain current (Id, 0.2 A/div) in the following order. The maximum voltage stress on the internal SenseFET is around 675 V as shown in Figure 4. However, the voltage rating of FSDM311 is 650V according to the datasheet. There are two reasons for exceeding the voltage ratings. One is the wrong transformer design, the other is the wrong snubber design. Figure 5 gives an example of incorrect snubber design. Figure 5. Steady state waveforms with 1 nF snubber capacitor and 480 kΩ snubber resistor. s osn sn peaklk sn sn f nVV ViL VR − = 2 1 2 2 1 ssnsn sn sn fRC VV =∆ 2 )(2)( 221 2 2 peakslksnoo sn IfLRnVnV V ++ = )(2 )( max max max max 2 oDCsm oDC oDC oDCin peak nVVfL nVV nVV nVVP I + × + × + = ms in peak Lf PI 22 = 574V 451V AN4147 APPLICATION NOTE 4 REV. 1.00 6/3/05 As mentioned above, for reliability the maximum voltage stress at the steady state should be equal to 80% of the rated voltage (650 V * 0.8 = 520 V). Figure 5 shows the voltage stress on the internal SenseFET is above 570 V with Vin = 265 Vac at steady state. However, the fact that Vin+nVo is around 450 V (= 375 V + 15 * 5 V) implies the turns ratio of the transformer is 15, which is a reasonable value. Therefore, the snubber circuit should be redesigned. Let Vsn be twice that of nVo, 150 V. And Llk1 and ipeak is 150 µH and 400 mA by measuring, respectively. Then we obtain the snubber resistance as follows: And the power emission from Rsn is calculated as follows: Let the maximum ripple of the snubber capacitor voltage be 10%, then the snubber capacitance is obtained as follows: The results with 1.4 kΩ (3 W) and 10 nF are shown in Figures 6 and 7. Figure 6. Startup waveforms with 10 nF snubber capacitor and 14 kΩ snubber resistor. Figure 7. Steady state waveforms with 10 nF snubber capacitor and 14 kΩ snubber resistor. The voltage stresses on the internal SenseFET are 593 V and 524 V at the startup and steady state, respectively. These are around 91.2% and 80.6% of the rated voltage of FSDM311, respectively. k ku f nVV ViL VR s osn sn peaklk sn sn 14 67 75150 1504.0150 2 1 150 2 1 2 2 2 1 2 = × − ××× = − = W kR VP sn sn 6.1 14 15022 === nF kkfRV VC ssnsn sn sn 10671412 120 = ×× = ∆ = AN4147 APPLICATION NOTE 6/3/05 0.0m 001 Stock#AN30000010  2005 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PROD- UCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPO- RATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the la- beling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support de- vice or system, or to affect its safety or effectiveness. www.fairchildsemi.com by Gwan-Bon Koo/ Ph. D FPS Application Group / Fairchild Semiconductor Phone +82-32-680-1327 Fax +82-32-680-1317 E-mail koogb@fairchildsemi.co.kr