More Than a Core_en

80 Issue 213 April 2008 CIRCUIT CELLAR® www.circuitcellar.com thought these shining stars would burn out so fast? The microprocessor was barely born before it headed into battle. Early 8-bit skirmishes foreshadowed the epic struggle between the Intel ’x86 and the then Motorola 68K, a battle that counted a myriad of upstart architec- tures as collateral casualties. May the 88K, i860, Clipper, 29K, and all of the others rest in peace. True believers are entitled to pitch their favorite architecture and poo-poo the others. Taking nothing away from Cortex M3, the fact is that all of the debates have become less relevant, especially for blue-collar embedded apps. Maybe it’s just battle fatigue, having seen so many architectures march off to war. Remember way back in the mainframe years (1960–1970s) when companies like Univac, Burroughs, and Honeywell challenged IBM with “better” architectures? All dead and gone. Then there were the fabulous mini- computers such as the Data General Nova and the Digital Equipment VAX. Like teenagers, they seemed invinci- ble. “Nova” indeed. Who would have Having covered the territory last month (“More Bits, Less Filling,” Circuit Cellar 212, 2008), it’s not my intention to get stuck on the topic of 32-bit MCUs. Believe me, there’s plenty of other neat stuff going on with FPGAs, wireless, sensors, and other wonders of the silicon age. Nevertheless, if you have anything to do with embedded systems, you need to stay up to speed with the latest hot rod chips or you’ll get left behind. In some ways these fast and furious MCUs remind me of the brand new Tesla Motors high-performance elec- tric vehicle just now hitting the streets. It’s got the efficiency and green aspects of a golf cart, but can smoke the tires when you punch it. The big difference is that the 32-bit MCUs don’t cost an arm and a leg, but in fact are a luxury any designer can afford. So this month, you’re invited to look over my shoulder as I pop the hood on the STMicroelectronics STM32 (see Figure 1). You’ll recall from last time that its main claim to fame is the use of the new ARM Cortex M3 core. Sure, that’s newswor- thy, but there’s more to the STM32 than that. WORLD BEYOND CORE Indeed, over the years, I’ve come to the conclusion that “core wars” More Than a Core SILICON UPDATE by Tom Cantrell While examining 32-bit microcontrollers last month, Tom decided that the STMicroelectronics STM32 was worth a second look. With the new ARM Cortex M3 core, good peripherals, integration, and energy efficiency, this could be just the MCU for your next project. Figure 1—The ARM Cortex M3 core is the attention-getter in the new STM32 MCU from STMicroelectronics. But there’s more to an MCU than a processor core, including lots of flash memory, fast SRAM, and a bunch of I/O. Cortex-M3 DMA ICode Flash interface Flash memory SRAM DCode System Ch. 1 Ch. 2 Ch. 7 AHB system bus Bridge 1 Bridge 2 APB2 APB1 GPIOA GPIOB GPIOC GPIOD GPIOE EXTI USART1 SPI1 ADC1 ADC2 TIM1 AFIO USART2 USART3 SPI2 I2C1 I2C2 USB IWDG WWDG CAN BKP PWR TIM2 TIM3 TIM4 DMA Request 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 80 Jeff Stamp Jeff Text Box Circuit Cellar, the Magazine for Computer Applications. Reprinted by permission. For subscription information, call (860) 875-2199, or www.circuitcellar.com. Entire contents copyright ©2008 Circuit Cellar Inc. All rights reserved. www.circuitcellar.com Issue 213 April 2008 81CIRCUIT CELLAR® major 32-bit MCUs (including the ARM7 and ARM9 chips ST also offers) are fully capable of getting the job done in most applications. Look at a die photo of any 32-bit flash MCU and what you’ll find is a little processor core stuck in the cor- ner, dwarfed by surrounding memory and I/O silicon. The fact is, while the architecture chosen for the core may be the sizzle, it’s the implementation of an entire chip that’s the steak. FLASH FOR CASH Sure architecture has an impact on performance, but so do a lot of other things starting with bus bandwidth. The differences (relatively minor actu- ally) in the way competing architec- tures choose to deal with instructions and data don’t matter nearly as much as how fast a particular chip can actu- ally do it. In the blue-collar space these chips target, we’re generally talking about non- cache implementations. That means flash (i.e., instruction fetch) bandwidth is a crit- ical limiting factor. The STM32 comes in two flavors, “Access” and “Performance,” with a major difference being that the for- mer runs up to 36 MHz and the latter to 72 MHz (see Table 1). Just keep in mind that higher clock rates require 0, 1, or 2 flash wait states for clock rates up to 24, 48, and 72 MHz, respectively. If something isn’t done, wait states can lead to the awkward situation where more “megahertz” means less performance. It’s no surprise that most 32-bit MCUs devote silicon to the cause of getting around the flash bottleneck. The STM32 is no excep- tion, using a 64-bit wide flash bus in conjunction with two 64-bit prefetch buffers to hide the flash latency. Even though this simple prefetch scheme is relatively unobtrusive, there may be times when you’d prefer to turn it off, which the STM32 allows you to do. If you really need max MIPS, take advantage of the fact that the STM32 allows execution of code from the on- chip SRAM at full speed. You can use the SRAM as a “programmer directed cache,” preloading it with perform- ance-critical routines such as DSP inner loops and interrupt handlers. Just remember that a MIPS rating is only half the story. You can crank through all of the instructions you want, but nothing useful happens until data makes its way to and from the pins. As a practical matter, the on- chip I/O devices are just as important as the processor core itself in achiev- ing peak system performance. I/O U I/O throughput starts with the num- ber and performance of the on-chip I/O devices themselves. The STM32 has a lot of fast I/O, but that can actually be a curse if the I/O traffic clogs available bus bandwidth and demands a lot of handholding by the processor. The STM32 avoids that pitfall with multi- ple on-chip I/O busses to boost band- width and a powerful seven-channel DMA controller that offloads the processor of I/O grunt work. Another way to boost bus band- width is to demand less of it in the first place. As I went through the specs, I was impressed with the way the STM32 uses “smart” I/O devices that take care of their own dirty laun- dry rather than bugging the processor to do it for them. Even the simple stuff such as serial and parallel I/O is pretty fancy these days. Every STM32 I/O line is indi- vidually programmable as input (pull- up and pull-down options) or output (push/pull or open collector with out- put drive strength options). I/O lines are also 5-V tolerant and can source/sink a whopping 25 mA, with the not unexpected caveat that total chip power is limited to 150 mA. A measure of port-remapping capability enables juggling peripheral pin assignments to best fit a particular application. As I’ve noted before, the traditional RISC load/store architecture is prob- lematic for “atomic” bit operations because an interrupt might occur between the load and the store. The Package pins 36 36 48 48 48 64 64 64 100 100 Flash 32 KB 64 KB 32 KB 64 KB 128 KB 32 KB 64 KB 128 KB 64 KB 128 KB SRAM 10 (6) KB 20 (10) KB 10 (6) KB 20 (10) KB 20 (16) KB 10 (6) KB 20 (10) KB 20 (16) KB 20 (10) KB 20 (16) KB General-purpose timers 2 3 2 3 3 2 3 3 3 3 Advanced control timer 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) SPI 1 1 1 2 2 1 2 2 2 2 I2C 1 1 1 2 2 1 2 2 2 2 USART 2 2 2 3 3 2 3 3 3 3 Full-speed USB 2.0 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) CAN 2.0B 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 12-bit 1-µs A/D 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 10 ch 2 (1) × 16 ch 2 (1) × 16 ch 2 (1) × 16 ch 2 (1) × 16 ch 2 (1) × 16 ch General-purpose I/Os 26 26 37 37 37 51 51 51 80 80 CPU Frequency 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz 72 (36) MHz Table 1—STMicroelectronics blasts off the starting line with a full complement of 20 STM32 parts, divided equally between “Performance” and “Access” lines. In this table, the “Access” line features are shown in parenthesis where they differ from the “Performance” line. Another difference is that both lines come standard with a –40° to 85°C tempera- ture range, but the “Performance” parts also have an extended temperature range (–40° to 105°C) option. 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 81 www.circuitcellar.com CIRCUIT CELLAR® Issue 213 April 2008 83 fast), and standards (e.g., SM Bus 2.0). No surprise that the USARTs are fast (up to 4.5 Mbps) and capable (e.g., LIN, IrDA) as well. Note that any or all of these serial I/Os work with the DMAC, taking advantage of its intelli- gence (e.g., 8-, 16-, and 32-bit bus matching, circular buffer manager), which leaves the processor free for more important tasks. The “Performance” parts include USB 2.0 (full-speed, 12.0 Mbps) and CAN interfaces. This seems like a rather unlikely pairing and indeed the datasheet reveals that you can really only use one function at a time (they share the use of a 512-byte buffer). Once again, you’ll find that these interfaces have the “smart” features that make life easier for the processor and programmer. For instance, the CAN controller has programmable Cortex M3 architecture takes a crack at the problem with a “bit-banding” capability that provides atomic access to single bits. In addition, the STM32 also incorporates “set/reset” shadow registers for I/O, a solution that has the advantage of being able to deal with multiple bits at a time. In safety-critical applications (e.g., transportation, medical, and industri- al), a single lowly I/O line can have life and death riding on its shoulders. The STM32 has a unique capability to “lock” the configuration of an I/O line against unintended reprogramming to help keep a software crash from lead- ing to a real one. Moving on to serial I/O, every STM32 includes a SPI port, an I2C port, and two USARTs while the larg- er parts add an extra one of each. That’s a total of up to seven fast and full-featured serial ports, quite impres- sive for an entry-level part. The SPI ports run at up to 18 MHz as master or slave in half- or full- duplex mode. Besides the usual options (clock rate, mode, 8- to 16-bit frame), there’s hardware that takes care of the CRC for flash cards (e.g., SD Card). Likewise, the I2C port han- dles different modes (e.g., Slave, Multi-Master), speeds (standard and message filters so it can screen mes- sage traffic by itself without bothering the processor. If you want to do real-time, you need plenty of timers. General house- keeping is handled with an RTC, a free-running “SysTick” counter, and two separate watchdog timers, while three 16-bit units with input capture, output compare, and PWM do the heavy lifting. “Performance” parts go even further by throwing in an “Advanced Control Timer” that has even more bells and whistles (see Figure 2). Analog capability is another differ- ence between the two STM32 lines. The “Access” parts include one con- verter while the “Performance” line has two converters with the simulta- neous sampling capability required for many applications (e.g., motor control TI1 TI2 Counter Forward Jitter Backward Jitter Forward Up Down Up Figure 2—Smart timers are needed to enable real-time applications to handle tasks in hardware that would otherwise bog down the processor core. The Encoder mode of the Advanced Control Timer (ACT) included in STM32 “Performance” parts is a good example. It automatically monitors the phase relationship of two inputs and keeps track of the cumulative count. Figure 3—Automatic scanning of a group of analog inputs is a common feature in modern ADCs. The STM32 takes the concept a step further with the ability to interrupt one group scan by “injecting” another. ADC1 reg ADC1 inj CH0 CH1 CH2 CH0 CH3 CH4 1st Trig CH3CH2 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 83 84 Issue 213 April 2008 CIRCUIT CELLAR® www.circuitcellar.com DMAC can work together to handle high-speed timing critical tasks in hardware. Purists will argue that no MCU can match a DSP or specialized chip for applications like motor con- trol, but I bet the STM32 might sur- prise them. REALITY SHOW There is no doubt that the processor and peripherals are the attention-get- ters for any MCU. But there are also a lot of nuts and bolts required to lash together a real-world design. Some par- ticular little piece of “glue logic” may seem insignificant, until you need it and it’s not there. Then all of a sudden it’s a big deal with the potential to and power factor correction). While the basic converter specs (12 bits, 1 µs, up to 16 channels) are competitive, it’s the sophisticated CPU cycle-savers that set this ADC apart from most. Many ADCs include a “scan” capa- bility to automatically convert a sequence of channels. The STM32 takes it to the next level by adding a second scan group that can be “inject- ed” into (i.e., interrupt) the regular scan (see Figure 3). An “analog watch- dog” capability provides independent threshold comparison for any/all pins in either the regular or injected scan groups, or both. Above and beyond their individual capabilities, the timers, ADC(s), and complicate the design or otherwise compromise the application. Traditional RISCs, reflecting their “computer” (versus “controller”) background, can be pretty lame when it comes to interrupts, but not so for the STM32. In addition to the Cortex M3 architectural improvements (e.g., built-in vectored interrupt controller and “tail-chaining” to minimize stack operations), the STM32 includes dedi- cated hardware to configure up to 19 I/O lines as external interrupt/event inputs. While it sometimes seems that all of the focus is on MIPS and mega- hertz, there is also the small matter of power consumption. “Small matter” SYSCLK 8-MHz HSI RC HSI /2 PLLSRC PLLMUL ..., x16 ... x2, x3, x4 PLL PLLCLK HSE CSS PLLXTPRE 4–16 MHz HSE OSC LSE OSC 32.768 kHz LSI RC 40 kHz LSI LSE /2 /128 to RTC RTCCLK SW 72 MHz Max RTCSEL[1:0] To independent watchdog (IWDG) IWDGCLK Main clock output /2 HSI HSE SYSCLK PLLCLK MCO USB Prescaler /1, 1.5 AHB Prescaler /1, 2...572 USBCLK to USB interface HCLK to AHB bus, core memory, and DMA to Cortex system timer FCLK Cortex free running clock PCLK1 to TIM2, 3, and 4 APB1 Prescaler /1, 2, 4, 8, 16 /8 to APB1 peripherals 36 MHz max 72 MHz max Clock enable (3 bits) Peripheral clock enable (13 bits) TIM2, 3, 4 x1, 2, Multiplier APB2 Prescaler /1, 2, 4, 6, 16 TIM1 Timer x1, 2 Multiplier ADC Prescaler /2, 4, 6, 8 TIMXCLK PCLK2 to TIM1 Peripheral clock enable (3 bits) Peripheral clock enable (11 bits) to APB2 peripherals 72 MHz max TIM1CLK Peripheral clock enable (1 bit) to ADC ADCCLK Legend: HSE = High-speed external clock signal HSI = High-speed internal clock signal LSI = Low-speed internal clock signal LSE = Low-speed external clock signal OSC_OUT OSC_IN OCS32_IN OSC32_OUT MCO 48 MHz HSI Figure 4—Some may consider it mere “glue logic,” but the clock generator on a modern MCU such as the STM32 plays a critical role in achieving system price, power, and performance goals. 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 84 www.circuitcellar.com CIRCUIT CELLAR® Issue 213 April 2008 85 pin) is detected. More evidence that the STM32 takes the nuts and bolts seriously is the clock generator (see Figure 4). Make that clock(s) generator(s). This chip’s got so many clocking options I thought I was in Switzerland. The primary 8-MHz oscillator (factory trimmed for accura- cy) drives a PLL to generate the myriad of high-frequency clocks required for the processor and peripherals. Alternatively, you can provide an exter- nal 4- to 16-MHz clock, in which case the internal clock serves as a monitor and backup should the external clock fail. There’s a separate low-speed (40-kHz) clock that’s powered from the VBAT backup power supply. It’s not accurate enough for real time, but it does fill the key role of providing an on-chip wakeup source when the MCU core (i.e., 1.8-V domain) is powered down. And while better than nothing, a sin- gle watchdog timer always raises the question of who will watch the watchers? Taking advantage of the additional clock, the STM32 inte- grates two independent watchdog timers for a level of protection only true redundancy provides. Together the power and clock sys- tems give you a lot of power-saving options. Embellishments to a trio of low-power modes (Sleep, Stop, and Standby) include the ability to tweak various dials on the clock generator and the voltage regulator (run, power down, off). The lowest power mode (Standby) takes advantage of the sepa- rate backup supply domain to shut primary power off yet retain the abili- ty to wake up from an RTC alarm or the independent watchdog. And just how low power are we talking? According to the datasheet, even running full bore at 72 MHz with all peripherals enabled, you’re looking at just 0.5 mA per 1 MHz typ- ical (i.e., 36 mA at 72 MHz at room temperature). And here’s another rea- son to put your most frequently exe- cuted routines in RAM: not only is it fast (zero wait states), but running code from RAM also consumes less than half the power (e.g., 14.4 mA at 72 MHz) of running code from flash memory. Another power-saving trick as in your design had better consume a small amount of power, or else. After all, a main claim to fame for all of the new-age 32-bit MCUs is that they can go head-to-head with 8-bit parts and that means battery-powered applications. Powering the chip couldn’t be sim- pler. Just hook it up to anything from 2 to 3.6 V and it springs to life. An on- chip regulator supplies 1.8 V internally while power-up/power-fail RESET and over- and under-voltage interrupts are built-in. The ADC features a precise on-chip 1.2-V reference voltage, but you can connect an external reference if you wish (noting that using the ADC boosts the minimum required chip voltage from 2 to 2.4 V). Finally, just hang a 1.8- to 3.6-V battery on the VBAT supply pins if you want to take advantage of the RTC and related backup features. Switchover between the primary and battery backup supplies is handled auto- matically on-chip. Besides the RTC, VBAT also pro- vides power for 10 16-bit “backup” registers (i.e., RAM). A unique protec- tion option automatically clears the contents of these registers if “tamper- ing” (i.e., unexpected activity on a Photo 1—Drape this gadget around your neck and you’ll be the life of the party! A good MCU needs a good starter kit and those provided by the likes of Raisonance (the STM32 primer shown here), Keil, IAR Systems, and Hitex Development Tools make it easy and inexpensive to check out the new STM32 MCU. Flash memory 128 KB Application 3 4 KB Application 1 8 KB Application 2 4 KB Debugable application 8 KB OS 24 KB RAM 20 KB OS 4 KB Application data 16 KB 0x0801FFF 0x08015000 0x08014000 0x08012000 0x0800A000 0x08009000 0x08008000 0x08006000 0x08000000 0x20004FFF 0x20004000 0x20000000 G et fu ll v e rs io n to u pg ra de to de bu g he re 9 6 KB Fr e e v e rs io n de bu g 32 K B Figure 5—The STM32 primer may look like a toy, but under the hood is a “Circle OS” that supports application development and experimentation. There’s plenty of room in the STM32 on-chip flash and SRAM for both “Circle OS” and application code and data. 2804003-Cantrell.qxp 3/7/2008 10:45 AM Page 85