time_interleaved_analog_to_digital_converters

Time-Interleaved Analog-to-Digital Converters David G. Nairn Department of Electrical & Computer Engineering University of Waterloo Waterloo, Ontario Canada N2L 3G1 nairn@uwaterloo.ca Abstract-This paper provides a tutorial review of time-inter- leaved analog-to-digital converters. After explaining the impact of offset, gain, timing and other mismatches on converter perfor- mance, current solutions to the mismatch problems are presented. The paper concludes with a summary of the current-state-of-the art for time-interleaved analog-to-digital converters. I. INTRODUCTION Time-interleaved Analog-to-Digital Converters (ADCs) combine multiple sub-ADCs into a single ADC system that can achieve significantly faster sample rates than that of the sub- ADCs alone [1]. Historically, the primary drawback to time- interleaved ADCs, has been the need to tightly match the char- acteristics of the sub-ADCs [2]. Recently, applications requir- ing the digitization of very wide-band signals, the availability of power efficient sub-ADCs and trimming techniques made possible by deep sub-micron Complementary Metal Oxide Sil- icon (CMOS) technologies, has lead to significant advances in the performance of time-interleaved ADCs. Typical very wide-band applications include high-band- width oscilloscopes [3] and optical communication systems [4]. Each of these applications require signal bandwidths in the range of 10GHz. Unfortunately, currently available non-time- interleaved ADCs are incapable of sampling the input signals at the 20 to 24GSample/s rates that are required. Consequently it is necessary to use time-interleaved ADCs in these applica- tions, simply to meet the required sample rates. In other applications, the power dissipation of existing high-speed ADCs is too high for a practical system. In these cases, slow low-power ADCs can be time-interleaved to achieve the required sample rates with lower power dissipa- tions [5]. A particularly attractive use for this approach is in ultra-wideband receivers, where it is desirable to embed the ADC into a single-chip system [6]. In addition, advances in digitally assisted analog circuits have greatly relieved the mismatch problem for time-inter- leaved ADCs. With the use of Digital Signal Processing (DSP), it is now possible to detect and correct the mismatches between sub-ADCs that have historically limited the resolution of time- interleaved ADCs [7-27]. Consequently, time-interleaved ADCs are now an attractive approach to implementing, high- speed/high-resolution, low-power ADCs. To facilitate a better understanding of time-interleaved ADCs, this paper provides an introduction to time-interleaved ADCs, their key limitations and current solutions to these limi- tations. In section II, the operation and terminology of time- interleaved ADCs is discussed along with an alternate approach to interleaving. Then in section III, the effects of mis- matches between the sub-ADCs are reviewed. Section IV looks at current approaches for reducing and compensating the vari- ous mismatches between the sub-ADCs. In Section V, the cur- rent state-of-the-art is reviewed, followed by conclusions in section VI. II. INTERLEAVING ADCS FOR HIGH-SPEED SAMPLING Multiple sub-ADCs can be interleaved in either the time domain, as shown in Fig. 1 [2] or in the frequency domain, as shown in Fig. 2 [26]. While the approaches are similar, the time-interleaved approach is generally simpler to implement in current processing technologies. When interleaved in the time domain, M sub-ADCs, each with a conversion rate of fc are combined to achieve a system sampling rate of fs. By appropriately shifting each sub-ADC’s Figure 1) A time-interleaved ADC with M = 4. ADC-A Clk-A ADC-B Clk-B ADC-C Clk-C ADC-D Clk-D Clock Control Analog In Digital Out Clock (fs) Clk-A (fc) Clk-B (fc) Clk-C (fc) Clk-D (fc) Clock (fs) 289 IEEE 2008 Custom Intergrated Circuits Conference (CICC) 978-1-4244-2018-6/08/$25.00 ©2008 IEEE 12-1-1 yxu Highlight clock, as shown in Fig. 1, the analog input is effectively sam- pled at fs which is given by: . (1) M, the interleaving factor, directly indicates the speed improvement. When M = 2, time-interleaved ADCs are often called “ping-ponged” ADCs. Time-interleaved ADCs are also commonly referred to as parallel ADCs.1 Note that if Nyquist rate performance is required, each sub-ADC’s bandwidth must be at least fs/2. In addition, as discussed in Section III, even for moderate resolutions, it is imperative that the sub-ADCs be well matched. When interleaving in the frequency domain, each sub-ADC is preceded by a frequency selective filter, as shown in Fig. 2 [26]. In this case, each sub-ADC handles a much narrower band of frequencies. Nevertheless if the sub-ADCs are identi- cal, they still require an input bandwidth of at least fs/2, to achieve Nyquist rate performance. A attractive feature of this approach is that all of the sub-ADCs can be operated from the same low-speed clock. Unfortunately, to achieve good perfor- mance, the analog filters must be well matched in their transi- tion bands. Most current fabrication technologies are better suited to implementing digital circuits than to implementing well- matched analog circuits. In this design environment, it is pref- erable to minimize the analog circuitry and exploit digital cir- cuits to enhance the performance of the remaining analog circuits. Consequently, the time-interleaved approach is gener- ally preferred over the band-splitting approach for implement- ing high-speed ADCs. III. EFFECTS OF MISMATCHES In time-interleaved ADCs, each output sample comes from a single sub-ADC. Consequently, if the sub-ADCs are not per- fectly matched, spurious tones appear in the interleaved output that are not present in the output of any of the sub-ADCs. Some mismatches, such as offsets and noise coupling produce spurious tones in the interleaved ADC’s output, even in the absence of an input signal. Other mismatches, such as gain mismatches and timing skews, only produce spurious tones when an input signal is present. In most untrimmed time-inter- leaved ADCs, the dominant spurious tones are due to offset, gain and timing skew mismatches and have been extensively analyzed by early researchers in the field [2], [7], [27]. Later researchers have also addressed the effects of bandwidth mis- matches [28] and linearity mismatches [29]. Since each of these authors provides a good analysis of the mismatch effects, the purpose of the following discussion is to provide some understanding of the nature of the matching problem particu- larly for offset, gain and timing skew mismatches. Offset mismatches When two ADCs, with different offsets, VOS1 and VOS2, are time-interleaved and there is no input signal, the output oscillates between the two offset levels, as shown in Fig. 3. The resulting square-wave has a frequency of fs/2. The square wave’s amplitude (and root mean squared (RMS) level) is given by (2) To lower the offset tone’s RMS level to the quantization noise level (i.e 0.289VLSB, where VLSB is the least significant bit size), the offsets of the converters must match to about VLSB/4. Often spurious tones at fs/2 are not a problem. Unfortu- nately when M is greater than two, the spurious tones appear at f = ifs/M, where i = 0, 1, … M-1. In this case, the tones due to offset mismatches appear in-band. The offset tones due to time-interleaving four (M = 4) ideal ADCs with random offsets between LSB at the 8-bit level are illustrated in Fig. 4. Note that the tone at fs/4 is only down 42dB from full scale. Conse- quently, to achieve a spurious free dynamic range (SFDR) at least equal to the ideal SNR, the sub-ADCs’ offsets must match to about 2 bits better than the resolution of the sub- ADCs. 1. Unfortunately, flash ADCs are also often called parallel ADCs. fs M fc⋅= Figure 2) A band-splitting ADC. ADC-A D S PAnalog In Digital Out Clock (fc) ADC-B ADC-C ADC-D ∆VOS VOS1 VOS2– 2 ------------------------------------= Figure 3) Output of two time-interleaved ADCs with different offsets and zero input (f = fs/2, VRMS = ∆VOS). 0 VOS1 VOS2 VOS(avg) ∆VOS ∆VOS Time O ut pu t S ig na l 1± 29012-1-2 Gain mismatches The effects of a gain mismatch in a two channel (M = 2) time-interleaved ADC are illustrated in Fig. 5. The input to the system is a single tone at fs/8, the two sub-ADCs have sample rates of fc = fs/2. So each sub-ADC sees an input at fc/4, as shown in Fig. 5a and b. In the sampled time domain, these samples also represent sine-waves at where k is any integer. The sine waves for fc - fin = 3fc/4 and for fc + fin = 5fc/ 4 are shown in Fig. 5. Note that the signal (fc/4) is in phase between the two channels while the other components (3fc/4 and 5fc/4) are 180o out of phase. In a single ADC these other signals are clearly outside the Nyquist band and can be neglected. When the two channels combine, the undesired spectral components cancel, if the two sub-ADCs have the same gain. If the gains do not match, imperfect cancellation results in residual tones at or as they are more com- monly expressed at , where i = 1, 2, … M - 1. Note that the spurious tones are proportional to the amplitude of the input signal and to the relative mismatch. For a single tone input, the SFDR due to gain mismatches, in a two channel sys- tem, is given by: (3) Where ∆A is the gain mismatch. To obtain an SFDR equal to an ideal N-bit ADC’s SNR, the sub-ADCs’ gains must match to the N-bit level. This gain matching is twice the required matching of the MSB component in each sub-ADC [2]. Timing skews The third dominant mismatch effect is due to sample time mismatches, these mismatches are often referred to as timing skews. Timing skews arise because the clock or signal delay to each sub-ADC’s sampler differs from that of the other sam- plers. In the case of timing skews, the plots illustrated in Fig. 5 are modified such that the outputs from the two channels have the same amplitudes but different phase shifts. Consequently when the two channels are combined, there is incomplete can- cellation of the undesired tones. The relative size of the tones depends on both the timing mismatches, ∆T and the frequency of the input signal, fin. For a two channel system, the SFDR due to timing skews is given by; (4) Similar to the gain mismatch tones, these tones appear at , where i = 1, 2, … M - 1. A distinguishing feature of the timing skew tones is that they are frequency dependent because timing errors are more significant at higher frequen- cies, as illustrated in Fig. 6. To obtain an 8-bit dynamic range (50dB), at Nyquist for a 1GS/s time-interleaved ADC, ∆T must be less than 1ps. Figure 4) An FFT of a time-interleaved ADC’s output with M = 4 and Full Scale.VOS 1 2 8⁄±≤ 0 Frequency M ag ni tu de (d B ) -10 -20 -30 -40 -50 -60 0 fs/2fs/4 3fs/4 fs 8-bit SNR kfc fin± k fc fin± ifs M⁄ fin± SFDRG 20 A∆( )log= Figure 5) Effects of gain mismatches when M = 1, a) channel 1’s output, b) channel 2’s output, c) combined output. a) b) c) t t t fs/8 3fs/8 5fs/8 fc/4 3fc/4 5fc/4 C om bi ne d O ut pu t C ha nn el 1 ’s O ut pu t C ha nn el 2 ’s O ut pu t SFDRT 20 2π fin∆T( )log= ifs M⁄ fin± Figure 6) Timing skew spurious tones for a 500MSample/s interleaved ADC with M = 4 and |∆T| <10ps. 0 Frequency (MHz) -10 -20 -30 -40 -50 -60 0 125125 375 250 -70 -80 40MHz input 230MHz input tones due to 230MHz input tones due to 40MHz input 29112-1-3 Other mismatches Unlike offset, gain and timing skew mismatches most other mismatches are signal dependent. Bandwidth mismatches cause gain and timing skew mismatches that are frequency dependent [28]. To illustrate the problem, if the input to each sub-ADC of a 1GS/s ADC can be characterized as a first-order low-pass filter with a cutoff frequency of twice the Nyquist band , the resulting gain and timing skew mismatches, for M = 2, are as shown in Fig. 7. Note that the mismatches get worse at higher frequencies, such that the effective timing skew limits the SFDR to only 34dB. INL mismatches give rise to tones dependent on both frequency and signal size. Fortu- nately these tones are no worse than the spurious tones gener- ated in a sub-ADC acting alone, but at different spectral locations [8]. As one goes to higher resolutions and speeds these additional sources of mismatch become more significant. Up to this point, the discussion has largely focused on determining the spurious tones when two sub-ADCs are time- interleaved. When M is greater than 2, the number of spurious components increases and their amplitudes tend to decrease. Nevertheless, the SNR degradation due to the spurious tones remains independent of M [27]. Consequently, the various for- mulae given above can still be used to estimate the total degra- dation due to mismatches and time-interleaving. IV. DEALING WITH MISMATCHES As discussed above, mismatches between the sub-ADCs lead to spurious tones a in time-interleaved ADC’s output. For most systems, the offset gain and timing skew mismatches are the most significant. These mismatches are characterized by a constant or global mismatch for all signals, making them both relatively easy to detect and to correct. Other mismatches such as bandwidth differences and INL differences are both more difficult to characterize and to correct. Approaches for dealing with mismatches are discussed below. Offset mismatch Offset mismatches are one of the most significant sources of mismatch tones in time-interleaved ADCs. As a result, numerous circuit techniques and trimming methods have been developed to deal with offset mismatches. Circuit techniques can be used to both reduce the sources of offsets and to reduce the magnitude of the spurious tones due to any remaining offset mismatches. One particularly attractive option for offset mismatch reduction is to share potential sources of error and thereby eliminate the mismatch. For example, if M = 2, the comparators [30] and the op amps [31] [18] can be shared in pipelined ADCs. Now when M = 4, the offset tones only appear at fs/2, which is not a problem in many applications. Another common solution to offset problems in analog circuits is the use of chopping. Chopping effectively shifts the offset error to a higher, ideally out-of-band fre- quency. Unfortunately, if regular chopping is applied in time- interleaving applications, the offset is shifted to fc/2 which only causes more problems. An alternative is to use a random chop- ping sequence [15]. In this case the offset energy is splattered fairly uniformly across the noise floor. Unfortunately, the increased noise may be undesirable and the offsets still need to be trimmed to achieve the desired level of performance [15]. Offset mismatches can be trimmed in a variety of ways. The first part of any trimming operation is to obtain an estimate of the offset. While a simple offset can be estimated by short- ing the input and reading the digital output, this method is usu- ally inappropriate for time-interleaved ADCs. As discussed in Section III, the offsets must match to better than the resolution of the sub-ADC. Provided the sub-ADC is sufficiently noisy, averaging a number of offset samples will yield sub-LSB offset estimates. Unfortunately, if the sub-ADCs have INL errors, it is not the offset at zero but the average offset of the sub-ADC’s that is needed. The desired offset can be obtained during nor- mal operation of the time-interleaved ADC, by averaging the output of the ADC provided there is no input signal at dc or that is correlated with the chopping frequency [11]. Fortu- nately, randomly chopping, as shown in Fig. 8 solves both of these problems [15]. The measured offset can then be applied to correct the offset at the input of the ADC (after chopping) or by simply subtracting the offset from the digital output (before un-chopping). The analog solution maximizes the sub-ADC’s useful input range, while the digital solution is relatively trivial to implement. Note that the offset correction resolution must exceed the desired resolution of the ADC. Fortunately, these sub-LSB correction bits can be relatively noisy without signifi- 5%± Figure 7) Mismatches for a 5% bandwidth mismatch a) Gain mismatch b) Timing skew. fs/2 = 500MHz 1.0 0.5 0 0 G ai n M is m at ch (% ) Input Frequencya) fs/2 = 500MHz 6 3 0 0 Ti m in g Sk ew M is m at ch (p S) Input Frequencyb) 12 9 Figure 8) Random chopping within a sub-ADC channel. ADC Analog Input Integrate Offset Estimate Digital Output 29212-1-4 cantly impacting the overall performance of the time-inter- leaved ADC. Consequently, offset mismatches are no longer a significant problem in time-interleaved ADCs Gain mismatch The second easiest mismatches to deal with are gain mis- matches. Similar to offset mismatches, a variety of circuit tech- niques and trimming techniques have been developed to solve the gain mismatch problem. Appropriate circuit techniques for avoiding gain mis- matches depend on the architecture of the sub-ADCs. Since most ADCs’ full-scale range, or gain, is set by the reference, a shared reference eliminates this source of mismatch [32]. Unfortunately, a shared reference provides cross talk between the sub-ADCs. For switched-capacitor based successive approximation ADCs (SARs) and pipelined ADCs, the capaci- tor arrays in the sub-ADCs should be laid out identically and oriented the same way [32]. For pipelined ADCs, another potential gain mismatch is the finite op amp gain. This source of gain mismatch can be avoided by increasing the op amp gain [32]. Unfortunately, since the op amp gain required for good matching in an interleaved ADC exceeds that required by the basic accuracy of the sub-ADCs, an increased gain may lead to a reduced speed for the sub-ADCs. An alternative circuit technique to reducing spurious tones due to mismatches is to randomly interleave the sub-ADCs [33], [34]. As shown in Fig. 9, the use of a pseudo random, or some other sequence that avoids a repetitive use of the sub- ADCs effectively spreads the mismatch energy (from all sources of mismatch) over the ADC’s Nyquist band. Alterna- tively, the sequence can be designed to spread the energy from the mismatch tones away from a particular band of interest. To achieve effective randomization, only one additional sub-ADC is required [34]. While randomization improves the SFDR, the overall Signal-to-Noise-plus-Distortion Ratio, SNDR (or SINAD), ideally remains constant. Consequently for high SNDR applications, it is still necessary to trim the sub-ADCs. To trim the gain mismatch, it is first necessary to measure or estimate the gain mismatches. While the mismatches can be determined during manufacturing or during a calibration inter- val [3], due to parameter drift, it is preferable to estimate the mismatches during normal operation. If the characteristics of the input signal are known, this information can be used to greatly simplify the parameter estimation process [12]. Unfor- tunately, in most applications, the input signal’s characteristics are unknown. In this case there are three options for estimating the mismatches; Add a calibration signal to the input [11], use a redundant ADC [13], perform a “blind estimation” of the sig- nal [19]. When calibration signals are added, the input signal is filtered from the sub-ADCs’ outputs and the calibration signal is extracted with correlation techniques. While good results can be achieved, the calibration signal typically reduces the allow- able signal swing for the input signal. When redundant sub- ADCs are used, one sub-ADC is taken offline and calibrated at a time. If extreme care is not taken in this approach, additional spurious tones can be created due to changing loads on the