UCC28950组成的移相全桥开关电源电路

Application Report SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Michael O'Loughlin .......................................................................................................................... 1 Introduction In high-power server applications to meet high-efficiency and green standards some power-supply designers have found it easier to use a phase-shifted, full-bridge converter. This is because the phase-shifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converter reducing switching losses, and EMI and increasing overall efficiency. The purpose of this application report is to review the design of the 600-W, phase-shifted, full-bridge converter for one of these power systems, using TI’s new UCC28950 Phase-Shifted, Full-Bridge Controller, and was based on typical values. In a production design the values need to be modified for worst case conditions. Hopefully this information will aid other power supply designers in their efforts to design an efficient phase-shifted, full-bridge converter. Also note there is a MathCAD Design Tool, (TI Literature Number SLUC210), that goes along with this application note as well. Table 1. Design Specifications DESCRIPTION MIN TYP MAX Input Voltage 370 V (VINMIN) 390 V (VIN) 410 V (VINMAX) Output Voltage 11.4 V 12 V (VOUT) 12.6 V Allowable Output Voltage Transient 600 mV (VTRAN) Load Step, 90% Output Power 600 W (POUT) Full Load Efficiency 93% (η) Inductor (LOUT) Switching Frequency 200 kHz (fS) 1SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated V IN + _ CT Q B QE QF C IN R RE D A RS Q A Q D Q C T1 L OUT V OUT + _ C OUT UCC28950 OUTE RSUM COMP SS/EN SYNC VREF TMIN VDD OUTA OUTC OUTD OUTB GND EA+ DELCD DELEF EA- CS ADEL ADELEF OUTF DELAB DCM RT C BP1 R AR B R I R C C P R F C Z V OUT 1 2 3 4 5 6 7 8 9 10 11 12 OUTE 23 22 21 20 19 18 17 16 15 14 13 C SS R DELAB R DELCD R DELEF R TMIN R SUM R T R E OUTF OUTA OUTB OUTC OUTD 24 OUTA OUTB OUTC OUTD OUTE OUTF CS CS C LF 330pF R LF2 1k CBP2 1uF 12V Bias SYNC VREF VREF R G VREF L S R D 825k R LF1 22 ohm D B D C QB d QD d 1uF R DA1 R DA2 R CA1 R CA2 BUDGET OUT 1 P P 45.2W æ ö - h = ´ » ç ÷ h è ø Functional Schematic www.ti.com 2 Functional Schematic Figure 1. UCC28950 Phase-Shifted, Full-Bridge Functional Schematic 3 Power Budget To meet the efficiency goal a power budget needs to be set. (1) 2 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated P S N a1 N = RDSON V 0.3 V= P S N a1 N = ( )INMIN RDSON MAX OUT RDSON V 2 V D a1 21 V V - ´ ´ = » + a1 21= ( ) ( ) OUT RDSON TYP IN RDSON V V a D 0.66 V 2 V + ´ = » - ´ OUT LOUT OUT P 0.2 I 10 A V ´ D = = IN TYP MAG LOUT S V (1 D ) L 2.76mH I 0.5 f a1 ´ - ³ » D ´ ´ www.ti.com Preliminary Transformer Calculations (T1) 4 Preliminary Transformer Calculations (T1) Transformer turns ratio (a1): (2) Estimated FET voltage drop (VRDSON): (3) Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give some room for dropout if a PFC front end is used. (4) (5) Turns ratio rounded to the nearest whole turn. (6) Calculated typical duty cycle (DTYP) based on average input voltage. (7) Output inductor ripple current is set to 20% of the output current. (8) Care needs to be taken in selecting a transformer with the correct amount of magnetizing inductance (LMAG). The following equations calculate the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in current-mode control. If LMAG is too small the magnetizing current could cause the converter to operate in voltage mode control instead of peak-current mode control. This is because the magnetizing current is too large, it will act as a PWM ramp swamping out the current sense signal across RS. (9) 3SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated I PRIMAY 0A 0A I QF 0A I QE I PS I MS QE g On Off QF g On Off I PP I MP D I MP2 I MS2 ( )MP2 PP LOUTI I I / 2 a1» -D ´ MS2 PS LOUT I I I /2» -D LOUT I /2D Preliminary Transformer Calculations (T1) www.ti.com Figure 2 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents with respect to the synchronous rectifier gate drive currents. Note that IQE and IQF are also T1’s secondary winding currents as well. Variable D is the converters duty cycle. Figure 2. T1 Primary and QE and QF FET Currents 4 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated OUT LOUT PS OUT P I I 55 A V 2 D = + » OUT LOUT MS OUT P I I 45 A V 2 D = - » LOUT MS2 PS ΔI I I 50A 2 = - » ( ) 2 PS MSMAX SRMS1 PS MS I ID I I I 29.6 A 2 3 é ù - æ ö ê ú = ´ + » ç ÷ è ø ê ú ë û ( ) 2 PS MS2MAX SRMS2 PS MS2 I I1 D I I I 20.3 A 2 3 é ù - - æ ö ê ú = ´ + » ç ÷ è ø ê ú ë û LOUT MAX SRMS3 I 1 D I 1.1A 2 2 3 D - æ ö = » ç ÷ ´ è ø 2 2 2 SRMS SRMS1 SRMS2 SRMS3 I I I I 36.0 A= + + » INMIN MAX LMAG MAG S V D I 0.47 A L f ´ D = » ´ OUT LOUT PP LMAG OUT P I 1 I I 3.3 A V 2 a1 æ ö D = + + D » ç ÷ ´ h è ø ( ) ( ) 2 PP MP PRMS1 MAX PP MP I I I D I I 2.5 A 3 é ù - ê ú = ´ + » ê ú ë û LOUT MP2 PP I 1 I I 3.0 A 2 a1 D æ ö = - » ç ÷ è ø www.ti.com Preliminary Transformer Calculations (T1) Calculate T1 secondary RMS current (ISRMS): (10) (11) (12) Secondary RMS current (ISRMS1) when energy is being delivered to the secondary: (13) Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are both on. (14) Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling period, please refer to Figure 2. (15) Total secondary RMS current (ISRMS): (16) Calculate T1 Primary RMS Current (IPRMS): (17) (18) (19) (20) 5SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated ( ) ( ) 2 PP MP PRMS1 MAX PP MP I I I D I I 2.5 A 3 é ù - ê ú = ´ + » ê ú ë û ( ) ( ) 2 PP MP2 PRMS2 MAX PP MP2 I I I 1 D I I 1.7 A 3 é ù - ê ú = - ´ + » ê ú ë û 2 2 PRMS PRMS1 PRMS2 I I I 3.1A= + » a1 21= MAG L 2.8mH= LK L 4 H= m P DCR 0.215= W S DCR 0.58= W ( ) 2 2 T1 PRMS P SRMS S P 2 I DCR 2 I DCR 7.0 W» ´ ´ + ´ ´ » BUDGET BUDGET T1 P P P 38.1W= - » Preliminary Transformer Calculations (T1) www.ti.com T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary. (21) T1 Primary RMS (IPRMS2) current when the converter is free wheeling. (22) Total T1 primary RMS current (IPRMS) (23) For this design a Vitec transformer was selected part number 75PR8107 that had the following specifications. (24) (25) Measure leakage inductance on the Primary: (26) Transformer Primary DC resistance: (27) Transformer Secondary DC resistance: (28) Estimated transform losses (PT1) are twice the copper loss. NOTE: This is just an estimate and the total losses may vary based on magnetic design. (29) Calculate remaining power budget: (30) 6 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated ds(on)QA R 0.220= W OSS _ QA _ SPEC C 780pF= dsQA V 25 V= dsQA OSS _ QA _ AVG OSS _ QA _ SPEC INMAX V C C 193pF V = » g QA 15nC= g V 12V= 2 QA PRMS ds(on)QA g g fs P I R 2 QA V 2.1W 2 = ´ + ´ ´ ´ » BUDGET BUDGET QA P P 4 P 29.7 W= - ´ » www.ti.com QA, QB, QC, QD FET Selection 5 QA, QB, QC, QD FET Selection In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon were chosen for QA..QD. FET drain to source on resistance: (31) FET Specified COSS: (32) Voltage across drain-to-source (VdsQA) where COSS was measured, data sheet parameter: (33) Calculate average Coss [2]: (34) QA FET gate charge: (35) Voltage applied to FET gate to activate FET: (36) Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg): (37) Recalculate power budget: (38) 7SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated ( ) 2 INMAX S OSS _ QA _ AVG LK2 LOUTPP V L 2 C L 26 H II 2 2 a1 ³ ´ - » m D æ ö - ç ÷ ´ è ø S L 26 H= m LS DCR 27m= W 2 LS PRMS LS P 2 I DCR 0.5 W= ´ ´ » BUDGET BUDGET LS P P P 29.2W= - » Selecting LS www.ti.com 6 Selecting LS Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltage switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. The following equation selects LS to achieve ZVS at 100% load down to 50% load based on the primary FET’s average total COSS at the switch node. NOTE: There may be more parasitic capacitance than was estimated at the switch node and LS may have to be adjusted based on the actual parasitic capacitance in the final design. (39) For this design a 26-µH Vitec inductor was chosen for LS, part number 60PR964. The shim inductor had the following specifications. (40) LS DC Resistance: (41) Estimate LS power loss (PLS) and readjust remaining power budget: (42) (43) 8 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated OUT LOUT OUT P 0.2 600 W 0.2 I 10 A V 12V ´ ´ D = = » OUT TYP OUT LOUT s V (1 D ) L 2 H I f ´ - = » m D ´ 2 2 OUT LOUT LOUT _ RMS OUT P I I 50.3 A V 3 æ ö D æ ö = + = ç ÷ ç ÷ è ø è ø OUT L 2 H= m LOUT DCR 750= mW 2 LOUT LOUT _ RMS LOUT P 2 I DCR 3.8 W= ´ ´ » BUDGET BUDGET LOUT P P P 25.4 W= - » www.ti.com Output Inductor Selection (LOUT) 7 Output Inductor Selection (LOUT) Inductor LOUT was designed for 20% inductor ripple current (∆ILOUT): (44) (45) Calculate output inductor RMS current (ILOUT_RMS): (46) A 2-µH inductor from Vitec Electronics Corporation, part number 75PR108, was chosen for this design. The inductor had the following specifications. (47) Output inductor DC resistance: (48) Estimate output inductor losses (PLOUT) and recalculate power budget. Note PLOUT is an estimate of inductor losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It is advisable to double check the magnetic loss with the magnetic manufacture. (49) (50) 9SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated OUT OUT OUT HU OUT L P 0.9 V t 7.5 s V ´ ´ = = m TRAN COUT OUT OUT V 0.9 ESR 12m P 0.9 V ´ £ = W ´ OUT HU OUT OUT TRAN P 0.9 t V C 5.6mF V 0.1 ´ ´ ³ » ´ LOUT COUT _ RMS I I 5.8 A 3 D = » n 5= OUT C 1500 F n 7500 F= m ´ » m COUT 31m ESR 6.2m n W = = W 2 COUT COUT _ RMS COUT P I ESR 0.21W= ´ » BUDGET BUDGET COUT P P P 25.2W= - » Output Capacitance (COUT) www.ti.com 8 Output Capacitance (COUT) The output capacitor is being selected based on holdup and transient (VTRAN) load requirements. Time it takes LOUT to change 90% of its full load current: (51) During load transients most of the current will immediately go through the capacitors equivalent series resistance (ESRCOUT). The following equations are used to select ESRCOUT and COUT based on a 90% load step in current. The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output capacitance (COUT) is selected for 10% of VTRAN. (52) (53) Before selecting the output capacitance it is also required to calculate the output capacitor RMS current (ICOUT_RMS). (54) To meet our design requirements five 1500-µF, aluminum electrolytic capacitors were chosen for the design from United Chemi-Con, part number EKY-160ELL152MJ30S. These capacitors had an ESR of 31 mΩ. Number of output capacitors: (55) Total output capacitance: (56) Effective output capacitance ESR: (57) Calculate output capacitor loss (PCOUT): (58) Recalculate remaining Power Budget: (59) 10 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated g QE 152nC= ds(on)QE R 3.2m= W INMAX dsQE V V 19.5 V a1 = » ds _ spec V 25 V= OSS _ SPEC C 1810pF= dsQE OSS _ QE _ AVG OSS _ SPEC ds _ spec V C C 1.6nF V = » QE _ RMS SRMS I I 36.0 A= = www.ti.com Select FETs QE and QF 9 Select FETs QE and QF Selecting FETs for a design is always trial and error. To meet the power requirements of this design we selected 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs’ had the following characteristics. (60) (61) Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage in the design (VdsQE) that will be applied to the FET in the application. Voltage across FET QE and QF when they are off: (62) Voltage where FET COSS is specified and tested in the FET data sheet: (63) Specified output capacitance from FET data sheet: (64) Average QE and QF COSS [2]: (65) QE and QF RMS current: (66) 11SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated nCQE MINMILLER 52 _ » nCQE MAXMILLER 100_ » MILLER _ MAX QE 100nC» MILLER _ MIN QE 52nC» P I 4 A» r f P 100nC 52nC 48nC t t 24ns I 4A 22 - » = = » ( ) 2 2OUT s s s QE QE _ RMS ds(on)QE dsQE r f OSS _ QE _ AVG dsQE gQE gQE OUT P f f f P I R V t t 2 C V 2 Q V V 2 2 2 = ´ + ´ + + ´ ´ + ´ ´ QE P 9.3 W» BUDGET BUDGET QE P P 2 P 6.5 W= - ´ » Select FETs QE and QF www.ti.com To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at the end of the miller plateau (QEMILLER_MAX) for the given VDS. Figure 3. Vg vs. Qg for QE and QF FETs Maximum gate charge at the end of the miller plateau: (67) Minimum gate charge at the beginning of the miller plateau: (68) NOTE: The FETs in this design were driven with UCC27324 setup to drive 4-A (IP) of gate drive current. (69) Estimated FET Vds rise and fall time: (70) Estimate QE and QF FET Losses (PQE): (71) (72) Recalculate the power budget. (73) 12 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated R S OSS _ QA _ AVG 1 f 2 L (2 C ) = p ´ ´ DELAY R 2 t 314ns f 4 = » ´ CLAMP DELAY 1 D t fs 94% fs æ ö = - ´ = ç ÷ è ø CLAMP RDSON OUT RDSON DROP CLAMP 2 D V a1 (V V ) V 276.2V D æ ö ´ ´ + ´ + = = ç ÷ è ø www.ti.com Input Capacitance (CIN) 10 Input Capacitance (CIN) If this converter was designed for a 390-V input, which is generally fed by the output of a PFC boost pre-regulator. The input capacitance is generally selected based on holdup and ripple requirements. NOTE: The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP). Calculate tank frequency: (74) Estimated delay time: (75) Effective duty cycle clamp (DCLAMP): (76) VDROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator. (77) 13SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated ( ) OUT IN 2 2 IN DROP 1 2 P 60Hz C 364 F V V ´ ´ ³ » m - 2 2 OUT CINRMS PRMS1 INMIN P I I 1.8 A V a1 æ ö = - = ç ÷ ´ è ø IN C 330 F= m CIN ESR 0.150= W 2 CIN CINRMS CIN P I ESR 0.5 W= ´ = BUDGET BUDGET CIN P P P 6.0 W= - » Input Capacitance (CIN) www.ti.com CIN was calculated based on one line cycle of holdup: (78) Calculate high frequency input capacitor RMS current (ICINRMS). (79) To meet the input capacitance and RMS current requirements for this design we chose a 330-µF capacitor from Panasonic part number EETHC2W331EA. (80) This capacitor had a high frequency (ESRCIN) of 150 mΩ this was measured with an impedance analyzer at both 120 and 200 kHz. (81) Estimate CIN power dissipation (PCIN): (82) Recalculate remaining power budget: (83) There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the control device and all resistors supporting the control device. 14 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated P S I a2 100 I = = OUT LOUT INMAX MAX P1 OUT MAG s P I V D1 I 3.3 A V 2 a1 L f æ ö D ´ = + + » ç ÷ ´ h ´ è ø P V 2V= P S PEAK V 0.2V R 49.9 I 1.1 a2 - = » W ´ S R 48.7= W 2 PRMS1 RS S I P R 0.03 W a2 æ ö = ´ » ç ÷ è ø CLAMP DA P CLAMP D V V 29.8 V 1 D = » - OUT DA INMIN P 0.6 V P 0.01W V a2 ´ = » ´ h´ RE S R 100 R 4.87k= ´ = W www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA) 11 Setting Up the Current Sense Network (CT, RS, RRE, DA) The CT chosen for this design had a turn’s ratio (a2) of 100:1 (84) Calculate nominal peak current (IP1) at VINMIN: Peak primary current: (85) The voltage where peak current limit will trip. (86) Calculate current sense resistor (RS) and leave 200 mV for slope compensation: (87) Select a standard resistor for RS: (88) Estimate power loss for RS: (89) Calculate maximum reverse voltage (VDA) on DA: (90) Estimate DA power loss (PDA): (91) Calculate RS reset resistor RRE: Resistor RRE is used to reset the current sense transformer CT. (92) 15SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated LF R 1k= W LF C 330pF= LFP LF LF 1 f 482kHz 2 f R C = = p ´ ´ BP1 C 1 F= m REF V 5 V= V1 2.5 V= B R 2.37k= W ( )B REF A R V V1 R 2.37k V1 ´ - = = W C R 2.37k= W ( )c OUT I R V V1 R 9k V1 ´ - = » W ( )c OUT I R V V1 R 9.09k V1 ´ - = » W Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this design we chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work for most applications but maybe adjusted to suit individual layouts and EMI present in the design. (93) (94) (95) The UCC28950 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. T