W27C010P-70

W27C010 128K ´ 8 ELECTRICALLY ERASABLE EPROM Publication Release Date: August 1997 - 1 - Revision A2 GENERAL DESCRIPTION The W27C010 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 131072 ´ 8 bits that operates on a single 5 volt power supply. The W27C010 provides an electrical chip erase function. FEATURES · High speed access time: 70/150 nS (max.) · Read operating current: 30 mA (typ.) · Erase/Programming operating current: 1 mA (typ.) · Standby current: 5 mA (typ.) · Single 5V power supply · +14V erase/+12V programming voltage · Fully static operation · All inputs and outputs directly TTL/CMOS compatible · Three-state outputs · Available packages: 32-pin 600 mil DIP, 450 mil SOP and PLCC PIN CONFIGURATIONS A6 A5 A4 A3 A2 A1 A0 Q0 5 6 7 8 9 10 11 12 13 Q 1 Q 2 Q 4 Q 5 Q 6 1 4 4 3 2 1 3 2 3 1 3 0 A14 A13 A8 A9 OE A11 Q7 29 28 27 26 25 24 23 22 21 32-pin PLCC G N D 1 5 1 6 1 7 1 8 1 9 2 0 N C V c c CE A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Q5 OE A10 Q7 Q6 A13 A8 A9 A11 PGM NC Q0 A0 A2 A3 A4 A5 A6 A7 A12 A15 A16 A14 A1 VccVpp A 1 5 A 1 6 15 16 30 31 32 25 26 27 28 29 20 21 22 23 24 19 18 17 Q3 Q4 GND Q2 CE Q1 Q 3 A7 A 1 2 V p p / P G M BLOCK DIAGRAM CONTROL OUTPUT BUFFER DECODER CORE ARRAY Q0 Q7 . .CE OE A0 . . V GND CC A16 PGM VPP PIN DESCRIPTION SYMBOL DESCRIPTION A0-A16 Address Inputs Q0-Q7 Data Inputs/Outputs CE Chip Enable OE Output Enable PGM Program Enable VPP Program/Erase Supply Voltage VCC Power Supply GND Ground NC No Connection W27C010 - 2 - FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C010 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C010 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VHH (14V), A0 = VIL, and all other address pins equal VIL and data input pins equal VIH. Pulsing PGM low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIL, and OE = VIL, PGM = VIH. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing PGM low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIL, OE = VIL, and PGM = VIH. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the CE, the W27C010 may have common inputs. W27C010 Publication Release Date: August 1997 - 3 - Revision A2 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In standby mode, all outputs are in a high impedance state, independent of OE and PGM. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C010 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 mF ceramic capacitor connected between its VCC and GND. This high frequency, low inherent- inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 mF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL MODE PINS CE OE PGM A0 A9 VCC VPP OUTPUTS Read VIL VIL X X X VCC VCC DOUT Output Disable VIL VIH X X X VCC VCC High Z Standby (TTL) VIH X X X X VCC VCC High Z Standby (CMOS) VCC ±0.3V X X X X VCC VCC High Z Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCP VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VPE VCC VPE FF (Hex) Erase Verify VIL VIL VIH X X VCC VPE DOUT Erase Inhibit VIH X X X X VCP VPE High Z Product Identifier- manufacturer VIL VIL X VIL VHH VCC VCC DA (Hex) Product Identifier-device VIL VIL X VIH VHH VCC VCC 01 (Hex) W27C010 - 4 - DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Ambient Temperature with Power Applied -55 to +125 °C Storage Temperature -65 to +125 °C Voltage on all Pins with Respect to Ground Except VCC, VPP and A9 Pins -0.5 to VCC +0.5 V Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ±5%, VHH = 14V) PARAMETER SYM. CONDITIONS LIMITS UNI T MIN. TYP. MAX. Input Load Current ILI VIN = VIL or VIH -10 - 10 mA VCC Erase Current ICP CE = VIL, OE = VIH, PGM = VIL, A9 = VHH - - 30 mA VPP Erase Current IPP CE = VIL, OE = VIH, PGM = VIL, A9 = VHH - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Erase Voltage VID - 13.75 14.0 14.25 V VPP Erase Voltage VPE - 13.75 14.0 14.25 V VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP . W27C010 Publication Release Date: August 1997 - 5 - Revision A2 CAPACITANCE (Vcc = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0 to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level1.5V/1.5V Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA AC Test Load and Waveforms +1.3V 3.3K ohm 100 pF for 150 nS (Including Jig and Scope) D (IN914) OUT Input 3.0V 0V 1.5V Test Point Test Point 1.5V Output 30 pF for 70 nS (Including Jig and Scope) W27C010 - 6 - READ OPERATION DC CHARACTERISTICS (Vcc = 5.0V ±5%) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI VIN = 0V to VCC -5 - 5 mA Output Leakage CurrentILO VOUT = 0V to VCC -10 - 10 mA Standby VCC Current (TTL input) ISB CE = VIH - - 1.0 mA Standby VCC Current (CMOS input) ISB1 CE = VCC ±0.2V - 5 100 mA VCC Operating Current ICC CE = VIL IOUT = 0 mA f = 5 MHz - - 30 mA VPP Operating Current IPP VPP = VCC - - 10 mA Input Low Voltage VIL - -0.3 - 0.6 V Input High Voltage VIH - 2.2 - VCC +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V VPP Operating Voltage VPP - VCC -0.7 - VCC V READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 70° C) PARAMETER SYM. W27C010-70 W27C010-15 UNIT MIN. MAX. MIN. MAX. Read Cycle Time TRC 70 - 150 - nS Chip Enable Access Time TCE - 70 - 150 nS Address Access Time TACC - 70 - 150 nS Output Enable Access Time TOE - 30 - 65 nS OE High to High-Z Output TDF - 25 - 50 nS Output Hold from Address Change TOH 0 - 0 - nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP . W27C010 Publication Release Date: August 1997 - 7 - Revision A2 DC PROGRAMMING CHARACTERISTICS (Vcc = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI VIN = VIL or VIH - - 10 mA VCC Program Current ICP CE = VIL, OE = VIH, PGM = VIL - - 30 mA VPP Program Current IPP CE = VIL, OE = VIH, PGM = VIL - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V AC PROGRAMMING/ERASE CHARACTERISTICS (Vcc = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. LIMITS UNIT MIN. TYP. MAX. VPP Setup Time TVPS 2.0 - - mS Address Setup Time TAS 2.0 - - mS Data Setup Time TDS 2.0 - - mS PGM Program Pulse Width TPWP 95 100 105 mS PGM Erase Pulse Width TPWE 95 100 105 mS Data Hold Time TDH 2.0 - - mS OE Setup Time TOES 2.0 - - mS Data Valid from OE TOEV - - 150 nS OE High to Output High Z TDFP 0 - 130 nS Address Hold Time after PGM High TAH 0 - - mS Address Hold Time (Erase) TAHE 2.0 - - mS CE Setup Time TCES 2.0 - - mS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP . W27C010 - 8 - TIMING WAVEFORMS AC Read Waveform CE Outputs T High Z High Z Valid Output CE TOE TACC TOH TDF Address Address Valid VIL VIH VIH VIL VIH VIL OE Erase Waveform Address Read SID Device Read SID A9 = 12.0V Others = VIL A0 = VIL Data Chip Erase A9 = 14.0V Erase Verify Address Stable TAS DA 01 Data All One 14.0V 5.0V A0=VIH 5V Read Verify Blank Check Manufacturer Address Stable Address StableOthers=VIL Others = VIL TAS TAS TAHC TDS TDH TVPS TDFP DOUT DOUTDOUT TAH TACC VIH VIL VPP CE OE PGM TCE TOETOE TOES TOEVTPWE TCES TOE VIH VIL VIH VIL W27C010 Publication Release Date: August 1997 - 9 - Revision A2 Timing Waveforms, continued Programming Waveform Address Data 12.0V 5.0V CE Address Stable Program Read Verify Address Stable Address Valid Verify Data In Stable 5V Program DOUT TAH DOUTDOUT TDHTDS TVPS TCES TACC TDFPTAS VIH VIL VIH VIL VPP OE TOES TOEV TOE VIH VIL PGM TPWP VIH VIL W27C010 - 10 - SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X = 0 Increment X X = 25? Verify One Byte Last Address? Vcc = 5V Vpp = 5V Compare All Bytes to Original Data Pass Device Increment Address No Fail Yes Pass Fail Fail Fail Device Verify One Byte Program One 100 S Pulsem No Pass Yes Pass W27C010 Publication Release Date: August 1997 - 11 - Revision A2 SMART ERASE ALGORITHM Start Vcc = 5V Vpp = 14V Increment X Last Address? Vcc = 5V Vpp = 5V Compare All Bytes to FFs (HEX) Pass Device Increment Address No Fail Fail Fail Device X = 0 A9 = 14V; A0 = V Chip Erase 100 mS Pulse Address = First Location Erase Verify X = 20? No Yes Pass Pass Yes IL - 12 - ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX. (mA) PACKAGE W27C010-70 70 30 100 600 mil DIP W27C010-15 150 30 100 600 mil DIP W27C010S-70 70 30 100 450 mil SOP W27C010S-15 150 30 100 450 mil SOP W27C010P-70 70 30 100 32-pin PLCC W27C010P-15 150 30 100 32-pin PLCC Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. W27C010 Publication Release Date: August 1997 - 13 - Revision A2 PACKAGE DIMENSIONS 32-pin P-DIP Seating Plane eA 2 A a c E Base Plane 1 A 1e L A S 1 E D 1B B 32 1 16 17 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 6. General appearance spec. should be based on final visual inspection spec. Notes: 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 1.371.220.0540.048 Symbol Min. Nom. Max. Max.Nom.Min. Dimension in Inches Dimension in mm A B c D e A L S A A 1 2 E 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.5550.550 13.84 14.1013.97 17.02 15.2414.99 15.490.6000.590 0.610 2.29 2.54 2.790.090 0.100 0.110 B1 1 e E1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.6500.630 16.00 16.51 150 32-pin SO Wide Body 1 1732 16 y e D S Seating Plane b A A E H L L E E 1 c e1 1e A 2 See Detail F Detail F 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch and are determined at the mold parting line.. Notes: 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. 0.200.150.0080.006 Symbol Min. Nom. Max. Max.Nom.Min. Dimension in Inches Dimension in mm A b c D e HE L y A A L E 1 2 E 0.012 0.31 0.118 3.00 0.004 0.101 0.014 0.106 0.016 0.111 0.020 2.57 0.36 0.10 2.69 0.41 2.82 0.51 0.047 0.004 0 10 0.805 0.055 0.817 0.063 1.19 20.45 1.40 20.75 1.60 0.5560.5560.546 14.3814.1213.87 100 0.10 11.4311.3011.180.4500.4450.440 0.58 0.79 0.990.023 0.031 0.039 1.12 1.27 1.420.044 0.050 0.056 S 0.910.036 q q W27C010 - 14 - Package Dimensions, continued 32-Lead PLCC L c 1b 2A H E E e b D H D y A A1 Seating Plane EG G D 1 13 14 20 29 324 5 21 30 Notes: 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. q Symbol Min. Nom. Max. Max.Nom.Min. Dimension in Inches Dimension in mm A b c D e HE L y A A 1 2 E b 1 G D 3.56 0.50 2.802.67 2.93 0.710.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 HD GE 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.0950.0900.075 0.4950.4900.485 0.5950.5900.585 0.4300.4100.390 0.5300.5100.490 0.050 0.4530.4500.447 0.5530.5500.547 0.0140.0100.008 0.0220.0180.016 0.0320.026 0.028 0.1150.105 0.110 0.020 0.140 1.12 1.420.044 0.056 0° 10° 10°0° 0.10 2.41 q W27C010 Publication Release Date: August 1997 - 15 - Revision A2 VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 May. 1997 Initial Issued A2 Aug. 1997 1, 5, 6, 12 Add 70 nS bining Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Note: All data and specifications are subject to change without notice.