_______________General Description
The MAX517/MAX518/MAX519 are 8-bit voltage output
digital-to-analog converters (DACs) with a simple 2-wire
serial interface that allows communication between
multiple devices. They operate from a single 5V supply
and their internal precision buffers allow the DAC out-
puts to swing rail-to-rail.
The MAX517 is a single DAC and the MAX518/MAX519
are dual DACs. The MAX518 uses the supply voltage
as the reference for both DACs. The MAX517 has a ref-
erence input for its single DAC and each of the
MAX519’s two DACs has its own reference input.
The MAX517/MAX518/MAX519 feature a serial interface
and internal software protocol, allowing communication
at data rates up to 400kbps. The interface, combined
with the double-buffered input configuration, allows the
DAC registers of the dual devices to be updated indi-
vidually or simultaneously. In addition, the devices can
be put into a low-power shutdown mode that reduces
supply current to 4µA. Power-on reset ensures the DAC
outputs are at 0V when power is initially applied.
The MAX517/MAX518 are available in space-saving 8-
pin DIP and SO packages. The MAX519 comes in 16-
pin DIP and SO packages.
________________________Applications
Minimum Component Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Programmable Attenuators
____________________________Features
' Single +5V Supply
' Simple 2-Wire Serial Interface
' I2C Compatible
' Output Buffer Amplifiers Swing Rail-to-Rail
' Space-Saving 8-pin DIP/SO Packages
(MAX517/MAX518)
' Reference Input Range Includes Both Supply Rails
(MAX517/MAX519)
' Power-On Reset Clears All Latches
' 4µA Power-Down Mode
______________Ordering Information
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
________________________________________________________________ Maxim Integrated Products 1
1
2
3
4
8
7
6
5
OUT1 (REF0)
VDD
AD0
AD1SDA
SCL
GND
OUT0
MAX517
MAX518
DIP/SO
TOP VIEW
_________________Pin Configurations
INPUT
LATCH 0
OUTPUT
LATCH 0
START/STOP
DETECTOR
DAC0
INPUT
LATCH 1
8-BIT
SHIFT
REGISTER
OUT0
REF
REF
OUT1
MAX518
8
1
DECODE
ADDRESS
COMPARATOR
DAC1OUTPUT
LATCH 1
VDD
7
SCL
SDA
AD0 AD1
3
4
6 5
GND
2
________________Functional Diagram
Call toll free 1-800-998-8800 for free samples or literature.
19-0393; Rev 0; 5/95
PART
MAX517ACPA
MAX517BCPA
MAX517ACSA 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
8 Plastic DIP
8 Plastic DIP
8 SO
TUE
(LSB)
1
1.5
1
MAX517BCSA
MAX517BC/D 0°C to +70°C
0°C to +70°C 8 SO
Dice*
1.5
1.5
Ordering Information continued at end of data sheet.
*Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
( ) ARE FOR MAX517
Pin Configurations continued at end of data sheet.
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are TA = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
OUT_ ..........................................................-0.3V to (VDD + 0.3V)
REF_ (MAX517, MAX519)...........................-0.3V to (VDD + 0.3V)
AD_.............................................................-0.3V to (VDD + 0.3V)
SCL, SDA to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ...727mW
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C)........640mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) ......800mW
Operating Temperature Ranges
MAX51_C_ _ .......................................................0°C to +70°C
MAX51_E_ _.....................................................-40°C to +85°C
MAX51_MJB ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
±1MAX51 _BM
±1MAX51 _E
MAX51 _C
Full-Scale-Error Temperature Coefficient
Full-Scale-Error Supply Rejection
±1
mV
±10 µV/°C
MAX517, MAX519
Code = FF hex
VDD = +5V ±10%
Code = FF hex
±20MAX51 _E mV
MAX51 _C
±1MAX51 _BM
±1MAX51 _E
MAX51 _C
20MAX51 _BM
20MAX51 _E
MAX51 _C
MAX51 _A
PARAMETER SYMBOL MIN TYP MAX UNITS
Resolution 8 Bits
TUE
±1
Differential Nonlinearity (Note 1) DNL ±1 LSB
Zero-Code Error ZCE
18
mV
Zero-Code-Error Supply Rejection
±1
Zero-Code-Error Temperature Coefficient ±10 µV/°C
Full-Scale Error
±18
CONDITIONS
Guaranteed monotonic
Code = 00 hex
Code = 00 hex
Code = 00 hex
Code = FF hex,
MAX518 unloaded
mV
MAX51 _B ±1.5
Total Unadjusted Error (Note 1) LSB
±20MAX51 _BM
STATIC ACCURACY
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are TA = +25°C.)
0.6ISINK = 6mA
ISINK = 3mA
0.3VDD
Input High Voltage VIH 0.7VDD V
Input Leakage Current IIN ±10 µA
Output Low Voltage VOL
0.4
V
Three-State Leakage Current IL ±10 µA
Three-State Output Capacitance COUT 10
0V ≤ VIN ≤ VDD
VIN = 0V to VDD
(Note 6)
PARAMETER SYMBOL MIN TYP MAX UNITS
Output Leakage Current ±10 µA
CONDITIONS
OUT_ = 0V to VDD, power-down mode
pF
LSB
1.5
VIL
Input Hysteresis VHYST 0.05VDD V
Input Capacitance CIN 10 pF(Note 6)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Leakage Current IIN ±10 µAVIN = 0V to VDD
Voltage Output Slew Rate
2.0
Positive and negative V/µs
MAX51 _C
Output Settling Time µs
Digital Feedthrough 5Code = 00 hex, all digital inputs from 0V to VDD nV-s
1.4MAX51 _E
1.0MAX51 _M
Input Voltage Range 0 VDD V
Input Resistance RIN 16 24 kΩCode = 55 hex (Note 2)
Input Current ±10 µAPower-down mode
Input Capacitance 30 pFCode = FF hex (Note 3)
Channel-to-Channel Isolation
(MAX519)
-60(Note 4)
MAX51 _M, REF_ = VDD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
2.0
AC Feedthrough -70
dB
(Note 5)
MAX51 _C/E, REF_ = VDD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
Full-Scale Output Voltage 0 VDD V
Output Load Regulation
0.25OUT_ = 4V, 0mA to 2.5mA
6To 1/2 LSB, 10kΩ and 100pF load (Note 8)
DAC OUTPUTS
DIGITAL INPUTS SCL, SDA
DIGITAL INPUTS AD0, AD1, AD2, AD3
DIGITAL OUTPUT SDA (Note 7)
DYNAMIC PERFORMANCE
REFERENCE INPUTS (MAX517, MAX519)
dB
Input Low Voltage V
mA
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
4 _______________________________________________________________________________________
Note 1: For the MAX518 (full-scale = VDD) the last three codes are excluded from the TUE and DNL specifications, due to the limited
output swing when loaded with 10kΩ to GND.
Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
Note 4: VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 5: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex.
Note 6: Guaranteed by design.
Note 7: I2C compatible mode.
Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 10: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD.
Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Hold Time, (Repeated) Start Condition tHD, STA 0.6 µs
Low Period of the SCL Clock tLOW 1.3 µs
High Period of the SCL Clock tHIGH 0.6
PARAMETER SYMBOL MIN TYP MAX UNITS
Serial Clock Frequency fSCL 0 400 kHz
Bus Free Time Between a STOP and a
START Condition
tBUF 1.3 µs
CONDITIONS
µs
Setup Time for a Repeated START Condition tSU, STA 0.6 µs
Data Hold Time tHD, DAT 0 0.9 µs
Data Setup Time tSU, DAT 100
(Note 9)
ns
Fall Time of SDA Transmitting (Note 7) tF 20 + 0.1Cb 250 ns
Setup Time for STOP Condition tSU, STO 0.6 µs
Capacitive Load for Each Bus Line Cb 400
ISINK ≤ 6mA (Note 10)
pF
Rise Time of Both SDA and SCL Signals, Receiving tR 20 + 0.1Cb 300 ns
Fall Time of Both SDA and SCL Signals, Receiving tF 20 + 0.1Cb 300
(Note 10)
(Note 10) ns
Pulse Width of Spike Suppressed tSP 0 50(Notes 6, 11) ns
TIMING CHARACTERISTICS
(VDD = 5V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are TA = +25°C.)
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
Digital-Analog Glitch Impulse 12Code 128 to 127 nV-s
Signal to Noise + Distortion
Ratio (MAX517, MAX519)
SINAD 87
VREF_ = 4Vp-p at 1kHz, VDD = 5V,
Code = FF hex
dB
Multiplying Bandwidth
(MAX517, MAX519)
1 MHz
Wideband Amplifier Noise 60 µVRMS
Supply Voltage VDD 4.5 5.5 V
1.5 3.0
MAX517E/M
MAX517C
2.5 5
1.5 3.5
VREF_ = 4Vp-p, 3dB bandwidth
Supply Current
Normal mode, output(s)
unloaded, all digital inputs
at 0V or VDD
2.5 6
MAX518C, MAX519C
MAX518E/M, MAX519E/M
IDD
Power-down mode 4 20 µA
POWER REQUIREMENTS
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 5
10
0
0 0.5 1.5 2.5 3.0 3.5 4.0
FULL-SCALE ERROR vs. SOURCE CURRENT
(VREF = VDD)
2
8
M
AX
51
7-
01
OUTPUT SOURCE CURRENT (mA)
FU
LL
-S
CA
LE
E
RR
OR
(L
SB
)
1.0 2.0
6
4
VDD = VREF = 5V
DAC CODE = FF HEX
LOAD TO AGND
10
0
0 0.5 2.0
ZERO-CODE ERROR
vs. SINK CURRENT
2
8
M
AX
51
7-
02
OUTPUT SINK CURRENT (mA)
ZE
RO
-C
OD
E
ER
RO
R
(L
SB
)
1.0 1.5
6
4
VDD = VREF = 5V
DAC CODE = 00 HEX
LOAD to VDD
3.0
0
-55 -15 5-35 65 125
MAX517/MAX519 SUPPLY CURRENT
vs. TEMPERATURE
0.5
2.0
2.5
M
AX
51
7-
03
TEMPERATURE (°C)
SU
PP
LY
C
UR
RE
NT
(m
A)
4525 85 105
1.5
1.0
VDD = 5.5V
REF_ INPUTS = 0.6V
ALL DIGITAL INPUTS to VDD
MAX519, DAC CODE = FF HEX
MAX517, MAX519
DAC CODE = 00 HEX
MAX517, DAC CODE = FF HEX
3.0
3.5
0
-55 -35 -15 5 6545 125105
MAX518 SUPPLY CURRENT
vs. TEMPERATURE
0.5
2.0
2.5
M
AX
51
7-
04
TEMPERATURE (°C)
SU
PP
LY
C
UR
RE
NT
(m
A)
25 85
1.5
1.0
VDD = 5.5V
AD0, AD1 = VDD
DAC CODE = FF HEX
DAC CODE = 1B HEX
DAC CODE = 00 HEX
6
0
-55 -15-35 45 65 125
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
1
4
5
M
AX
51
7-
07
TEMPERATURE (°C)
SH
UT
DO
W
N
SU
PP
LY
C
UR
RE
NT
(µ
A)
255 85 105
3
2
VDD = 5.5V
ALL DIGITAL INPUTS to VDD
MAX518 SUPPLY CURRENT
vs. DAC CODE
M
AX
51
7-
05
DAC CODE (DECIMAL)
SU
PP
LY
C
UR
RE
NT
(m
A)
VDD = 5.5V
BOTH DACS SET
0
0
0.5
1.0
1.5
2.0
2.5
3.0
32 64 96 128 160 192 224 256
2.5
0
0 10.5 32.5 54.5
MAX517/MAX519 SUPPLY CURRENT
vs. REFERENCE VOLTAGE
0.5
1.5
2.0
M
AX
51
7-
08
REFERENCE VOLTAGE (V)
SU
PP
LY
C
UR
RE
NT
(m
A)
21.5 43.5
1.0
VDD = 5V
DAC CODE(S) FF HEX
MAX519
MAX517
0
1k 100k10k 1M 10M
MAX517/MAX519 REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
-16
M
AX
51
7-
09
FREQUENCY (Hz)
RE
LA
TI
VE
O
UT
PU
T
(d
B)
-12
-8
-4
VDD = 5V
VREF = SINE WAVE
CENTERED AT 2.5V
4VP-P SINE
2VP-P SINE
1VP-P SINE
0.5VP-P SINE
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = 00 HEX to FF HEX
1µs/div
POSITIVE FULL-SCALE STEP RESPONSE
OUT0
1V/div
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
6 _______________________________________________________________________________________
A = REF0, 1V/div (4VP-P)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 10kHz to 1MHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 100kHz
B
A
______________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
A = SCL, 400kHz, 5V/div
B = OUT0, 5mV/div
DAC CODE = 7F HEX
REF0 = 5V (MAX517/MAX519)
CLOCK FEEDTHROUGH
B
A
A = REF0, 1V/div (4VP-P)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 100Hz to 10kHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 1kHz
B
A
A = REF0, 1V/div (4VP-P)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 1kHz to 100kHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 10kHz
B
A
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = FF HEX to 00 HEX
1µs/div
NEGATIVE FULL-SCALE STEP RESPONSE
OUT0
1V/div
REF0 = 5V (MAX517/MAX519)
DAC CODE = 80 HEX to 7F HEX
500ns/div
WORST-CASE 1LSB STEP CHANGE
OUT0
20mV/div
AC COUPLED
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 7
Figure 1. MAX517/MAX519 Functional Diagram
_______________Detailed Description
Serial Interface
The MAX517/MAX518/MAX519 use a simple 2-wire
serial interface requiring only two I/O lines (2-wire bus)
of a standard microprocessor (µP) port. Figure 2 shows
the timing diagram for signals on the 2-wire bus.
Figure 3 shows a typical application. The 2-wire bus can
have several devices (in addition to the MAX517/
MAX518/MAX519) attached. The two bus lines (SDA and
SCL) must be high when the bus is not in use. When in
use, the port bits are toggled to generate the appropriate
signals for SDA and SCL. External pull-up resistors are
not required on these lines. The MAX517/MAX518/
MAX519 can be used in applications where pull-up resis-
tors are required (such as in I2C systems) to maintain
compatibility with existing circuitry.
The MAX517/MAX518/MAX519 are receive-only devices
and must be controlled by a bus master device. They
operate at SCL rates up to 400kHz. A master device
sends information to the devices by transmitting their
address over the bus and then transmitting the desired
information. Each transmission consists of a START
condition, the MAX517/MAX518/MAX519’s programm-
able slave-address, one or more command-byte/out-
put-byte pairs (or a command byte alone, if it is the last
byte in the transmission), and finally, a STOP condition
(Figure 4).
______________________________________________________________Pin Description
PIN
MAX517 MAX518 MAX519
NAME FUNCTION
1 1 1 OUT0 DAC0 Voltage Output
2 2 4 GND Ground
— — 5 AD3 Address Input 3; sets IC’s slave address
3 3 6 SCL Serial Clock Input
4 4 8 SDA Serial Data Input
— — 9 AD2 Address Input 2; sets IC’s slave address
5 5 10 AD1 Address Input 1; sets IC’s slave address
6 6 11 AD0 Address Input 0; sets IC’s slave address
7 7 12 VDD Power Supply, +5V; used as reference for MAX518
— — 13 REF1 Reference Voltage Input for DAC1
8 — 15 REF0 Reference Voltage Input for DAC0
— 8 16 OUT1 DAC1 Voltage Output
— — 2, 3, 7, 14 N.C. No Connect—not internally connected.
INPUT
LATCH 0
OUTPUT
LATCH 0
START/STOP
DETECTOR
DAC0
INPUT
LATCH 1
8-BIT
SHIFT
REGISTER
OUT0
REF0 (REF1)
(OUT1)
MAX517/MAX519
DECODE
ADDRESS
COMPARATOR
DAC1OUTPUT
LATCH 1
VDD
SCL
SDA
AD0 (AD2)
AD1 (AD3)
GND
MAX519 ONLY
( ) ARE FOR MAX519
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
8 _______________________________________________________________________________________
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low, with the exception of START and STOP condi-
tions. SDA’s state is sampled, and therefore must remain
stable while SCL is high. Data is transmitted in 8-bit
bytes. Nine clock cycles are required to transfer the data
bits to the MAX517/MAX518/MAX519. Set SDA low dur-
ing the 9th clock cycle as the MAX517/MAX518/MAX519
pull SDA low during this time. RC (see Figure 3) limits the
current that flows during this time if SDA stays high for
short periods of time.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 5). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
The Slave Address
The MAX517/MAX518/MAX519 each have a 7-bit long
slave address (Figure 6). The first three bits (MSBs) of
the slave address have been factory programmed and
are always 010. In addition, the MAX517 and MAX518
have the next two bits factory programmed to 1s. The
logic state of the address inputs (AD0 and AD1 on the
MAX517/MAX518; AD0, AD1, AD2, and AD3 on the
MAX519) determine the LSB bits of the 7-bit slave
address. These input pins may be connected to VDD or
DGND, or they may be actively driven by TTL or CMOS
logic levels. The MAX517/MAX518 have four possible
slave addresses and therefore a maximum of four of
MAX518
SDA SCL
µC
SDA
SCL
+5V
AD1
AD0
DUAL
DAC
MAX519
AD0
SDA
REF1
REF0
RC
1k SCL
+4V
+1V
AD2
AD1
DUAL
DAC
SDA
SCL
AD1
AD0
SINGLE
DAC
MAX517
AD3
OUT0 OFFSET ADJUSTMENT
OUT1 GAIN ADJUSTMENT
OUT0 BRIGHTNESS ADJUSTMENT
OUT1 CONTRAST ADJUSTMENT
REF0 +2.5V
OUT0 THRESHOLD ADJUSTMENT
Figure 3. MAX517/MAX518/MAX519 Application Circuit
SCL
SDA
tLOW
tHIGH
tFtR
tHD, STA
tHD, DAT
tHD, STA
tSU, DAT tSU, STA
tBUF
tSU, STO
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
Figure 2. Two-Wire Serial Interface Timing Diagram
M
A
X
5
1
7
/M
A
X
5
1
8
/M
A
X
5
1
9
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 9
these devices may share the bus. The MAX519 has 16
possible slave addresses. The eighth bit (LSB) in the
slave address byte should be low when writing to the
MAX517/MAX518/MAX519.
The MAX517/MAX518/MAX519 monitor the bus continu-
ously, waiting for a START condition followed by their
slave address. When a device recognizes its slave
address, it is ready to accept data.
The Command Byte and Output Byte
A command byte follows the slave address. Figure 7
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
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