si530

Rev. 1.1 6/07 Copyright © 2007 by Silicon Laboratories Si530/531 Si530/531 CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ) Features Applications Description The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram „ Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz „ 3rd generation DSPLL® with superior jitter performance „ 3x better frequency stability than SAW-based oscillators „ Internal fixed crystal frequency ensures high reliability and low aging „ Available CMOS, LVPECL, LVDS, and CML outputs „ 3.3, 2.5, and 1.8 V supply options „ Industry-standard 5 x 7 mm package and pinout „ Pb-free/RoHS-compliant „ SONET/SDH „ Networking „ SD/HD video „ Test and measurement „ Clock and data recovery „ FPGA/ASIC clock generation Fixed Frequency XO Any-rate 10–1400 MHz DSPLL® Clock Synthesis VDD CLK+CLK– OE GND Ordering Information: See page 7. Pin Assignments: See page 6. (Top View) Si5602 1 2 3 6 5 4GND OE VDD CLK+ CLK– NC 1 2 3 6 5 4GND NC VDD CLK NC OE 1 2 3 6 5 4GND NC VDD CLK+ CLK– OE Si530 (LVDS/LVPECL/CML) Si530 (CMOS) Si531 (LVDS/LVPECL/CML) REVISION D Si530/531 2 Rev. 1.1 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Units Supply Voltage1 VDD 3.3 V option 2.97 3.3 3.63 V2.5 V option 2.25 2.5 2.75 1.8 V option 1.71 1.8 1.89 Supply Current IDD Output enabled LVPECL CML LVDS CMOS — — — — 111 99 90 81 121 108 98 88 mA Tristate mode — 60 75 Output Enable (OE)2 VIH 0.75 x VDD — — V VIL — — 0.5 Operating Temperature Range TA –40 — 85 ºC Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE pin includes a 17 kΩ pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Units Nominal Frequency1,2 fO LVPECL/LVDS/CML 10 — 945 MHz CMOS 10 — 160 Initial Accuracy fi Measured at +25 °C at time of shipping — ±1.5 — ppm Temperature Stability1,3 –7 –20 –50 — — — +7 +20 +50 ppm Aging fa Frequency drift over first year — — ±3 ppm Frequency drift over 15 year life — — ±10 ppm Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Si530/531 Rev. 1.1 3 Total Stability Temp stability = ±7 ppm — — ±20 ppm Temp stability = ±20 ppm — — ±31.5 ppm Temp stability = ±50 ppm — — ±61.5 ppm Powerup Time4 tOSC — — 10 ms Table 3. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units LVPECL Output Option1 VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP LVDS Output Option2 VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP CML Output Option2 VO mid-level — VDD – 0.75 — V VOD swing (diff) 0.70 0.95 1.20 VPP CMOS Output Option3 VOH IOH = 32 mA 0.8 x VDD — VDD V VOL IOL = 32 mA — — 0.4 Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff) LVDS: 1.25 V (diff) CMOS: VDD/2 45 — 55 % Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Symbol Test Condition Min Typ Max Units Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Si530/531 4 Rev. 1.1 Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)* for FOUT > 500 MHz φJ 12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps 50 kHz to 80 MHz (OC-192) — 0.26 0.37 Phase Jitter (RMS)* for FOUT of 125 to 500 MHz φJ 12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps 50 kHz to 20 MHz (OC-192) — 0.34 0.42 *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Table 5. CLK± Output Period Jitter Parameter Symbol Test Condition Min Typ Max Units Period Jitter* JPER RMS — 2 — ps Peak-to-Peak — 14 — *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 6. CLK± Output Phase Noise (Typical) Offset Frequency (f) 120.00 MHz LVDS 156.25 MHz LVPECL 622.08 MHz LVPECL Units 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz –112 –122 –132 –137 –144 –150 n/a –105 –122 –128 –135 –144 –147 n/a –97 –107 –116 –121 –134 –146 –148 dBc/Hz Si530/531 Rev. 1.1 5 Table 7. Absolute Maximum Ratings1 Parameter Symbol Rating Units Maximum Operating Temperature TAMAX 85 ºC Supply Voltage VDD –0.5 to +3.8 Volts Input Voltage (any input pin) VI –0.5 to VDD + 0.3 Volts Storage Temperature TS –55 to +125 ºC ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 Volts Soldering Temperature (Pb-free profile)2 TPEAK 260 ºC Soldering Temperature Time @ TPEAK (Pb-free profile)2 tP 20–40 seconds Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Table 8. Environmental Compliance The Si530/531 meets the following qualification test requirements. Parameter Conditions/Test Method Mechanical Shock MIL-STD-883F, Method 2002.3 B Mechanical Vibration MIL-STD-883F, Method 2007.3 A Solderability MIL-STD-883F, Method 203.8 Gross & Fine Leak MIL-STD-883F, Method 1014.7 Resistance to Solvents MIL-STD-883F, Method 2016 Si530/531 6 Rev. 1.1 2. Pin Descriptions Table 9. Pinout for Si530 Series Pin Symbol LVDS/LVPECL/CML Function CMOS Function 1 OE (CMOS only)* No connection Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 OE (LVPECL,LVDS, CML)* Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled No connection 3 GND Electrical and Case Ground Electrical and Case Ground 4 CLK+ Oscillator Output Oscillator Output 5 CLK– Complementary Output No connection 6 VDD Power Supply Voltage Power Supply Voltage *Note: OE includes a 17 kΩ pullup resistor to VDD. Table 10. Pinout for Si531 Series Pin Symbol LVDS/LVPECL/CML Function 1 OE (LVPECL, LVDS, CML)* Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 No connection No connection 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK– Complementary output 6 VDD Power Supply Voltage *Note: OE includes a 17 kΩ pullup resistor to VDD. 1 2 3 6 5 4GND NC VDD CLK NC OE (Top View) 1 2 3 6 5 4GND OE VDD CLK+ CLK– NC 1 2 3 6 5 4GND NC VDD CLK+ CLK– OE Si530 LVDS/LVPECL/CML Si530 CMOS Si531 LVDS/LVPECL/CML Si530/531 Rev. 1.1 7 3. Ordering Information The Si530/531 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si530/531 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si530 and Si531 XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. The Si531 Series supports an alternate OE pinout (pin #1) for the LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si530 and Si531 series. Figure 1. Part Number Convention 53x X XXXMXXXX 1st Option Code VDD Output Format Output Enable Polarity A 3.3 LVPECL High B 3.3 LVDS High C 3.3 CMOS High D 3.3 CML High E 2.5 LVPECL High F 2.5 LVDS High G 2.5 CMOS High H 2.5 CML High J 1.8 CMOS High K 1.8 CML High M 3.3 LVPECL Low N 3.3 LVDS Low P 3.3 CMOS Low Q 3.3 CML Low R 2.5 LVPECL Low S 2.5 LVDS Low T 2.5 CMOS Low U 2.5 CML Low V 1.8 CMOS Low W 1.8 CML Low Note: CMOS available to 160 MHz. D G R Frequency (e.g., 622M080 is 622.080 MHz) Available frequency range is 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. The position of “M” shifts to denote higher or lower frequencies. If the frequency of interest requires greater than 6 digit resolution, a six digit code will be assigned for the specific frequency. Tape & Reel Packaging Blank = Trays Operating Temp Range (°C) G -40 to +85°C Part Revision Letter 530 or 531 XO Product Family Example P/N: 530AB622M080DGR is a 5 x 7 XO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply, LVPECL output, and Output Enable active high polarity. Temperature stability is specifed as ±20 ppm. The part is specified for –40 to +85 °C ambient temperature range operation and is shipped in tape and reel format. 2nd Option Code Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±) A 50 61.5 B 20 31.5 C 7 20 Si530/531 8 Rev. 1.1 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si530/531. Table 11 lists the values for the dimensions shown in the illustration. Figure 2. Si530/531 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.45 1.65 1.85 b 1.2 1.4 1.6 c 0.60 TYP. D 7.00 BSC. D1 6.10 6.2 6.30 e 2.54 BSC. E 5.00 BSC. E1 4.30 4.40 4.50 L 1.07 1.27 1.47 S 1.815 BSC. R 0.7 REF. aaa — — 0.15 bbb — — 0.15 ccc — — 0.10 ddd — — 0.10 Si530/531 Rev. 1.1 9 5. Si530/Si531 Mark Specification Figure 3 illustrates the mark specification for the Si530/Si531. Table 12 lists the line information. Figure 3. Mark Specification Table 12. Si53x Top Mark Description Line Position Description 1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number) 2 1–10 Si530, Si531: Option1 + Option2 + Freq(7) + Temp Si532, Si533, Si534, Si530/Si531 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant SiLabs 123 1 2 3 456 R T T T T Y W W + 1 2 3 4 5 6 7 8 9 0 Si530/531 10 Rev. 1.1 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si530/531. Table 13 lists the values for the dimensions shown in the illustration. Figure 4. Si530/531 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm) Dimension Min Max D2 5.08 REF e 2.54 BSC E2 4.15 REF GD 0.84 — GE 2.00 — VD 8.20 REF VE 7.30 REF X 1.70 TYP Y 2.15 REF ZD — 6.78 ZE — 6.30 Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). Si530/531 Rev. 1.1 11 DOCUMENT CHANGE LIST Revision 0.4 to Revision 0.5 „ Updated Table 1, “Recommended Operating Conditions,” on page 2. z Added maximum supply current specifications. z Specified relationship between temperature at startup and operation temperature. „ Updated Table 4, “CLK± Output Phase Jitter,” on page 4 to include maximum rms jitter generation specifications and updated typical rms jitter specifications. „ Added Table 6, “CLK± Output Phase Noise (Typical),” on page 4. „ Added Output Enable active polarity as an option in Figure 1, “Part Number Convention,” on page 7. Revision 0.5 to Revision 1.0 „ Updated Note 3 in Table 1, “Recommended Operating Conditions,” on page 2. „ Updated Figure 1, “Part Number Convention,” on page 7. Revision 1.0 to Revision 1.1 „ Updated Table 1, “Recommended Operating Conditions,” on page 2. z Device maintains stable operation over –40 to +85 ºC operating temperature range. z Supply current specifications updated for revision D. „ Updated Table 2, “CLK± Output Frequency Characteristics,” on page 2. z Added specification for ±20 ppm lifetime stability (±7 ppm temperature stability) XO. „ Updated Table 3, “CLK± Output Levels and Symmetry,” on page 3. z Updated LVDS differential peak-peak swing specifications. „ Updated Table 4, “CLK± Output Phase Jitter,” on page 4. „ Updated Table 5, “CLK± Output Period Jitter,” on page 4. z Revised period jitter specifications. „ Updated Table 7, “Absolute Maximum Ratings1,” on page 5 to reflect the soldering temperature time at 260 ºC is 20–40 sec per JEDEC J-STD-020C. „ Updated 3. "Ordering Information" on page 7. z Changed ordering instructions to revision D. „ Added 5. "Si530/Si531 Mark Specification" on page 9. Si530/531 12 Rev. 1.1 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. 1. Electrical Specifications Table 1. Recommended Operating Conditions Table 2. CLK± Output Frequency Characteristics Table 3. CLK± Output Levels and Symmetry Table 4. CLK± Output Phase Jitter Table 5. CLK± Output Period Jitter Table 6. CLK± Output Phase Noise (Typical) Table 7. Absolute Maximum Ratings1 Table 8. Environmental Compliance 2. Pin Descriptions Table 9. Pinout for Si530 Series Table 10. Pinout for Si531 Series 3. Ordering Information Figure 1. Part Number Convention 4. Outline Diagram and Suggested Pad Layout Figure 2. Si530/531 Outline Diagram Table 11. Package Diagram Dimensions (mm) 5. Si530/Si531 Mark Specification Figure 3. Mark Specification Table 12. Si53x Top Mark Description 6. 6-Pin PCB Land Pattern Figure 4. Si530/531 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm) Document Change List Contact Information << /ASCII85EncodePages false /AllowTransparency false /AutoPositionEPSFiles true /AutoRotatePages /All /Binding /Left /CalGrayProfile (Dot Gain 20%) /CalRGBProfile (sRGB IEC61966-2.1) /CalCMYKProfile (U.S. Web Coated \050SWOP\051 v2) /sRGBProfile (sRGB IEC61966-2.1) /CannotEmbedFontPolicy /Warning /CompatibilityLevel 1.4 /CompressObjects /Tags /CompressPages true /ConvertImagesToIndexed true /PassThroughJPEGImages true /CreateJDFFile false /CreateJobTicket false /DefaultRenderingIntent /Default /DetectBlends true /ColorConversionStrategy /LeaveColorUnchanged /DoThumbnails false /EmbedAllFonts true /EmbedJobOptions true /DSCReportingLevel 0 /EmitDSCWarnings false /EndPage -1 /ImageMemory 1048576 /LockDistillerParams false /MaxSubsetPct 100 /Optimize true /OPM 1 /ParseDSCComments true /ParseDSCCommentsForDocInfo true /PreserveCopyPage true /PreserveEPSInfo true /PreserveHalftoneInfo false /PreserveOPIComments false /PreserveOverprintSettings true /StartPage 1 /SubsetFonts true /TransferFunctionInfo /Apply /UCRandBGInfo /Preserve /UsePrologue false /ColorSettingsFile () /AlwaysEmbed [ true ] /NeverEmbed [ true ] /AntiAliasColorImages false /DownsampleColorImages true /ColorImageDownsampleType /Bicubic /ColorImageResolution 300 /ColorImageDepth -1 /ColorImageDownsampleThreshold 1.50000 /EncodeColorImages true /ColorImageFilter /DCTEncode /AutoFilterColorImages true /ColorImageAutoFilterStrategy /JPEG /ColorACSImageDict << /QFactor 0.15 /HSamples [1 1 1 1] /VSamples [1 1 1 1] >> /ColorImageDict << /QFactor 0.15 /HSamples [1 1 1 1] /VSamples [1 1 1 1] >> /JPEG2000ColorACSImageDict << /TileWidth 256 /TileHeight 256 /Quality 30 >> /JPEG2000ColorImageDict << /TileWidth 256 /TileHeight 256 /Quality 30 >> /AntiAliasGrayImages false /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages true /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict << /QFactor 0.15 /HSamples [1 1 1 1] /VSamples [1 1 1 1] >> /GrayImageDict << /QFactor 0.15 /HSamples [1 1 1 1] /VSamples [1 1 1 1] >> /JPEG2000GrayACSImageDict << /TileWidth 256 /TileHeight 256 /Quality 30 >