CD4033

7-826 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4033BMS CMOS Decade Counter/Divider Description CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display. This device is particularly advantageous in display applications where low power dissipation and/or low package count is important. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7 segment out- puts go high on selection. Features • High Voltage Types (20V Rating) • Decoded 7 Segment Display Outputs and Ripple Blanking • Counter and 7 Segment Decoding in One Package • Easily Interfaced with 7 Segment Display Types • Fully Static Counter Operation DC to 6MHz (typ.) at VDD = 10V • Ideal for Low-Power Displays • “Ripple Blanking” and Lamp Test • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Schmitt-Triggered Clock Inputs • Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, “Standard Specifications for Descrip- tion of “B” Series CMOS Device’s Applications • Decade Counting 7 Segment Decimal Display • Frequency Division 7 Segment Decimal Displays • Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/ Display • Counter/Display Driver For Meter Applications File Number 3301 December 1992 Pinout CD4033BMS TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLOCK CLOCK INHIBIT RIPPLE BLANKING IN RIPPLE BLANKING OUT CARRY OUT f VSS g VDD LAMP TEST c b e a d RESET Functional Diagram CLOCK b c d e f g CARRY OUT RIPPLE VSS VDD 1 10 12 13 9 11 6 7 5 16 8 a 4 7 D EC O DE D O UT PU TS BLK OUT 3 RIPPLE BLK IN 2 15 CLOCK INHIBIT RESET 14 LAMP TEST 7-827 CD4033BMS The CD4033BMS has provisions for automatic blanking of the non-significant zeros in a multi-digit decimal number which results in an easily readable display consistent with normal writing practice. For example, the number 0050.0700 in an eight digit display would be displayed as 50.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the CD4033BMS associated with the most significant digit in the display to a low-level voltage and connecting the RBO terminal of that stage to the RBI termi- nal of the CD4033BMS in the next-lower significant position in the display. This procedure is continued for each succeed- ing CD4033BMS on the interger side of the display. On the fraction side of the display the RBI of the CD4033BMS associated with the least significant bit is con- nected to a low-level voltage and the RBO of that CD4033BMS is connected to the RBI terminal of the CD4033BMS in the next more-significant-bit position. Again, this procedure is continued for all CD4033BMS’s on the frac- tion side of the display. In a purely fractional number the zero immediately preceding the decimal point can be displayed by connecting the RBI of that stage to a high level voltage (instead of to the RBO of the next more-significant-stage). For example: optional zero → 0.7346. Likewise, the zero in a number such as 763.0 can be displayed by connecting the RBI of the CD4033BMS associated with it to a high-level voltage. Ripple blanking of non-significant zeros provides an appre- ciable savings in display power. The CD4033BMS has a LAMP TEST input which, when con- nected to a high-level voltage, overrides normal decoder operation and enables a check to be made on possible dis- play malfunctions by putting the seven outputs in the high state. The CD4033BMS are supplied in these 16 lead outline pack- ages: Braze Seal DIP H4W Frit Seal DIP H2R Ceramic Flatpack H6W Logic Diagram FIGURE 1. CD4033BMS D Q CL Q R CL D Q CL Q R CL D Q CL Q R CL D Q CL Q R CL D Q CL Q R CL CL 1 2 *CLOCK *CLOCK INHIBIT 15* RESET *RBI 3 16 8 VDD GND 5 COUT (CLOCK ÷ 10) 4 7 6 11 9 13 12 10 a b c d e f g VDD VSS *ALL INPUTS PROTECTED BY CMOS INPUT PROTECTION NETWORK a b c d e f g SEGMENT DESIGNATIONS 14 *LAMP TEST RBO 7-828 Specifications CD4033BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE LIMITS UNITSMIN MAX Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA 2 +125oC - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VDD/2 VOL < VDD/2 V VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-829 Specifications CD4033BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE LIMITS UNITSMIN MAX Propagation Delay Clock To Carry Out TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns 10, 11 +125oC, -55oC - 675 ns Propagation Delay Clock To Decode Out TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 700 ns 10, 11 +125oC, -55oC - 945 ns Propagation Delay Reset To Carry Out TPLH3 VDD = 5V, VIN = VDD or GND 9 +25oC - 550 ns 10, 11 +125oC, -55oC - 743 ns Propagation Delay Reset To Decode Out TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns 10, 11 +125oC, -55oC - 810 ns Transition Time TTHL TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns Maximum Clock Input Frequency FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2.5 - MHz 10, 11 +125oC, -55oC 1.85 - MHz NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS UNITSMIN MAX Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA +125oC - 300 µA VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA +125oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA -55oC - -0.64 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA -55oC - -2.0 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA -55oC - -2.6 mA 7-830 Specifications CD4033BMS Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V Propagation Delay Clock To Carry Out TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 150 ns Propagation Delay Clock To Decode Out TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns Propagation Delay Reset To Carry Out TPLH3 VDD = 10V 1, 2, 3 +25oC - 240 ns VDD = 15V 1, 2, 3 +25oC - 160 ns Propagation Delay Reset To Decode Out TPHL4 TPLH4 VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns Transition Time TTHL TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 50 ns Maximum Clock Input Frequency FCL VDD = 10V 1, 2, 3 +25oC 5.5 - MHz VDD = 15V 1, 2, 3 +25oC 8 - MHz Minimum Reset Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 120 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 50 ns Minimum Reset Removal Time TREM VDD = 5V 1, 2, 3 +25oC - 30 ns VDD = 10V 1, 2, 3 +25oC - 15 ns VDD = 15V 1, 2, 3 +25oC - 10 ns Minimum Clock Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 220 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns Input Capacitance CIN Any Input 1, 2 +25oC - 7 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS UNITSMIN MAX Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VDD/2 VOL < VDD/2 V VDD = 3V, VIN = VDD or GND TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS UNITSMIN MAX 7-831 Specifications CD4033BMS Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11 Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS MIL-STD-883 METHOD TEST READ AND RECORD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9( Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD 9V ± -0.5V OSCILLATOR 50kHz 25kHz PART NUMBER Static Burn-In 1 (Note 1) 4 - 7, 9 - 14 1 - 3, 8, 15 16 Static Burn-In 2 (Note 1) 1, 2, 14, 15 3 - 6, 8, 10 - 13 7, 9, 16 Dynamic Burn- In (Note 1) - 2, 8, 15 3, 16 4 - 7, 9 - 13 1 Irradiation (Note 2) 4 - 7, 9 - 14 8 1 - 3, 15, 16 PART NUMBER CD4033BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS UNITSMIN MAX 7-832 Specifications CD4033BMS Static Burn-In 1 Note 1 4 - 7, 9 - 13 1 - 3, 8, 14, 15 16 Static Burn-In 2 Note 1 4 - 7, 9 - 13 8 1 - 3, 14 - 16 Dynamic Burn- In Note 1 - 2, 3, 8, 14, 15 16 4 - 7, 9 - 13 1 Irradiation Note 2 4 - 7, 9 - 13 8 1 - 3, 14 - 16 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Timing Diagram FIGURE 2. CD4033BMS TIMING DIAGRAM FIGURE 3. DETAIL OF TYPICAL FLIP-FLOP STAGE TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD 9V ± -0.5V OSCILLATOR 50kHz 25kHz 0 1 2 3 4 5 6 7 8 9 0 1 8 4 5 6 7 8 9 1 2 CLOCK RESET CLOCK INHIBIT LAMP TEST RBICOUT (CLOCK ÷ 10) a b c d e f g RBO p n CL CL p n CL CL p n CL CL p n CL CL CL CL CL Q R D Q D CL R Q Q ≡ 7-833 CD4033BMS Typical Performance Characteristics FIGURE 4. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 6. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FOR DECODED OUTPUTS FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FOR CARRY-OUT OUTPUTS 10V 5V AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 0 5 10 15 15 10 5 20 25 30 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) OU TP UT L OW (S INK ) C UR RE NT (IO L) (m A) 10V 5V AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 0 5 10 15 7.5 5.0 2.5 10.0 12.5 15.0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) OU TP UT L OW (S INK ) C UR RE NT (IO L) (m A) -10V -15V AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -20 -25 -30 0-5-10-15 OU TP UT H IG H (SO UR CE ) C UR RE NT (IO H) (m A) -10V -15V AMBIENT TEMPERATURE (TA) = +25oC 0 -5 -10 -15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15 OU TP UT H IG H (SO UR CE ) C UR RE NT (IO H) (m A) GATE-TO-SOURCE VOLTAGE (VGS) = -5V 15V AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 10V PR O PA G AT IO N DE LA Y TI M E (tP LH , tP HL ) ( µs ) 600 400 200 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 15V AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 10V PR O PA G AT IO N DE LA Y TI M E (tP LH , tP HL ) ( µs ) 300 200 100 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 7-834 CD4033BMS FIGURE 10. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 11. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY Light Emitting Diode Displays FIGURE 12. INTERFACING THE CD4033BMS WITH COMMERCIALLY AVAILABLE LIGHT EMITTING DIODE DISPLAYS Typical Performance Characteristics (Continued) M A XI M UM C LO CK IN PU T - F RE QU EN CY (f CL ) ( MH z) 20 15 10 5 0 2 4 6 8 10 12 14 16 AMBIENT TEMPERATURE (TA) = +25oC tr = tf = 20ns SUPPLY VOLTAGE (VDD) (V) 1 10 102 103 104 105 8642 8642 8642 8642 8642 INPUT PULSE FREQUENCY (fCL) (MHz) PO W ER D IS SI PA TI O N (P D) (µ W ) 105 104 103 102 10 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 15V 10V 10V (CL) = 15pF LOAD CAPACITANCE (CL) = 50pF CD4033BMS 7 SEGMENTS A G MAN 3 A IB VDD 1/7 CA3082 OR EQUIVALENT G IB R R IF G A CLOCK INHIBIT RESET MONSANTO MAN 3 OR EQUIVALENT (LOW POWER) VDD ≥ 3.5V IF ≈ 5mA/SEGMENT 100% DUTY CYCLE VP - VBE - VF(LED) ILED WHERE VP = INPUT PULSEVF = FORWARD DROP ACROSS DIODE VDD VSS R = CD4033BMS 7 SEGMENTS A G MAN 1 A IB VDD 1/7 CA3082 OR EQUIVALENT G IB R R IF G A CLOCK INHIBIT RESET MONSANTO MAN 1 OR EQUIVALENT VDD 5V (MIN) IB 0.4mA IF 12mA/Seg.(100% DUTY CYCLE) bdc(MIN) 30 ILED WHERE VF = FORWARD DROP ACROSS DIODE R R VCE(SAT) £ 0.5V VDD - VCE(sat)-VF(LED) VDD VSS R = 7-835 CD4033BMS FIGURE 13. INTERFACING THE CD4033BMS WITH COMMERCIALLY AVAILABLE 7-SEGMENT DISPLAY DEVICES* 7-Segment Display Devices INCANDESCENT READOUTS Numitron DR2000 Series TUBE REQUIREMENTS VT = 3.5 - 5V IT = 24mA Segment ASSUMED TRANSISTOR CHARACTERISTICS βdc (min) ≥ 25 VCE (sat) ≤ 0.5V VDD = 8V (min) IB = 1mA (min) IT = 24mA (min) CD4049UB at VCC = 10V (min) Vo “0” ≤ 2V IT = 8mA (min) VT ≈ 3.5V to 6V CD4049UB at VCC = 10V (min) Vo “0” ≤ 0.6V IT = 8mA (min) at VCC = 6V (min) Vo “0” ≤ 1V IT = 5mA (min) VT ≈ 1.5V to 3.5V LOW-POWER INCANDESCENT READOUTS PINLITES INC-Series O and R ASSUMED TRANSISTOR CHARACTERISTICS TUBE REQUIREMENTS 0-03-15 0-04-30 0-06-30 R-R3-20 R-R4-30 VT(V) 1.5 3 3 2 3 mA/Segment