SST39VF1601

www.DataSh Preliminary Specifications 16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 FEATURES: • Organized as 1M x16: SST39VF1601/1602 2M x16: SST39VF3201/3202 4M x16: SST39VF6401/6402 • Single Voltage Read and Write Operations – 2.7-3.6V • Superior Reliability – Endurance: 100,000 Cycles (Typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical) • Hardware Block-Protection/WP# Input Pin – Top Block-Protection (top 32 KWord) for SST39VF1602/3202/6402 – Bottom Block-Protection (bottom 32 KWord) for SST39VF1601/3201/6401 • Sector-Erase Capability • Security-ID Feature – SST: 128 bits; User: 128 bits • Fast Read Access Time: – 70 ns – 90 ns • Latched Address and Data • Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bits – Data# Polling • CMOS I/O Compatibility SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories eet4U.com ©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Chip-Erase Capability • Erase-Suspend/Erase-Resume Capabilities • Hardware Reset Pin (RST#) • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (6mm x 8mm) for 16M and 32M – 48-ball TFBGA (8mm x 10mm) for 64M PRODUCT DESCRIPTION The SST39VF160x/320x/640x devices are 1M x16, 2M x16, and 4M x16 respectively, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF160x/320x/640x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST39VF160x/320x/640x devices provide a typical Word- Program time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program opera- tion. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF160x/320x/640x devices are suited for appli- cations that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inher- ently use less energy during Erase and Program than alter- native flash technologies. The total energy consumed is a function of the applied voltage, current, and time of applica- tion. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technolo- gies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage appli- cations. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. www.DataSh Preliminary Specifications 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 To meet high density, surface mount requirements, the SST39VF160x/320x/640x are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 1 and 2 for pin assignments. Device Operation Commands are used to initiate the memory operation func- tions of the device. Commands are written to the device using standard microprocessor write sequences. A com- mand is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF160x/320x/640x also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39VF160x/320x/640x is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is dese- lected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Word-Program Operation The SST39VF160x/320x/640x are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, which- first. The Program operation, once initiated, will be com- pleted within 10 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform addi- tional tasks. Any commands issued during the internal Pro- gram operation are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST39VF160x/320x/640x offer both Sec- tor-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block- Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six- byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of- Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for tim- ing waveforms and Figure 23 for the flowchart. Any com- mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output eet4U.com 2 ©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03 ever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. www.DataSh Preliminary Specifications 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Chip-Erase Operation The SST39VF160x/320x/640x provide a Chip-Erase oper- ation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 9 for tim- ing diagram, and Figure 23 for the flowchart. Any com- mands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. Write Operation Status Detection The SST39VF160x/320x/640x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a Data# Poll- ing or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to pre- vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39VF160x/320x/640x are in the internal Program operation, any attempt to read DQ7 will produce ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase oper- ation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 20 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any con- secutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next opera- tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is ini- tiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart. Note: DQ7 and DQ2 require a valid address when reading status information. TABLE 1: WRITE OPERATION STATUS Status DQ7 DQ6 DQ2 Normal Operation Standard Program DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Erase- Suspend Mode Read from Erase-Suspended Sector/Block 1 1 Toggle Read from Non- Erase-Suspended Sector/Block Data Data Data Program DQ7# Toggle N/A T1.0 1223 eet4U.com 3 ©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03 the complement of the true data. Once the Program oper- ation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately follow- www.DataSh Preliminary Specifications 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Data Protection The SST39VF160x/320x/640x provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Hardware Block Protection The SST39VF1602/3202/6402 support top hardware block protection, which protects the top 32 KWord block of the device. The SST39VF1601/3201/6401 support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table 2. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 15). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Software Data Protection (SDP) The SST39VF160x/320x/640x provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Pro- gram operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. Dur- ing SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15- DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Common Flash Memory Interface (CFI) The SST39VF160x/320x/640x also contain the CFI infor- mation to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. TABLE 2: BOOT BLOCK ADDRESS RANGES Product Address Range Bottom Boot Block SST39VF1601/3201/6401 000000H-007FFFH Top Boot Block SST39VF1602 0F8000H-0FFFFFH SST39VF3202 1F8000H-1FFFFFH SST39VF6402 3F8000H-3FFFFFH T2.0 1223 eet4U.com 4 ©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03 www.DataSh Preliminary Specifications 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus SST39VF1601 / SST39VF3201 / SST39VF6401 SST39VF1602 / SST39VF3202 / SST39VF6402 Product Identification The Product Identification mode identifies the devices as the SST39VF1601, SST39VF1602, SST39VF3201, SST39VF3202, SST39VF6401, SST39VF6402, and manufacturer as SST. This mode may be accessed soft- ware operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 11 for the Software ID Entry and Read timing dia- gram and Figure 21 for the Software ID Entry command sequence flowchart. Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accom- plished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 13 for timing waveform, and Figures 21 and 22 for flowcharts. Security ID The SST39VF160x/320x/640x devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is pro- grammed and locked at SST with a random 128-bit num- ber. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by