首页 MG2040-D

MG2040-D

举报
开通vip

MG2040-D © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 1 1 Publication Order Number: MG2040/D MG2040 Transient Voltage Suppressors Low Capacitance ESD Protection for High Speed Video Interface The MG2040 transient voltage suppressor is de...

MG2040-D
© Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 1 1 Publication Order Number: MG2040/D MG2040 Transient Voltage Suppressors Low Capacitance ESD Protection for High Speed Video Interface The MG2040 transient voltage suppressor is designed specifically to protect HDMI and Display Port with full functionality ESD protection and back drive current protection for VCC line. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance for the high speed TMDS lines. Features • Full Function HDMI / Display Port Solution • Single Connect, Flow through Routing for TMDS Lines • Low Capacitance (0.35 pF Typical, I/O to GND) • Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 (±8 kV Contact) • UL Flammability Rating of 94 V−0 • This is a Pb−Free Device Typical Applications • HDMI • Display Port MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) ESD ESD ±15 ±15 kV kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. See Application Note AND8308/D for further description of survivability specs. MARKING DIAGRAM Device Package Shipping ORDERING INFORMATION UDFN18 CASE 517BV http://onsemi.com MG2040MUTAG UDFN18 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (*Note: Microdot may be in either location) 1 18 2040M� � 2040 = Specific Device Code M = Date Code � = Pb−Free Package MG2040 http://onsemi.com 2 1 2 3 4 5 6 7 8 9 10 11 18 17 16 15 14 13 12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND GND Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 15 Pin 17 Center Pins, Pin 12, 14, 16, 18 Note: Common GND – Only Minimum of 1 GND connection required Figure 1. Pin Schematic Figure 2. Pin Configuration = Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground. Only minimum of one pin needs to be connected to ground for functionality of all pins. MG2040 http://onsemi.com 3 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM I/O Pin to GND (Note 1) 5.0 V Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 V Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 1.0 �A Clamping Voltage (Note 1) VC IPP = 1 A, I/O Pin to GND (8 x 20 �s pulse) 10 V Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact See Figures 3 and 4 V Clamping Voltage TLP (Note 3) See Figures 8 through 11 VC IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 11.4 15.3 −4.6 −8.1 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 0.15 0.20 pF Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.35 0.42 pF 1. Surge current waveform per Figure 7. 2. For test procedure see Figures 5 and 6 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 �, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. Figure 3. IEC61000−4−2 +8 KV Contact Clamping Voltage Figure 4. IEC61000−4−2 −8 KV Contact Clamping Voltage TIME (ns) TIME (ns) V O LT A G E ( V ) V O LT A G E ( V ) −10 0 10 20 30 40 50 60 70 80 90 −20 0 20 40 60 80 100 120 140 −50 −40 −30 −20 −10 0 −20 0 20 40 60 80 100 120 140 MG2040 http://onsemi.com 4 IEC 61000−4−2 Spec. Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 Ipeak 90% 10% IEC61000−4−2 Waveform 100% I @ 30 ns I @ 60 ns tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec Figure 6. Diagram of ESD Clamping Voltage Test Setup 50 � 50 � Cable TVS OscilloscopeESD Gun The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. Figure 7. 8 X 20 �s Pulse Waveform 100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 t, TIME (�s) % O F P E A K P U LS E C U R R E N T tP tr PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 �s PEAK VALUE IRSM @ 8 �s HALF VALUE IRSM/2 @ 20 �s MG2040 http://onsemi.com 5 Figure 8. Positive TLP I−V Curve Figure 9. Negative TLP I−V Curve C U R R E N T ( A ) VOLTAGE (V) C U R R E N T ( A ) VOLTAGE (V) 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 −22 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 −18−16−14−12−10−8−6−4−20 Transmission Line Pulse (TLP) Measurement Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 10. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 11 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. Figure 10. Simplified Schematic of a Typical TLP System DUT L S ÷ Oscilloscope Attenuator 10 M� VC VMIM 50 � Coax Cable 50 � Coax Cable Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms MG2040 http://onsemi.com 6 With MG2040Without ESD Figure 12. HDMI1.4 Eye Diagram with and without MG2040. 3.4 Gb/s, 400 mVPP Figure 13. MG2040 Insertion Loss −10 −8 −6 −4 −2 0 2 4 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 FREQUENCY (Hz) S 21 IN S E R T IO N L O S S ( dB ) MG2040 IO−GND MG2040 http://onsemi.com 7 Figure 14. HDMI Layout Diagram 5V D2+ HPD (and HEC_DAT – HDMI1.4) GND SDA D1+ D1− GND MG2040 HDMI Type−A Connector Black = Top layer Red = other layer GND CEC GND N/C (or HEC_DAT – HDMI1.4) CLK+ CLK− GND D0+ D2− SCL D0− MG2040 http://onsemi.com 8 PACKAGE DIMENSIONS ÉÉ ÉÉ UDFN18, 5.5x1.5, 0.5P CASE 517BV ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. EXPOSED ENDS OF TERMINALS ARE ELECTRICALLY ACTIVE. DIM MIN MAX MILLIMETERS A 0.45 0.55 A1 0.00 0.05 A3 0.13 REF b 0.15 0.25 D 5.50 BSC D2 0.45 0.55 E 1.50 BSC eA 0.50 BSC L 0.20 0.40 0.10 C D E BA 2X 2X NOTE 4 A A1 (A3) 0.10 C PIN ONE REFERENCE 0.10 C 0.05 C C SEATINGPLANE BOTTOM VIEW beB 18X 0.10 B 0.05 AC C L SIDE VIEW TOP VIEW NOTE 3 1 11 1218 3X *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* DETAIL A L1 0.00 0.05 DIMENSION: MILLIMETERS RECOMMENDED L1 DETAIL A L OPTIONAL CONSTRUCTION ÉÉÉ ÉÉÉÇÇÇ DETAIL B MOLD CMPDEXPOSED Cu OPTIONAL CONSTRUCTION DETAIL B 0.50 1.80 0.60 0.50 PITCH eB 0.75 BSC 3X 0.30 18X E2 0.35 0.45 eA M M D2 E2 NOTE 5 END VIEW 0.75 PITCH 1.50 PITCH 18X 0.50 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MG2040/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
本文档为【MG2040-D】,请使用软件OFFICE或WPS软件打开。作品中的文字与图均可以修改和编辑, 图片更改请在作品中右键图片并更换,文字修改请直接点击文字进行修改,也可以新增和删除文档中的内容。
该文档来自用户分享,如有侵权行为请发邮件ishare@vip.sina.com联系网站客服,我们会及时删除。
[版权声明] 本站所有资料为用户分享产生,若发现您的权利被侵害,请联系客服邮件isharekefu@iask.cn,我们尽快处理。
本作品所展示的图片、画像、字体、音乐的版权可能需版权方额外授权,请谨慎使用。
网站提供的党政主题相关内容(国旗、国徽、党徽..)目的在于配合国家政策宣传,仅限个人学习分享使用,禁止用于任何广告和商用目的。
下载需要: 免费 已有0 人下载
最新资料
资料动态
专题动态
is_258178
暂无简介~
格式:pdf
大小:233KB
软件:PDF阅读器
页数:0
分类:互联网
上传时间:2011-11-16
浏览量:21