intel 80386SXSA

Copyright© INTEL Corporation, 2002 June 2002 Order Number: 272419-004 Intel386™ SXSA EMBEDDED MICROPROCESSOR The Intel386™ SXSA embedded microprocessor is a 5-volt, 32-bit, fully static CPU with a 16-bit external data bus and a 24-bit external address bus. The Intel386 SXSA CPU brings the vast software library of the Intel386 architecture to embedded systems. It provides the performance benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems. The Intel386 SXSA microprocessor is manufactured on Intel’s 0.8-micron CHMOS V process. This process provides high performance and low power consumption for power-sensitive applications. Figure 3 and Figure 4 illustrate the flexibility of low power devices with respect to temperature and frequency relationships. ■ Static Intel386™ CPU Core — Low Power Consumption — Operating Power Supply 4.5V to 5.5V - 25 and 33 MHz 4.75V to 5.25V - 40 MHz — Operating Frequency SA-40 = 40 MHz SA-33 = 33 MHz SA-25 = 25 MHz ■ Clock Freeze Mode Allows Clock Stopping at Any Time ■ Full 32-bit Internal Architecture — 8-, 16-, 32-bit Data Types — 8 General Purpose 32-bit Registers ■ Runs Intel386 Architecture Software in a Cost-effective, 16-bit Hardware Environment — Runs Same Applications and Operating Systems as the Intel386 SX and Intel386 DX Processors — Object Code Compatible with 8086, 80186, 80286, and Intel386 Processors ■ TTL-Compatible Inputs ■ High-performance 16-bit Data Bus — Two-clock Bus Cycles — Address Pipelining Allows Use of Slower, Inexpensive Memories ■ Integrated Memory Management Unit (MMU) — Virtual Memory Support — Optional On-chip Paging — 4 Levels of Hardware-Enforced Protection — MMU Fully Compatible with 80286 and Intel386 DX Processors ■ Virtual 8086 Mode Allows Execution of 8086 Software in a Protected and Paged System ■ Large Uniform Address Space — 16 Megabyte Physical — 64 Terabyte Virtual — 4 Gigabyte Maximum Segment Size ■ Numerics Support Intel387™ SX and Intel387™ SL Math Coprocessors ■ On-chip Debugging Support Including Breakpoint Registers ■ Complete System Development Support ■ High Speed CHMOS Technology ■ 100-Pin Plastic Quad Flatpack Package Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-ment of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. w w w .D at aS he et 4U .c om ww w. da tas he et4 u.c om Intel386™ SXSA EMBEDDED MICROPROCESSOR 2 Sta Fla ALU C Segmentation Unit Paging Unit Bus Control32 3-Input Barrel Shifter/ Adder Multiply/ Divide Register File Pro Te Effe Effectiv Figure 1. Intel386™ SXSA Microprocessor Block Diagram Decode and Sequencing Control ROM tus gs ALU ontrol Control Prefetcher/ Limit Checker 16-Byte Code Queue Code Stream 32 32 32 32 27 Instruction Prefetch Co nt ro l Ph ys ica l A dd re ss B us Adder Page Cache Control and Attribute PLA Instruction Decoder 3-Decoded Instruction Queue Instruction Predecode MUX/ Trans- ceivers Pipeline/ Bus Size Control Address Driver Request PrioritizerAdder Descriptor Register Limit and Attribute PLA Li ne ar A dd re ss B us D is pl ac em en t Bu s tection st Unit A2298-01 Internal Control Bus 32 Co de F et ch /P ag e Ta bl e Fe tc h ctive Address Bus e Address Bus Dedicated ALU Bus HOLD, RESET INTR, NMI ERROR# BUSY#,HLDA BLE#, BHE# A23:1 M/IO#, D/C# W/R#, LOCK# ADS#, NA# READY# D15:0 Intel386™ SXSA EMBEDDED MICROPROCESSOR 1.0 PIN ASSIGNMENT NOTE: NC = No Co D0 Vss HLDA HOLD Vss NA# READY# Vcc Vcc Vcc Vss Vss Vss Vss CLK2 ADS# BLE# A1 BHE# NC Vcc Vss M/IO# D/C# W/R# 1 2 ss cc 3 4 5 6 7 cc 8 9 10 11 12 ss cc 13 14 15 23 22 ss ss 21 3 Figure 2. Intel386™ SXSA Microprocessor Pin Assignment (PQFP) nnection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A20 A19 A18 A17 Vcc A16 Vcc Vss Vss A15 A14 A13 Vss A12 A11 A10 A9 A8 Vcc A7 A6 A5 A4 A3 A2 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 D D V V D D D D D V D D D D D V V D D D A A V V A LO CK # N C FL T# N C N C N C Vc c R ES ET BU SY # Vs s ER R O R# PE R EQ N M I Vc c IN TR Vs s Vc c N C N C N C N C N C Vc c Vs s Vs s TOP VIEW A2297-0A Intel386™ SXSA EMBEDDED MICROPROCESSOR 4 Table 1. Pin Assignment Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 D0 26 LOCK# 51 A2 76 A21 2 VSS 3 HLDA 4 HOLD 5 VSS 6 NA# 7 READ 8 VCC 9 VCC 10 VCC 11 VSS 12 VSS 13 VSS 14 VSS 15 CLK2 16 ADS# 17 BLE# 18 A1 19 BHE# 20 NC 21 VCC 22 VSS 23 M/IO# 24 D/C# 25 W/R# 27 NC 52 A3 77 VSS 28 FLT# 53 A4 78 VSS 29 NC 54 A5 79 A22 30 NC 55 A6 80 A23 31 NC 56 A7 81 D15 Y# 32 VCC 57 VCC 82 D14 33 RESET 58 A8 83 D13 34 BUSY# 59 A9 84 VCC 35 VSS 60 A10 85 VSS 36 ERROR# 61 A11 86 D12 37 PEREQ 62 A12 87 D11 38 NMI 63 VSS 88 D10 39 VCC 64 A13 89 D9 40 INTR 65 A14 90 D8 41 VSS 66 A15 91 VCC 42 VCC 67 VSS 92 D7 43 NC 68 VSS 93 D6 44 NC 69 VCC 94 D5 45 NC 70 A16 95 D4 46 NC 71 VCC 96 D3 47 NC 72 A17 97 VCC 48 VCC 73 A18 98 VSS 49 VSS 74 A19 99 D2 50 VSS 75 A20 100 D1 Intel386™ SXSA EMBEDDED MICROPROCESSOR 2.0 PIN DESCRIPTIONS Table 2 lists the Intel386 SXSA microprocessor pin descriptions. The following definitions are used in the pin descriptions: # The named I Input signal O Output sign I/O Input and ou P Power pin. G Ground pin. Symbol T A23:1 O ADS# O BHE# O BLE# O BUSY# I CLK2 I D/C# O D15:0 I ERROR# I FLT# I HLDA O HOLD I INTR I 5 signal is active low. . al. tput signal. Table 2. Pin Descriptions ype Pin Name and Function 80–79, 76–72, 70, 66–64 62–58, 56–51, 18 Address Bus outputs physical memory or port I/O addresses. 16 Address Status indicates that the processor is driving a valid bus-cycle definition and address onto its pins (W/R#, D/C#, M/IO#, BHE#, BLE#, and A23:1). 19 Byte High Enable indicates that the processor is transferring a high data byte. 17 Byte Low Enable indicates that the processor is transferring a low data byte. 34 Busy indicates that the math coprocessor is busy. 15 CLK2 provides the fundamental timing for the device. 24 Data/Control indicates whether the current bus cycle is a data cycle (memory or I/O) or a control cycle (interrupt acknowledge, halt, or code fetch). When D/C# is high, the bus cycle is a data cycle; when D/C# is low, the bus cycle is a con- trol cycle. /O 81–83, 86–90, 92–96, 99–100, 1 Data Bus inputs data during memory read, I/O read, and interrupt acknowledge cycles and outputs data during mem- ory and I/O write cycles. 36 Error indicates that the math coprocessor has an error condi- tion. 28 Float forces all bidirectional and output signals, including HLDA, to a high-impedance state. 3 Bus Hold Acknowledge indicates that the CPU has surren- dered control of its local bus to another bus master. 4 Bus Hold Request allows another bus master to request con- trol of the local bus. 40 Interrupt Request is a maskable input that causes the CPU to suspend execution of the current program and then exe- cute an interrupt acknowledge cycle. Intel386™ SXSA EMBEDDED MICROPROCESSOR 6 LOCK# O 26 Bus Lock prevents other system bus masters from gaining control of the system bus while it is active (low). M/IO# O NA# I NC NMI I PEREQ I READY# I RESET I W/R# O VCC P VSS G Table 2. Pin Descriptions (Continued) Symbol Type Pin Name and Function 23 Memory/IO indicates whether the current bus cycle is a mem- ory cycle or an input/output cycle. When M/IO# is high, the bus cycle is a memory cycle; when M/IO# is low, the bus cycle is an I/O cycle. 6 Next Address requests address pipelining. 20, 27, 29–31, 43–47 No Connection should always be left unconnected. Connect- ing a NC pin may cause the processor to malfunction or cause your application to be incompatible with future steppings of the device. 38 Nonmaskable Interrupt Request is a nonmaskable input that causes the CPU to suspend execution of the current pro- gram and execute an interrupt acknowledge function. 37 Processor Extension Request indicates that the math coprocessor has data to transfer to the processor. 7 Bus Ready indicates that the current bus cycle is finished and the external device is ready to accept more data from the pro- cessor. 33 Reset suspends any operation in progress and places the processor into a known reset state. 25 Write/Read indicates whether the current bus cycle is a write cycle or a read cycle. When W/R# is high, the bus cycle is a write cycle; when W/R# is low, it is a read cycle. 8–10, 21, 32, 39, 42, 48, 57, 69, 71, 84, 91, 97 System Power provides the nominal DC supply input. 2, 5, 11–14, 22 35, 41, 49–50, 63, 67–68, 77–78, 85, 98 System Ground provides the 0V connection from which all inputs and outputs are measured. Intel386™ SXSA EMBEDDED MICROPROCESSOR 3.0 DESIGN CONSIDERATIONS This section describes the Static Intel386 SXSA microprocessor instruction set, component and revision identifier, and package thermal specifica- tions. 3.1. Instruc The Static Intel3 same instruction microprocessor. microprocessor r dynamic Intel38 some instruction and the Static execution times Intel386 SX mic to the “Instructio in the Intel386™ (order number 24 3.2. Compo Identifi To assist user component ident register after res component iden identifies the Int nibble, 2H, iden Intel386 micropro The lower 8 bi identifier. The r chronologically that are intended distinction from identifier will tr whenever possib value is not gu stepping revision numerical seque intent of the revis required to be c over these char initial revision ide microprocessor i 3.3. Package Thermal Specifications Static Intel386 SXSA microprocessor is specified for operation with case temperature (TCASE) as specified in the “DC SPECIFICATIONS” on page 9. 7 tion Set 86 SXSA microprocessor uses the set as the dynamic Intel386 SX However, the Static Intel386 SXSA equires more clock cycles than the 6 SX microprocessor to execute s. Table 4 lists these instructions Intel386 SXSA microprocessor . For the equivalent dynamic roprocessor execution times, refer n Set Clock Count Summary” table SX Microprocessor data sheet 0187). nent and Revision er s, the microprocessor holds a ifier and revision identifier in its DX et. The upper 8 bits of DX hold the tifier, 23H. (The lower nibble, 3H, el386 architecture, while the upper tifies the second member of the cessor family.) ts of DX hold the revision level evision identifier will, in general, track those component steppings to have certain improvements or previous steppings. The revision ack that of the Intel386 CPU le. However, the revision identifier aranteed to change with every or to follow a completely uniform nce, depending on the type or ion or the manufacturing materials hanged. Intel has sole discretion acteristics of the component. The ntifier for the Static Intel386 SXSA s 09H. The case temperature can be measured in any environment to determine whether the micropro- cessor is within the specified operating range. The case temperature should be measured at the center of the top surface opposite the pins. An increase in the ambient temperature (TA) causes a proportional increase in the case temperature (TCASE) and the junction temperature (TJ). See Figures 3 and Figures 4 for case and ambient temperature relationships to frequency. A packaged device produces thermal resistance between junction and case temperatures (θJC) and between junction and ambient temperatures (θJA). The relationships between the temperature and thermal resistance parameters are expressed by these equations (P = power dissipated as heat = VCC × ICC): 1. TJ = TCASE + P × θJC 2. TA = TJ – P × θJA 3. TCASE = TA + P × [θJA – θJC] A safe operating temperature can be calculated from equation 1 by using the maximum safe TJ of 115° C, the maximum power drawn by the chip in the specific design, and the θJC value from Table 3. The θJA value depends on the airflow (measured at the top of the chip) provided by the system venti- lation. The θJA values are given for reference only and are not guaranteed. Table 3. Thermal Resistances (0°C/W) θJA, θJC Pkg θJC θJA versus Airflow (ft/min) 0 100 200 100 PQFP 5.1 46.0 44.8 41.2 Intel386™ SXSA EMBEDDED MICROPROCESSOR 8 Table 4. Intel386™ SXSA Microprocessor Instruction Execution Times (in Clock Counts) Instru Clock Count POPA IN: Fixed Port Variable Port OUT: Fixed Port Variable Port INS OUTS REP INS REP OUTS HLT MOV C0, reg NOTES: 1. The clock count v exception fault 13 Microprocessor d 2. n = the number of 3. When two clock c ction Virtual 8086 Mode (Note 1) Real Address Mode or Virtual 8086 Mode Protected Virtual Address Mode (Note 3) 28 35 27 28 14 15 7/29 8/29 27 28 14 15 7/29 9/29 30 17 9/32 31 18 10/33 31+6n (Note 2) 17+6n (Note 2) 10+6n/32+6n (Note 2) 30+8n (Note 2) 16+8n (Note 2) 10+8n/31+8n (Note 2) 7 7 10 10 alues in this column apply if I/O permission allows I/O to the port in virtual 8086 mode. If the I/O bit map denies permission, occurs; see clock counts for the INT 3 instruction in the “Instruction Set Clock Count Summary” table in the Intel386™ SX ata sheet (order number 240187). times repeated. ounts are listed, the smaller value refers to a register operand and the larger value refers to a memory operand. Intel386™ SXSA EMBEDDED MICROPROCESSOR 4.0 DC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS* Storage Temperature ................................ –65°C to +150°C Case Temperature Supply Voltage wi Voltage on Other OPERATING C VCC (Digital Suppl VCC (Digital Suppl TCASE minimum (C TCASE maximum . Operating Freque NOTICE: This document contains information on products in the sampling and initial production Symbol VIL Inp VIH Inp VILC CLK VIHC CLK VOL Ou VOH Ou ILI Inp (fo BU IIH Inp (P IIL Inp (B ILO Ou ICC Sup CL MH CL MH CL MH ICCF Sta CIN Inp COUT Ou CCLK CLK NOTES: 1. PEREQ input ha 2. BUSY#, FLT# an 3. ICC max measur 4. ICC typical and I 5. Not fully tested. 9 Under Bias ................. –65°C to +112°C th Respect to VSS ............... –0.5V to 6.5V Pins .......................... –0.5V to VCC + 0.5V ONDITIONS* y Voltage - 25 and 33 MHz) ...4.5V to 5.5V y Voltage - 40 MHz) ...........4.75V to 5.25V ase Temperature Under Bias) ......... 0°C ........................................ see Figure 4 ncy ................................ 0 MHz to 40 MHz phases of development. The specifications are sub- ject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 5. DC Characteristics Parameter Min. Max. Unit Test Condition ut Low Voltage –0.3 +0.8 V ut High Voltage 2.0 VCC + 0.3 V 2 Input Low Voltage –0.3 +0.8 V 2 Input High Voltage VCC – 0.8 VCC + 0.3 V tput Low Voltage 0.45 V IOL = 5 mA tput High Voltage 2.4 VCC – 0.5 V V IOH = –1 mA IOH = –0.2 mA ut Leakage Current r all pins except PEREQ, SY#, FLT#, ERROR#) ±15 µA 0 ≤ VIN ≤ VCC ut Leakage Current EREQ) 150 µA VIH = 2.4V (Note 1) ut Leakage Current USY#, FLT#, ERROR#) –120 µA VIL = 0.45V (Note2) tput Leakage Current ±15 µA 0.45V ≤ VOUT ≤ VCC ply Current K2 = 80 MHz, CLK = 40 z K2 = 66 MHz, CLK = 33 z K2 = 50 MHz, CLK = 25 z 275 225 175 mA mA mA (Notes 3, 4) typical = 200 mA typical = 175 mA typical = 140 mA ndby Current (Freeze Mode) 150 µA typical = 10 µA (Notes 3 4) ut Capacitance 10 pF FC = 1 MHz (Note 5) tput or I/O Capacitance 12 pF FC = 1 MHz (Note 5) 2 Capacitance 20 pF FC = 1 MHz (Note 5) s an internal weak pull-down resistor. d ERROR# inputs each have an internal weak pull-up resistor. ement at worst-case frequency, VCC, and temperature with reset active. CCF typical are measured at nominal VCC and are not fully tested. Intel386™ SXSA EMBEDDED MICROPROCESSOR 10 Figu T a re 3. Ambient Temperature vs. Frequency at Zero Air Flow and TJ = 115° C A2586-01 100 75 50 25 (˚C) Operating Frequency (MHz) 12 16 20 25 33 40 90 85 80 70 58 45 Intel386™ SXSA EMBEDDED MICROPROCESSOR 115 T (˚c 11 Figure 4. Case Temperature vs. Frequency at TJ = 115° C A2587-01 105 C) Operating Frequency (MHz) 12 16 20 25 33 40 110 112 111.5 111 110 108.5 107 Intel386™ SXSA EMBEDDED MICROPROCESSOR 12 5.0 AC SPECIFICATIONS Table 6 lists output delays, input setup require- ments, and input hold requirements. All AC specifi- cations are relative to the CLK2 rising edge crossing the 2.0V level. Figure 5 shows the measurement points for AC specifications. Inputs must be driven to the indicated voltage levels when AC specifications are measured. Output delays are specified with minimum and maximum limits measured as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct operation. Outputs ADS#, W/R#, D/C#, MI/O#, LOCK#, BHE#, BLE#, A23:A1 and HLDA change only at the beginning of phase one. D15:0 (write cycles) change only at the beginning of phase two. The READY#, HOLD, BUSY#, ERROR#, PEREQ, FLT# and D15:0 (read cycles) inputs are sampled at the beginning of phase one. The NA#, INTR and NMI inputs are sampled at the beginning of phase two. Intel386™ SXSA EMBEDDED MICROPROCESSOR Tx OUT (A23:1 BLE#,ADS# D/C#W/R#,L OUT ( IN (N/A IN (READY# FLT#,ER BUSY#,P LEGEN a - 1.5V b - 2.0V A - Ma B - Min C - Min D - Min PH1 PH2 13 Figure 5. Drive Levels and Measurement Points for AC Specifications A B Valid Output n+1 a a a a b Min Max C D CLK2 PUTS ,BHE# ,MI/O# OCK# HLDA) PUTS D15:0) PUTS #,INTR NMI) PUTS ,HOLD ROR# EREQ D15:0) D ximum Output Delay Spec imum Output Delay Spec imum Input Setup Spec imum Input Hold Spec 3.0V 0V Valid Output n A B Valid Output n+1 a a Min Max Valid Output n Valid Input a a C D 3.0V 0V Valid Input A2296-02 Intel386™ SXSA EMBEDDED MICROPROCESSOR 14 Table 6. AC Characteristics Symbol Parameter 40 MHz 33 MHz 25 MHz Test ConditionMin. Max. Min. Max . Min. Max. Op t1 CL t2a CL t2b CL t3a CL t3b CL t4 CL t5 CL t6 A2 t7 A2 t8 BH LO t9 BH LO t10 W/ AD t11 W/ AD t12 D1 Va t12a D1 Ho t13 D1 Flo t14 HL t15 NA t16 NA t19 RE t20 RE t21 D1 Tim NOTES: 1. Tested at maxim 2. These are not te 3. Float condition o 4. These inputs ma a specific CLK2 5. Minimum time no (ns) (ns) (ns) (ns) (ns) (ns) erating Frequency 0 40 0 33 0 25 MHz (Note 1) K2 Period 12.5 15 20 K2 High Time 4.5 6.25 7 (Note 2) K2 High Time 3.5 4 4 (Note 2) K2 Low Time 4.5 6.25 7 (Note 2) K2 Low Time 3.5 4.5 5 (Note 2) K2 Fall Time 4 4 7 (Note 2) K2 Rise Time 4 4 7 (Note 2) 3:1 Valid Delay 4 1