A Parallel LSI Architecture for LDPC Decoder Improving Message-Passing Schedule
Kazunori Shimizut Tatsuyuki Ishikawat Nozomu Togawatt Takeshi Ikenagat Satoshi Gotot
tGraduate School of Information, Production and Systems, Waseda University
ttDept. of Computer Science, Waseda University
2-7, Hibikino, Wakamatsu, Kitakyushu, 808-0135, Japan, Tel: +81-93-692-5298 Fax: +81-93-692-5298
E-mail: kazu@suou.wasedajp
Abstract- This paper proposes a parallel LSI architecture meet the requirement (2).) In the decoder shown in Ref. [6],
for LDPC decoder which improves a message-passing schedule. each column operation computes only a single message in
The proposed LDPC decoder is characterized as follows: (i) association with each row operation. However, the decoder
The column operations follow the row operations in a pipelined . .
architecture to ensure that the row and column operations are partitions the memory into a large number of memory banks.
performed concurrently. (ii) The proposed parallel pipelined bit (i.e. the decoder does not meet the requirement (3).)
functional unit enables the decoder to perform every column This paper proposes an efficient parallel LSI architecture
operation using the messages which is updated by the row for the LDPC decoder which meets the requirements (1), (2)
operations. These column operations can be performed without and (3) simultaneously. The proposed decoder is based on the
extending the single iterative decoding delay. Hardware imple-
mentation and simulation results show that the proposed decoder simple addressing and controller as shown in Refs. [2]-[4].
improves the decoding throughput and bit error performance Firstly, the proposed schedule performs the row operations
with a small hardware overhead. determining positions for the column operations. The column
operations are then performed at these positions. We propose
I. INTRODUCTION a pipelined architecture to ensure that the row and column
Low-Density Parity-Check (LDPC) code achieves informa- operations are performed concurrently. Secondly, we focus on
tion rates close to the Shannon limit by using the iterative the fact that the computational complexity of the column oper-
decoding algorithm called message-passing algorithm. Some ation is less than that of the row operation. In our schedule, the
work has been done on designing LDPC decoder in Refs. row and column operations are performed concurrently, as a
[2]-[6]. LDPC decoders are composed of a check functional result of which the column operations can be performed more
unit (CFU) and a bit functional unit (BFU), where the CFU frequently in a single iterative decoding. From this point of
performs row operations and the BFU performs column opera- view, the proposed parallel pipelined BFU enables the decoder
tions. The message-passing algorithm exchanges the messages to perform every column operation using the messages which
between the check and bit nodes iteratively. is updated by the row operations. These column operations can
The requirements to improve the decoding throughput and be performed without extending the single iterative decoding
bit error performance of the LDPC decoder are as follows: delay. In addition, our decoder architecture enables us to in-
(1) The single iterative decoding delay should be reduced crease the parallelism of the functional unit without increasing
by performing the row and column operations in parallel. the number of memory banks.
(2) The number of iterations until the decoding convergence Hardware implementation and simulation results show that
is reached should be reduced by improving the message- the proposed decoder improves the decoding throughput and
passing efficiency. The requirements (1) and (2) depend on the bit error performance with a small hardware overhead.
message-passing schedule. On the other hand, from a hardware
design point of view, (3) the message-passing schedule should II. HIGH-EFFICIENCY MESSAGE-PASSING SCHEDULE
not partition the memory into a large number of memory banks LDPC codes can be decoded iteratively using a message-
since presence of a large number of memory banks makes passing algorithm [1]. Each iteration of message-passing al-
layouts of VLSI circuit difficult [7]. gorithm is composed of two phases. Phase 1 is called row
The decoder shown in Refs. [2]-[4] enables the decoder to operation. This updates messages (a), and sends the messages
perform the row and column operations concurrently using to the column operations. Phase 2 called column operation
a dual memory architecture. Therefore, the single iterative updates messages (Q), and sends the messages to the row oper-
decoding delay is reduced [2],[3]. However, the message- ations. A partially-parallel LDPC decoder performs the Phase
passing efficiency is degraded since the row and column 1 and the Phase 2 partially in parallel. For the partially-parallel
operations are performed independently. (i.e. the decoder does LDPC decoder, the parity check matrix has to be structured
not meet the requirement (2).) On the other hand, in the in order to reuse the CFUs and BFUs [4]. Fig. 1 shows the
LDPC decoder shown in Refs. [5],[6], the row operations block-structured parity check matrix which is composed of
follow the column operations. The decoder shown in Ref. wc x w, sub-blocks', and can be applied to (wC, w)-regular
[5] is designed based on a single memory architecture. By LDPC codewords. This matrix enables the decoder to perform
approximating the column operation in this decoder, the single wc row operations and wr column operations in parallel.
iteratve deodingdelayand te numer ofmemor bank and Each sub-block in the parity check matrix is b x b square matrix, where
words can be reduced. However, the approximation degrades the diagonal line represents non-zero bits. The b X b square matrix is defined
the message-passing efficiency. (i.e. the decoder does not by shifting each row of the identity matrix 'b>
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