VHDL程序题

如有侵权，请联系网站删除，仅供学习与交流【精品文档】第PAGE11页VHDL程序 题 快递公司问题件快递公司问题件货款处理关于圆的周长面积重点题型关于解方程组的题及答案关于南海问题 1．以下是一位全加器的VHDL 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 ，试补充完整。libraryieee;--半加器设计useieee.std_logic_1164.all;entityh_adderisport(a,b:instd_logic;co,so:outstd_logic);endh_adder;architecturefh1ofh_adderisbeginso<=not(axor(notb));co<=aandb;endarchitecturefh1;libraryieee;--或门设计useieee.std_logic_1164.all;entityor2aisport(a,b:instd_logic;c:outstd_logic);endor2a;architecturertlofor2aisbeginc<=aorbafter10ns;endrt;libraryieee;--全加器设计useieee.std_logic_1164.all;entityf_adderISport(ain,bin,cin:instd_logic;cout,sum:outstd_logic);endentityf_adder;architecturefd1OFf_adderIScomponenth_adderport(a,b:instd_logic;co,so:outstd_logic);endcomponent;componentor2aport(a,b:instd_logic;c:outstd_logic);endcomponent;signald,e,f:std_logic;beginu1:h_adderportmap(a=>ain,b=>bin,co=>d,so=>e);u2:h_adderportmap(a=>e,b=>cin,co=>f,so=>sum);u3:or2aportmap(a=>d,b=>f,c=>cout);endarchitecturefd1;2．以下是含有使能端且具有同步清零的加减计数器的VHDL设计，试补充完整。libraryieee;useieee.std_logic_1164.all;entitycounterisport(updown,enable,clear,clk:instd_logic;q:outintegerrange0to255);endcounter;architectureaofcounterisbeginprocess(clk)variablecnt:integerrange0to（7）;variabledirection:（8）;beginif(updown='1')thendirection:=1;else（9）endif;if(clk'eventandclk='1')thenifclear='0'thencnt:=0;elseifenable='1'then（10）endif;endif;endif;q<=cnt;endprocess;enda;(7)255(8)integer(9)direction:=-1；(10)cnt:=cnt+direction1．以下是8位分频器程序设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPULSEISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);FOUT:OUTSTD_LOGIC);END;ARCHITECTUREoneOFPULSEISSIGNALFULL:STD_LOGIC;BEGINP_REG:PROCESS(CLK)VARIABLECNT8:STD_LOGIC_VECTOR(7DOWNTO0);BEGINIFCLK’EVENTANDCLK=‘1’THENIFCNT8="11111111"THENCNT8:=D;FULL<='1';ELSECNT8:=CNT8+1;FULL<='0';ENDIF;ENDIF;ENDPROCESSP_REG;P_DIV:PROCESS(FULL)VARIABLECNT2:STD_LOGIC;BEGINIFFULL'EVENTANDFULL='1'THENCNT2<=NOTCNT2;IFCNT2='1'THENFOUT<='1';ELSEFOUT<='0';ENDIF;ENDIF;ENDPROCESSP_DIV;END;1．根据如下原理图，将相应VHDL描述补充完整。Libraryieee;Useieee.std_logic_1164.all;EntityprojisPort(ain,bin,clk:instd_logic;Cout:（1）std_logic);Endproj;Architectureoneof（2）isSignalt1,t2:（3）;begin（4）Process(clk)beginIfclk’eventandclk=‘1’thent1<=bin;endif;Endprocess;Process(（5）)beginIf（6）thencout<=t2;endif;Endprocess;Endone;2．用元件例化语句设计如图3-1所示电路。LIBRARYieee;--底层2输入与非门USEieee.std_logic_1164.ALL;ENTITYnand2ISPORT(A1,B1:INstd_logic;C1:OUTstd_logic));ENDnand2;ARCHITECTUREa1OFnand2ISBEGINC1<=A1NANDB1;ENDa1;LIBRARYieee;--顶层设计USEieee.std_logic_1164.ALL;ENTITYyf4ISPORT(A,B,C,D:INstd_logic;Z:OUTstd_logic));ENDyf4;ARCHITECTUREaOFyf4ISCOMPONENTnand2PORT(A1,B1:INstd_logic;C1:OUTstd_logic));ENDCOMPONENT;SIGNALX,Y:std_logic;BEGINU1:nand2PORTMAP(A,B,X);U2:nand2PORTMAP(C,D,Y);U3:nand2PORTMAP(X,Y,Z);ENDa;1.根据如图3-1所示原理图将相应的VHDL程序补充完整。Libraryieee;Useieee.std_logic_1164.all;EntityyuanlituisPort(A,B,clk:instd_logic;Qout:outstd_logic);Endyuanltu;ArchitecturebehaveyuanlituisSignals1,s2,s3:std_logic;Begins3<=s1nands2;Process(clk)BeginIfclk’eventandclk=‘1’thens1<=A;s2<=B;Endif;Endprocess;Process(clk,s3)BeginIfclk=‘1’thenQout<=s3;Endif;Endprocess;Endbehave;1．以下VHDL程序实现和。其中有两处错误，指出错误位置并改正。01libraryieee;02useieee.std_logic_1164.all;03useieee.std_logic_unsigned.all;04entitytforis05port(clk:instd_logic;06data:inintegerrange0to1000000;07ma,mb:outintegerrange0to1000000);08endtfor;09architectureaoftforis10begin11process(clk,data)12variablem1,m2:integerrange0to1000000;13begin14m1:=0;15m2:=0;16ifclk='1'then17foriindata'rangeloop18ifi>=datathen20exit;21else22m1:=i+m1;23m2:=i+m2;24endif;25endloop;26ma<=m1;mb<=m2;27endif；28endprocess;29enda;18行，改为ifi>datathen23行，改为m2:=i*i+m2;1．8位二进制数判奇电路中有三处错误，指出错误位置并改正。01LIBRARYIEEE;02USEIEEE.STD_LOGIC_1164.ALL;03ENTITYp_checkIS04PORT(a:INSTD_LOGIC_VECTOR(7DOWNTO0);05y:OUTSTD_LOGIC);06ENDp_check;07ARCHITECTUREabcOFp_checkIS08BEGIN09PROCESS(a)10VARIABLEtmp:INTEGER;11VARIABLEn:INTEGER;12BEGIN13tmp:='0';14FORnin0TO7LOOP15tmp:=tmpXNORa(n);16ENDLOOP;17y<=tmp;18ENDPROCESS;19ENDabc;10行，改为VARIABLEtmp:STD_LOGIC;11行，去掉15行，改为tmp:=tmpXORa(n);2.以下是时钟设计中模24计数器的VHDL设计，试补充完整。其中有两处错误，指出错误位置并改正。01libraryieee;02useieee.std_logic_1164.all;03useieee.std_logic_unsigned.all;04entitycnt24is05port(clk,clr:instd_logic;06ten,one:outstd_logic_vector(3downto0);07co:outstd_logic);08end;09architectureoneofcnt24is10signalten_temp,one_temp:std_logic;11begin12process(clk,clr)13begin14ifclr='0'then15ten_temp<="0000";16one_temp<="0000";17elsifclk'eventandclk='1'then18iften_temp=2andone_temp=3then19ten_temp<="0000";20one_temp<="0000";21elsifone_temp=9then22one_temp<="0000";23ten_temp<=ten_temp+1;24elseone_temp<=one_temp+1;25endif;26endif;27endprocess;28ten<=ten_temp;29one<=one_temp;30co<='1'whenten_temp=2andone_temp=4else'0';31end;10行，改为signalten_temp,one_temp:std_logic_vector(3downto0);30行，改为co<='1'whenten_temp=2andone_temp=3else'0';2.已知一个简单的波形发生器的数字部分系统框图如下图所示：图中DOWNCNT、MYROM都是在QuartusII中使用MegaWizard调用的LPM模块，其VHDL描述中Entity部分分别如下：ENTITYDOWNCNTISPORT(clock:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(5DOWNTO0));ENDDOWNCNT;ENTITYmyromISPORT(address:INSTD_LOGIC_VECTOR(5DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDmyrom;该系统的顶层VHDL设计如下，其中有两处错误，指出错误位置并改正。01Libraryieee;02Useieee.std_logic_1164.all;03Entitymysgis04Port(clk:instd_logic;05To_da:outstd_logic_vector(7downto0));06Endmysq;07Architectureoneofmysqis08Signaladdr:std_logic_vector(5downto0);09ComponentDOWNCNT10Port(clock:instd_logic;11Q:outstd_logic_vector(5downto0));12Endcomponent;13Component14Port(address:instd_logic_vector(5downto0);15Q:outstd_logic_vector(7downto0));16Endcomponent;17Begin18U1:DOWNCNTportmap(clock=>clk,q=>addr);19U2:myromportmap(addr=>address,q=>to_da);20Endone;13行，改为Componentmyrom19行，改为U2:myromportmap(address=>addr,q=>to_da);