PIC单片机仿真实例大全CHAP11MEMORYPARMEM

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; PARMEM.ASM MPB Ver:1.0 6-9-05 ;............................................................... ; ; Parallel memory system ; Status: write working ; read not done ; ; PIC 16F877 operates with expansion memory RAM ; = 2 x 62256 32kb ; Control bits = Port B ; Data bus = Port C ; Address Bus = Port D ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; PROCESSOR 16F877 ; define MPU __CONFIG 0x3731 ; XT clock ; LABEL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; INCLUDE "P16F877.INC" ; Standard register labels ConReg EQU 06 ; Port B = Control Register DatReg EQU 07 ; Port C = Data Register AddReg EQU 08 ; Port D = Address Register HiAdd EQU 20 ; High address store CLK0 EQU 0 ; RAM0 address buffer clock CLK1 EQU 1 ; RAM1 address buffer clock SelRAM EQU 2 ; RAM select bit ResHi EQU 3 ; High address reset bit WritEn EQU 4 ; Write enable bit OutEn0 EQU 5 ; Output enable bit RAM0 OutEn1 EQU 6 ; Output enable bit RAM1 LED EQU 7 ; Memory error indicator ; Initialise ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ORG 0 ; Place machine code NOP ; Required for ICD mode BANKSEL TRISB ; Select bank 1 CLRF TRISB ; Control output bits CLRF TRISC ; Data bus initially output CLRF TRISD ; Address bus output BANKSEL AddReg ; Select bank 0 CLRF DatReg ; Clear outputs initially CLRF AddReg ; Clear outputs initially BCF ConReg,CLK0 ; RAM0 address buffer clock BCF ConReg,CLK1 ; RAM1 address buffer clock BCF ConReg,SelRAM ; Select RAM0 initially BCF ConReg,ResHi ; Reset high address latches BSF ConReg,OutEn0 ; Disable output enable RAM0 BSF ConReg,OutEn1 ; Disable output enable RAM1 BSF ConReg,WritEn ; Disable write enable bit BCF ConReg,LED ; Switch of error indicator ; MAIN LOOP ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; start CALL write ; test write to memory CALL read ; test read from memory SLEEP ; shut down ; Write checkerboard pattern to both RAMs ;;;;;;;;;;;;;;;;;;;;;;; write BSF ConReg,ResHi ; Enable address latches nexwrt MOVLW 055 ; checkerboard test data MOVWF DatReg ; output on data bus CALL store ; and write to RAM MOVLW 0AA ; checkerboard test data MOVWF DatReg ; output on data bus CALL store ; and write to RAM BTFSS ConReg,ResHi ; all done? RETURN ; yes - quit GOTO nexwrt ; no - next byte pair ; Check data stored ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; read NOP ; required for label BANKSEL TRISC ; select bank 1 MOVLW 0FF ; all inputs.. MOVWF TRISC ; ..at Port C BANKSEL ConReg ; select default bank 0 BSF ConReg,ResHi ; Enable address latches BCF ConReg,SelRAM ; select RAM0 BCF ConReg,OutEn0 ; set RAM0 for output CALL nexred ; check data in RAM0 BSF ConReg,SelRAM ; select RAM0 BCF ConReg,OutEn1 ; set RAM0 for output CALL nexred ; check data in RAM0 RETURN ; all done ; Load test data and check data ................................ nexred MOVLW 055 ; load even data byte CALL test ; check data MOVLW 0AA ; load odd data byte CALL test ; check data BTFSS ConReg,ResHi ; all done? RETURN ; yes - quit GOTO nexred ; no - next byte pair ; Write data to RAM ............................................. store BCF ConReg,SelRAM ; no - Select RAM0 BCF ConReg,WritEn ; negative pulse .. BSF ConReg,WritEn BSF ConReg,SelRAM ; Select RAM1 BCF ConReg,WritEn ; negative pulse .. BSF ConReg,WritEn ; ..write bit INCF AddReg ; next address BTFSC STATUS,Z ; last address? CALL inchi ; yes - increment high address RETURN ; no - next byte ; Test memory data .............................................. test MOVF DatReg,F ; read data SUBWF DatReg,W ; compare data BTFSS STATUS,Z ; same? BSF ConReg,LED ; no - switch on LED INCF AddReg ; yes - next address BTFSC STATUS,Z ; last address in block? CALL inchi ; yes - increment high address RETURN ; no - continue ; Select next block of RAM ...................................... inchi INCF HiAdd ; next block BTFSC STATUS,Z ; all done? GOTO alldon ; yes MOVF HiAdd,W ; no - load high address MOVWF AddReg ; output it BSF ConReg,CLK0 ; clock it into latches BSF ConReg,CLK1 BCF ConReg,CLK0 BCF ConReg,CLK1 CLRF AddReg ; reset low address to zero RETURN ; block done alldon BCF ConReg,ResHi ; reset address latches RETURN ; all blocks done END ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;