NG_NIC_VbPCI_FRD_EB7038228

ENGINEERING SPECIFICATION SECURITY NOTATION SPEC NO. EB7038228 X05 CAGE CODE 55939 REV LTR THIS TITLE PAGE CONTAINS PROPRIETARY AND DATA RIGHTS NOTATIONS. DOCUMENT TYPE CLASS INITIAL RELEASE DATE FORMDROPDOWN A DIVISION DEPARTMENT NO. PRODUCT LINE NO. CONTRACT NO. AES – BELL RD. 450444 6710       TITLE FPGA REQUIREMENTS DOCUMENT FOR the MAU NextGen NIC VbPCI MASTER FIELD PROGRAMMABLE GATE ARRAY PREPARED BY: DATE APPROVED BY TECHNICAL MANAGER DATE APPROVED BY ENGINEERING DEPARTMENT MANAGER DATE Y. Skaggs R. Skutecki             APPROVED FOR SCM DATE APPROVED FOR SQA DATE APPROVED BY:                                     REF AWAEB/PSAEB NO. CHECKER EIR PRODUCT DESIGN CHECKER (FOR REF, SPCL CONT PER HWEP-039) COGNIZANCE OF QE SUPVR (FOR REF, SPCL CONT PER HWEP-039) 7027848             FOR PAGE INDEX, SEE PAGE CR-2. REVISION RECORD FOLLOWS PAGE INDEX. THIS IS AN ELECTRONIC FACSIMILE OF THE ORIGINAL CR-1 ON FILE WITH DOCUMENT CONTROL. PROPRIETARY NOTICE THIS DOCUMENT AND THE INFORMATION DISCLOSED HEREIN ARE PROPRIETARY DATA OF HONEYWELL INTERNATIONAL INC. NEITHER THIS DOCUMENT NOR THE INFORMATION CONTAINED HEREIN SHALL BE REPRODUCED, USED, OR DISCLOSED TO OTHERS WITHOUT THE WRITTEN AUTHORIZATION OF HONEYWELL INTERNATIONAL INC. NOTICE FREEDOM OF INFORMATION ACT (5 USC 552) AND DISCLOSURE OF CONFIDENCE INFORMATION GENERALLY (18 USC 1905) THIS DOCUMENT IS BEING FURNISHED IN CONFIDENCE BY HONEYWELL INTERNATIONAL INC. THE INFORMATION DISCLOSED HEREIN FALLS WITHIN EXEMPTION (b) (4) OF 5 USC 552 AND THE PROHIBITIONS OF 18 USC 1905. Copyright 2008 HONEYWELL INTERNATIONAL INC. All Rights Reserved Title CR-1 - Page Index CR-2 - Revision Records CR-3 - Table of Contents i - ii - iii - iv - v - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 64 - 65 - 66 - 67 - 68 - 69 – 70 – 71 – 72 – 73 – 74 – 75 – 76 – 77 – 78 – 79 – 80 – 81 – 82 – 83 – 84 – 85 – Appendix A A-0 - A-1 - A-2 - A-3 - A-4 - A-5 - TOTAL PAGES: 91 X00 INITIAL RELEASE April 27, 2007 X01 Updated after review per Review Action Items Log June 12, 2007 X02 Incremental changes for initial HDL delivery Jan 2, 2008 X03 Verion reviewed on 8th Jan 2008 Janary 8,2008 X04 Updated with AIs from FCR_3973 April 23, 2008 X05 Updated with Actions from CR’s since version X03 September 1, 2008 A Table of Contents Title Page 11. INTRODUCTION 1.1 Scope 1 1.2 References 2 1.3 Acronyms and Abbreviations 2 1.4 Definitions 4 2. GENERAL DESCRIPTION 4 2.1 Level 0 Top Level Block Diagram 6 2.2 Level 1 Functional Block Diagram 7 3. DETAILED REQUIREMENTS 8 3.1 Trace Anchor Format 8 3.2 General Requirements 8 3.2.1 Device Selection 8 3.2.2 Device I/O Signal Definitions 9 3.3 Functional Requirements 23 3.3.1 Clock 23 3.3.2 Reset 23 3.3.2.1 Backplane VbPCI Bus 1 Reset Control 24 3.3.3 Monitors 25 3.3.3.1 Isolated Window Pulse Detector (IPD) 25 3.3.3.2 Power Monitors 26 3.3.4 PCI Busses 27 3.3.4.1 Configuration of PCI Busses 27 3.3.5 PCI Client Bus Interface 28 3.3.5.1 PCI Bus Operations and Address spaces 29 3.3.5.2 PCI Bus Data Path Access 32 3.3.5.3 PCI Data Bursting 33 3.3.5.4 PCI Bus Access latency 34 3.3.6 VbPCI Bus 1 Master Functions 35 3.3.6.1.1 VbPCI Memory Reads and Writes 38 3.3.6.1.2 VbPCI Bus 1 Configuration Reads and Writes 38 3.3.6.1.3 VbPCI Error Handling 40 3.3.6.2 VbPCI Bus Request/ Bus Arbitration 42 3.3.6.3 VbPCI Test Registers 42 3.3.6.4 VbPCI Bus 1 Last Transaction Registers 43 3.3.7 Aircraft Personality Module (APM) Interface 45 3.3.8 FPGA ID 49 3.3.9 Discrete Outputs 50 3.3.10 Discrete Inputs 55 3.3.11 Automatic DMA 59 3.3.12 NIC Dual-Port RAM Interface 67 3.3.12.1 DPRAM Arbitration 69 3.3.12.2 External DPRAM memory Interface timing 70 3.3.12.3 Internal DPRAM Interface 74 3.3.13 Real-Time Clock / Temperature Monitor Interface 75 3.3.14 Fan Monitor 81 3.3.14.1 Fan Monitor Requirements 82 3.3.15 Fault Containment Function (FCI) 83 3.3.16 JTAG and Programming 84 APPENDIX A TRACEABILITY INDEX 1 List of Figures 6Figure 1 – NG NIC VbPCI FPGA Top Level External Interface Block Diagram Figure 2 – NG NIC VbPCI Level 1 Functional Block Diagram 7 Figure 3 – FPGA Rev. Register format 50 Figure 4 – DPRAM Signal timing 71 Figure 5 – DPRAM Memory Read Cycle 72 Figure 6 – DPRAM Memory Write Cycle 73 Figure 7 – I2C Write Data Format 77 Figure 8 – I2C Read Data Format 78 Figure 9 – I2C Register Format 80 List of Tables 11Table 1 – NextGen NIC VbPCI Master FPGA Pin-out Table 2 – NG_NICVBPCI Clock Inputs 23 Table 3 – Local Power Supply Monitor Test Discrete Outputs 27 Table 4 – Supported PCI bus operations 30 Table 5 – NG_NICVBPCI FPGA PCI Memory Space Address Map 31 Table 6 – NG_NICVBPCI FPGA PCI I/O Space Address Map 31 Table 7 – PCI Configuration Space Accesses 32 Table 8 – PCI Burst Ordering 33 Table 9 – Required PCI Bus maximum access times 34 Table 10 – VbPCI Bus 1 Memory Map 37 Table 11 – PCI Bus Command Definitions 37 Table 12 – VbPCI Bus 1 I/O Address Map 38 Table 13 – CONFIG_ADDR Register 39 Table 14 – Translation of CONFIG_ADDR to VB_AD 40 Table 15 – VbPCI Bus 1 Test Memory Map 43 Table 16 – VbPCI Bus 1 Last Transaction Memory Map 44 Table 17 – VbPCI Bus 1 Last Command Register 44 Table 18 – VbPCI Bus 1 Last Address Register 44 Table 19 – APM Register Memory Map 46 Table 20 – APM Serial Data Out (SDO) Register 47 Table 21 – APM Serial Data In (SDI) Register 49 Table 22 – FPGA Revision Register Memory Map 49 Table 23 – Discrete Output Registers Memory Map 52 Table 24 – Discrete Outputs 53 Table 25 – Discrete Input Registers Memory Map 56 Table 26 – Lower Discrete Inputs Register Bit Definition 57 Table 27 – Upper Discrete Inputs and Fan Read/Set Status Register Bit Definition 58 Table 28 – Auto DMA Registers 60 Table 29 – Auto DMA Register Bit Definition 66 Table 30 – NIC DPRAM Arbitration Priority 69 Table 31 – RTC memory map 76 TITLE: FPGA REQUIREMENTS DOCUMENT FOR nEXT GEN NIC VbPCI MASTER FIELD PROGRAMMABLE GATE ARRAY 1. INTRODUCTION The Next Generation (NG) NIC VbPCI Master FPGA, referred to herein as the NG_NICVBPCI, is used on the Next Generation Network Interface Controller (NG_NIC) Circuit Card Assembly (CCA). This CCA performs three main functions. The first is to provide the Avionics Standard Communication Bus - rev. D (ASCB-D) interface, which is a multi-drop deterministic communication bus based on IEEE802.3, but with a proprietary physical layer. The second function is to act as the bus master for a backplane bus. The backplane bus is a passive bus designed to meet the timing and electrical requirements defined in the Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.1, revised to meet the Primus Epic® Virtual Backplane Network® requirements. This modified PCI interface is called Virtual backplane PCI (VbPCI). The third function is to provide Ethernet 10B2/100BTX LAN communications capability for all client modules within each EPIC MAU Cabinet. The NG_NIC CCA can be installed in the Modular Avionics Unit (MAU) Cabinet as a single NIC module or as a sub-assembly in a Dual NIC w/ PM-Processor module. A stand-alone NIC is able to access up to eight client modules on one VbPCI bus. When connected with a Pentium M -NIC card eight additional client modules can be accessed on a second VbPCI bus. The purpose of the NGNIC VbPCI Master FPGA is to provide the interface to the VbPCI backplane signals and the master timing to exchange data between the NIC and one or more client modules. The requirements for the NG_NIC VbPCI Master FPGA were derived from the Hardware Requirements Document for the Primus EPIC® Next Gen Dual NIC with Processor Module, EB 7037770, the Hardware Requirements Document for the Primus EPIC® -906 Next Gen NIC Core, EB7038227, and the Hardware Requirements Document for the Primus EPIC® Next Gen NIC CCA, EB7028226. 1.1 Scope This FPGA Requirements Document (FRD) will define all of the requirements for the Next Generation NIC VbPCI Master FPGA. Each requirement will be tagged with a trace anchor and contain the word shall. This document is also intended to function as a user’s guide for this FPGA. Therefore, commentary was included to better describe functions within the FPGA. Any text in this specification that is not identified as a requirement will be considered to be commentary. 1.2 References Ref. No. Document No. Title 1 EB7038226 Hardware Requirements Document for the Primus EPIC® NextGen NIC CCA, P/N 7037781-var, 7037782-var 2 EB7038227 Hardware Requirements Document for the Primus EPIC® NextGen NIC Core 3 EB7037770 Hardware Requirements Document for the Primus EPIC® NextGen Dual NIC w/ Proc Module, P/N 7038231-1901 4 EB7038229 FPGA Requirements Document for Next Gen NIC Core Resources Field Programmable Gate Array 5 EB7034444 FPGA Requirements Document for PM-NIC BIC Master Field Programmable Gate Array External: 6 PCI Local Bus Specification (June 1, 1995), Revision 2.1. 7 PCI Local Bus Specification (December 18, 1998), Revision 2.2. 8 Dallas Semi MaximDS3232 I2C RTC with Int. Crystal and SRAM Datasheet, Revision 2. 9 The I2C Bus Specification (January, 2000), Revision 2.1. 10 ProASIC3E Flash Family FPGAs Datasheet (April, 2006), version 2.1 (July 2007.) 1.3 Acronyms and Abbreviations ASCB-D Avionics Standard Communication Bus – rev. D ASIC Application Specific Integrated Circuit B Binary BIC Backplane Interface Controller BIT Built In Test BITE Built In Test Equipment BTM Branch Trace Messaging CCA Circuit Card Assembly CPU Central Processing Unit D Decimal DEOS Digital Engine Operating System DIN Discrete Input DMA Direct Memory Access DOUT Discrete Output DPRAM Dual-Port Random Access Memory EEPROM Electrically Erasable & Programmable Read Only Memory EOI End Of Interrupt FIFO First-In / First-Out FPGA Field Programmable Gate Array FRD FPGA Requirements Document GB Giga-Byte (1,073,741,824 Bytes) GND Ground H Hexadecimal HBM Heartbeat Monitor HRD Hardware Requirements Document H/W Hardware I2C Inter-Integrated Circuit (2-wire serial communication port) ID Identification I/O Input / Output JTAG Joint Test Advisory Group (industry standard test access port) KB kilo-Byte (1024 Bytes) MAU Modular Avionics Unit MB Mega-Byte (1,048,576 Bytes) Ms Millisecond (10-3 second) MSB Most Significant Byte/Most Significant Bit MTBF Mean Time Between Failure N/A Not Applicable NG Next Generation NIC Network Interface Controller Ns nanosecond (10-9 second) PCI Peripheral Component Interconnect PIC Programmable Interrupt Controller P/N Part Number Ppm Parts Per Million P/S Power Supply RAM Random Access Memory RTC Real-Time Clock RX Receive or Receiver SDRAM Synchronous Dynamic Random Access Memory SNIC Serial Network Interface Controller S/W Software TX Transmit or Transmitter Us microsecond (10-6 second) VbPCI Virtual Backplane PCI 1.4 Definitions Asserted – When referring to external or internal signals of the FPGA, an active-high signal is asserted when its value is 1. An active-low signal, which contains a “_n” (lower-case N) or “_N” or “#” suffix, is asserted when its value is 0. De-asserted – When referring to external or internal signals of the FPGA, an active-high signal is de-asserted when its value is 0. An active-low signal, which contains a “_n” (lower-case N) or “_N” or “#” suffix, is de-asserted when its value is 1. 2. GENERAL DESCRIPTION The NICVBPCI FPGA will perform the following functions: · Act as a PCI bus master to allow the NIC CPU to initiate transactions to all client modules connected to the VbPCI bus. · Monitor error signals during VbPCI transactions and send an interrupt to the NIC Core FPGA when an error is detected. · Capture the VbPCI address and control values on each VbPCI transaction in case an error occurs. · Support broadcast writes to multiple VbPCI clients. · Use an automatic DMA function to fetch data from the NIC DPRAM for transfer on the VbPCI bus or to read data from the VbPCI bus and store it in the NIC DPRAM. · Provide Discrete Inputs (DINs) and Discrete Outputs (DOUTs) used to support both internal and external functions. · Provide a Local Bus PCI interface for access by the CPU · Provide arbitration of accesses to the left port of the NIC DPRAM by the CPU, the PCI bus 1 master, and the PCI bus 2 master function in the PM-NIC VbPCI Master FPGA (if dual NIC mezzanine card installed). · Monitor pulses from the cabinet cooling fans and determine if the fans have dropped below a certain speed. · Support CPU accesses to an external temperature monitor. · Support CPU accesses to an external real-time clock. · Provide an FPGA ID byte that can be read by the CPU. · Tri-state all outputs when a test input is asserted to support In-Circuit Test. · Function as a PCI target device on PCI Bus 0. · Provide power supply (P/S) test bus interface. · Provide VbPCI Bus 1 backplane reset control. · Provide an interface to the DPRAM. · Provide fan control and fan tachometer functions. Refer to Figure 1 for a top-level interface block diagram and Figure 2 for functional block diagrams. 2.1 Level 0 Top Level Block Diagram Figure 1 – NG NIC VbPCI FPGA Top Level External Interface Block Diagram 2.2 Level 1 Functional Block Diagram Figure 2 – NG NIC VbPCI Level 1 Functional Block Diagram 3. DETAILED REQUIREMENTS The following sections will provide detailed requirements and implementation data on the various functions of the NIC VbPCI Master FPGA. 3.1 Trace Anchor Format As the FRD identifies requirements that must be fulfilled by detailed hardware design and verification, these requirements will be tagged with a trace anchor. This allows other documents to trace to the defined requirement. The trace anchor identifies the requirement, while the trace-up pointer identifies the source of the requirement. The format for a trace anchor is shown below: Trace Anchor>Trace-up Pointer The Trace-up Pointer identifies the higher-level requirement that the Trace Anchor is satisfying. If there is no higher-level requirement then the Trace-up Pointer will contain the word “derived”. The actual Trace Anchor format is shown below: FRD_NGNICVBPCI_aaaa_nnnn The prefix FRD_NGNICVBPCI identifies that the requirement pertains to this FRD. The “aaaa” field contains a unique sub-function descriptor (not limited to four characters). The “nnnn” field contains a unique 4-digit number for each requirement in this document. 3.2 General Requirements 3.2.1 Device Selection [FRD_NGNICVBPCI_IO_0010>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0010>DERIVED" ] The NG_NICVBPCI functions shall be implemented in a Flash based, Live on Power-up, FPGA technology device. [FRD_NGNICVBPCI_IO_0020>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0020>DERIVED" ] The NG_NICVBPCI FPGA shall be In System Programmable (ISP). [FRD_NGNICVBPCI_IO_0030>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0030>DERIVED" ] The NG_NICVBPCI shall be implemented in an FPGA technology with an integrated PLL capable of producing a 5X multiplied frequency from a specified input clock. [FRD_NGNICVBPCI_IO_0040>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0040>DERIVED" ] The NG_NICVBPCI shall be implemented in an FPGA technology with an integrated PLL capable of generating an internal clock with a frequency between 99 MHz and 120 MHz. [FRD_NGNICVBPCI_IO_0050>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0050>DERIVED" ] The NG_NICVBPCI device programmable cell utilization shall be no more than 75% at the time of the Critical Design Review (CDR). Commentary: A programmable cell is the smallest unit of logic reported by the FPGA vendor's tool set as being allocated to implement the intended function. [FRD_NGNICVBPCI_IO_0060>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0060>DERIVED" ] The NG_NICVBPCI device package used for this design shall be the FG484 FBGA package or equivalent. [FRD_NGNICVBPCI_IO_0070>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0070>DERIVED" ] The NG_NICVBPCI FPGA shall be rated to meet required speed, timing and power performance over the industrial temperature range (-40C to +85C). 3.2.2 Device I/O Signal Definitions The pin-out for the NG_NICVBPCI is listed in Table 1. [FRD_NGNICVBPCI_IO_0080>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0080>DERIVED" ] The NG_NICVBPCI shall assign package pin numbers to top-level pin names as defined in Table 1. [FRD_NGNICVBPCI_IO_0090>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0090>DERIVED" ] When the TRISTATE_N input is asserted the NG_NICVBPCI shall tri-state all outputs and bi-directional pins listed in Table 1 except for TDO. Commentary : Certain PCI and VB_PCI signals require PCI_CLK and CLK_25 to be present to react to TRISTATE_N assertion. If clocks are not present then assertion of PCI_RST_N and Assertion of CCA_RST_N signals will cause those signals to tri-state asynchronously. [FRD_NGNICVBPCI_IO_0100>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0100>DERIVED" ] Unless specifically called out, all inputs (and bi-directional circuits when acting as inputs) of the NG_NICVBPCI shall respond to LVTTL voltage levels. [FRD_NGNICVBPCI_IO_0110>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IO_0110>DERIVED" ] Unless specifically called out, all outputs (and bi-directional circuits when acting as outputs) of the NG_NICVBPCI shall drive to LVTTL voltage levels. The following legend applies to Table 1: The following abbreviations are used to identify the reset state of the pin · N/A not applicable · U undefined · Z tri-state or high impedance state · 0 Driven Low · 1 Driven High The following abbreviations are used for the I/O type of the pin. · IN Input · OUT output · STS Sustained Tristate · OD Open Drain · OS Open Source · I/O Input and Output · I/STS Input and Sustained Tristate Output · I/OD Input and Open Drain Table 1 – NextGen NIC VbPCI Master FPGA Pin-out Schematic Name Spec Name FPGA Ball # Type Pull up Reset State SSO prone Description Clock/ Reset Interface CLK20_FPGA1 CLK20 M5 In N/A N/A N/A 20Mhz clock (Reserved for growth) CLK25_FPGA1 CLK_25 L19 In N/A N/A N/A 25Mhz clock PCI_CLK1 PCI_CLK N4 In N/A N/A N/A 50 MHz clock CCA_RST# CCA_RST_N D5 In N/A N/A N/A CCA reset signal, resets internal FPGA logics PCI_RST# PCI_RST_N U5 In N/A N/A N/A PCI reset signal (PCI I/O standard) PCI (bus 0) Interface PCI_DEVSEL# PCI_DEVSEL_N R4 STS No Z No PCI DEVSEL# (PCI I/O standard) PCI_FRAME# PCI_FRAME_N V5 In N/A N/A N/A PCI FRAME# (PCI I/O standard) PCI_IRDY# PCI_IRDY_N T6 In N/A N/A N/A PCI IRDY# (PCI I/O standard) PCI_PAR PCI_PAR1 AB6 I/STS No Z No PCI PAR (PCI I/O standard) PCI_PERR# PCI_PERR_N P5 I/STS No Z No PCI PERR# (PCI I/O standard) PCI_SERR# PCI_SERR_N P4 OD No Open No PCI SERR# PCI_STOP# PCI_STOP_N1 T4 I/STS No Z No PCI STOP# (PCI I/O standard) PCI_IDSEL PCI_IDSEL M3 In No N/A No PCI DEVSEL (unused – reserved) PCI_TRDY# PCI_TRDY_N1 AA6 I/STS No Z No PCI TRDY# (PCI I/O standard) PCI_C_BE#0 PCI_C_BE0_N M8 In N/A N/A N/A PCI C/BE# bit 0 (PCI I/O standard) PCI_C_BE#1 PCI_C_BE1_N M7 In N/A N/A N/A PCI C/BE# bit 1 (PCI I/O standard) PCI_C_BE#2 PCI_C_BE2_N L6 In N/A N/A N/A PCI C/BE# bit 2 (PCI I/O standard) PCI_C_BE#3 PCI_C_BE3_N L4 In N/A N/A N/A PCI C/BE# bit 3 (PCI I/O standard) PCI_AD(31:0) Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PCI_AD(31:0) 1 H7 J7 H5 H4 J6 K6 J5 K5 J4 K4 J2 J1 L2 K1 N1 M2 N6 N7 P2 R2 T2 P6 P7 R6 R5 V7 W7 W6 W5 U4 K7 L8 I/O No Z Yes PCI Address/ Data Bus (PCI I/O standard) VbPCI Backplane Interface VB_C_BE#(3:0) Bit 0 1 2 3 VB_C_BE_N(3:0) 2 P17 N17 M17 P16 Out No Z No VbPCI Command / Byte Enable (active low) VB_FRAME# VB_FRAME_N2 L17 STS No Z No VbPCI Cycle Frame (active low) VB_IRDY# VB_IRDY_N2 L15 STS No Z No VbPCI Initiator Ready (active low) VB_DEVSEL# VB_DEVSEL_N2 M15 I/STS No Z No VbPCI Device Select (active low) VB_TRDY# VB_TRDY_N2 L16 I/STS No Z No VbPCI Target Ready (active low) VB_PAR VB_PAR2 K19 I/O No Z No VbPCI Parity – even parity across VB_AD(31:0) and VB_C_BE_N(3:0) VB_SERR# VB_SERR_N2 N16 I/OD No Z No VbPCI System Error (active low) VB_PERR# VB_PERR_N2 M16 I/STS No Z No VbPCI Parity Error (active low) VB_STOP# VB_STOP_N L22 In N/A N/A N/A VbPCI Stop (active low) – target initiated stop VB_RST# VB_RST_N K18 Out No 0 No VbPCI Reset (active low) VB_NIC_GNT# VB_NIC_GNT_N K16 Out No 1 No VbPCI NIC Grant (active low) VB_RST_LOCK VB_RST_LOCK K17 Out No 0 No VbPCI Reset Lockout VB1_SERR_INT# VB_SERR_INT_L R17 Out No 1 No VbPCI Bus #1 System Error Interrupt signal (active low) VB1_PERR_INT# VB_PERR_INT_L V15 Out No 1 No VbPCI Bus #1 Parity Error Interrupt signal (active low) VB1_STOP_INT# VB_STOP_INT_L V16 Out No 1 No VbPCI Bus #1 Stop Interrupt signal (active low) VB_AD(31:0) Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VB_AD(31:0) 2 K22 J22 J21 J19 J18 J17 H19 H18 G19 G18 F19 E19 B17 B16 A17 A16 AA16 W17 U19 T19 R19 R21 R22 P19 P18 M21 P22 N18 N19 N21 M19 F18 I/O Yes Z Yes VbPCI Address / Data Bus (32 bits) EEPROM EEPROM_WP EEPROM_WP AA17 Out No 1 No EEPROM Write Protect Input (reserved for growth) EE_SCL EE_SCL AB14 Out No 1 No I2C Serial Clock (reserved for growth) EE_SDA EE_SDA AB15 I/OD No Z No I2C Serial Data (reserved for growth) RTC/ Temperature Monitor Interface RTC_SDA RTC_SDA AA8 I/OD Yes 0 No I2C Serial Data RTC_SCL RTC_SCL AA9 OD No 0 No I2C Serial Clock NIC ASCB DPRAM Interface (Left Port) NIC_RW# NIC_RW_N F15 Out No 1 No DPRAM Read/Write Select NIC_OE# NIC_OE_N G17 I/O No 1 No DPRAM Output Enable (active low) NIC_ADS# NIC_ADS_N E15 I/O No 1 No DPRAM Address Strobe (active low) NIC_CNTEN# NIC_CNTEN_N J16 I/O No 1 No DPRAM Counter Enable (active low) NIC_CNTRST# NIC_CNTRST_N H16 Out No 1 No DPRAM Counter Reset (active low) NIC_CE1_B0 NIC_CE1_BO A14 Out No 0 No Chip Enable (active hi) for ASCB DPRAM NIC_CE0# NIC_CE0_N H17 Out No 1 No Chip Enable (active low) for ASCB DPRAM NIC_BE#(3:0) Bit 0 1 2 3 NIC_BE_N(3:0) D8 E8 A7 B7 I/O No 1 No DPRAM Byte Enable (active low) NIC_A(16:2) Bit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NIC_A(16:2) D15 D14 F14 G14 A13 B13 G13 G2 G1 A6 B6 B8 B9 A9 A8 I/O No 0 Yes DPRAM Address Bus (15-bit) NIC_D(31:0) Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NIC_D(31:0) F9 F8 E7 D7 E5 F5 D6 A4 E14 A12 D13 D12 E13 G12 H12 F12 E12 A11 A10 E11 D11 F11 F10 B10 G11 H11 D10 E10 D9 E9 G10 G9 I/O Yes Z Yes DPRAM Data Bus (32-bit) LAN DPRAM Interface (Right Port) LAN_DPR_RW# LAN_DPR_RW_N F2 Out No 1 No DPRAM Read/Write Select (reserved for growth) LAN_DPR_OE# LAN_DPR_OE_N C10 Out No 1 No DPRAM Output Enable (reserved for growth) LAN_DPR_ADS# LAN_DPR_ADS_N A18 Out No 1 No DPRAM Address Strobe (reserved for growth) LAN_DPR_CNTEN# LAN_DPR_CNTEN_N F13 Out No 1 No DPRAM Counter Enable (reserved for growth) LAN_DPR_CNTRST# LAN_DPR_CNTRST_N C11 Out No 1 No DPRAM Counter Reset (reserved for growth) LAN_DPR_CE# LAN_DPR_CE_N F4 Out No 1 No Chip Enable (reserved for growth) LAN DPRAM Interface (Left Port) NIC_CE1_B1 NIC_CE1_B1 A15 Out No 0 No Chip Enable (active hi) for LAN DPRAM (left port) NG NIC Core FPGA and CPU Interface IPD_STROBE# IPD_STROBE_N T9 In N/A N/A N/A IPD strobe from Core FPGA every 12.5 ms IPD_VALID IPD_VALID V4 Out No 0 No IPD Monitor Valid AUTO_DMA_DONE# AUTO_DMA_DONE_N T18 Out No 0 No Indicates Auto DMA is busy transferring data between the NIC DPRAM and clients on VbPCI Bus 1 or VbPCI Bus 2. Local POL Monitors FAIL_1_5V_HI FAIL_1_5V_HI B4 Out No 0 No 1.5V supply overshoot test FAIL_1_5V_LO FAIL_1_5V_LO C6 Out No 0 No 1.5V supply undershoot test FAIL_3_3V_HI FAIL_3_3V_HI B5 Out No 0 No 3.3V supply overshoot test FAIL_3_3V_LO FAIL_3_3V_LO C7 Out No 0 No 3.3v supply undershoot test APM Interface APM_CLK APM_CLK N5 Out No 1 No Aircraft Personality Module clock APM_CS APM_CS U3 Out No 0 No Aircraft Personality Module chip select APM_DI APM_DI AA4 In Yes N/A N/A Aircraft Personality Module serial data input APM_DO APM_DO U2 Out No 1 No Aircraft Personality Module serial data output APM_PWR_FAIL# APM_PWR_FAIL_N AB5 In Yes N/A N/A Status for Power Supply for APM APM_SHDN# APM_SHDN_N Y4 Out No 1 No Control Signal for PS for APM Host ID Interface HSTIDBUS(4:0) Bit 0 1 2 3 4 HOSTIDBUS(4:0) N22 L20 K21 L21 K20 In N/A N/A N/A Host identification discrete inputs (4-0) HOSTIDBUS5 HOSTIDBUS5 P21 In N/A N/A N/A Channel A/B# input HOSTIDBUS6 HOSTIDBUS6 Y10 In N/A N/A N/A Channel Parity input P/S Test Bus PSBUS(8:0) Bit 0 1 2 3 4 5 6 7 8 PSBUS(8:0) W10 W9 W8 AB9 AB8 AA7 AA10 R12 R11 Out Out Out Out Out In In In In No No No No No N/A N/A N/A N/A 0 0 0 0 0 N/A N/A N/A N/A No No No No No N/A N/A N/A N/A Power supply #1 output discrete bus, Bits 0 -4 Power supply #1 input discrete bus, Bits 5-8 Mezzanine Card Interface AUTO_DPREQ3# AUTO_DPREQ3_N G6 In N/A N/A N/A Active-low DPRAM request from Auto DMA state machine in FPGA#3 (PII-NIC VbPCI Master FPGA). AUTO_BUSY3# AUTO_BUSY3_N G5 In N/A N/A N/A When low, indicates Auto DMA in FPGA#3 is busy transferring data between the NIC DPRAM and clients on PCI Bus 2. AUTO_DPGNT3# AUTO_DPGNT3_N H6 Out No 1 No Active-low DPRAM grant to Auto DMA state machine in FPGA#3 (PII-NIC VbPCI Master FPGA). AUTO_EXCUSE_ME AUTO_EXCUSE_ME_N G4 Out No 1 No Used to pause Auto DMA in this FPGA and FPGA#3 temporarily if another function needs access to the DPRAM (active low). Fan Tachometer Interface FANTACH(4:1) Bit 0 1 2 3 4 FANTACH(4:1) U9 V8 U10 T10 In N/A N/A N/A Fan Tachometer signals FAN_ON (4:1) Bit 0 1 2 3 4 FAN_ON (4:1) V10 V9 U11 T11 Out No 0 No Fan Control on/ off signals JTAG Interface FPGA1_TCK FPGA1_TCK U16 In N/A N/A N/A Boundary Scan Test Clock B_TMS B_TMS W18 In N/A N/A N/A Boundary Scan Test Mode Select FPGA1_TDI FPGA_TDI V17 In N/A N/A N/A Boundary Scan Test Data In B_TRST# B_TRST_N U18 In N/A N/A N/A Boundary Scan Test Reset FPGA1_TDO FPGA1_TDO V19 Out N/A N/A N/A Boundary Scan Test Data Output Fault Isolation SLOT_SERR#(7:0) Bit 0 1 2 3 4 5 6 7 SLOT_SERR_N(7:0) V12 V11 U12 T12 W13 W12 W11 AA13 In N/A N/A N/A To monitor SERR# signals from multiple clients on the VbPCI bus 1. SLOT_RST#(7:0) Bit 0 1 2 3 4 5 6 7 SLOT_RST_N(7:0) U14 U13 AB13 AB12 T14 T13 AB17 AB16 Out N/A 1 No To drive RST# signals to multiple clients on the VbPCI bus 1 Miscellaneous CLK25_TEST_CLK CLK25_TEST_CLK D16 In N/A N/A N/A For JTAG structured test coverage to emulate a clock input to the DPRAM's (Reserved for growth) CLK25_OSC_DISABLE# CLK25_OSC_DISABLE_N G21 In N/A N/A N/A For JTAG structured test coverage to emulate a clock input to the DPRAM's (Reserved for growth) CLK25_GEN_TESTMODE CLK25_GEN_TESTMODE B18 In N/A N/A N/A For JTAG structured test coverage to emulate a clock input to the DPRAM's (Reserved for growth) PCICLK_GEN_TESTMODE PCICLK_GEN_TESTMODE G20 In N/A N/A N/A For JTAG structured test coverage to emulate a clock input to the DPRAM's (Reserved for growth) TRISTATE2# TRISTATE_N M4 In N/A N/A N/A Tri-state#: The assertion of this signal tri-states all outputs. VBPCI_CPU_DREQ VBPCI_CPU_DREQ L3 Out No 0 No (Reserved for growth) SCRUB_MCHK_INT# SCRUB_MCHK_INT_N R18 Out No 1 No (Reserved for growth) CORE_DONE# CORE_DONE_N A5 In N/A N/A N/A Done signal from CORE FPGA IM_HERE# IM_HERE_N B12 In N/A N/A N/A Indicates that PM NIC card is installed. Spares INTER_FPGA_SPARE1 INTER_FPGA_SPARE1 W16 In N/A N/A N/A Spare signal from Core FPGA. INTER_FPGA_SPARE2 INTER_FPGA_SPARE2 F3 Out Yes Z No Spare signal to Core FPGA. FPGA1_SPARE43 FPGA1_SPARE43 V14 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE42 FPGA1_SPARE42 V13 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE32 FPGA1_SPARE32 W15 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE31 FPGA1_SPARE31 W14 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE21 FPGA1_SPARE21 B11 Out No 0 No Spare signal from VBPCI FPGA. BKP_EN_MON BKP_EN_MON AB4 Out No Z No Unused left for future development (ascb TX time stamp function). PRI_EN_MON PRI_EN_MON AA5 Out No Z No Unused left for future development (ascb TX time stamp function). FPGA1_SPARE17 FPGA1_SPARE17 Y7 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE16 FPGA1_SPARE16 Y6 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE11 FPGA1_SPARE11 E16 Out No 0 No Spare signal from VbPCI FPGA FPGA1_SPARE5 FPGA1_SPARE5 K2 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE4 FPGA1_SPARE4 U8 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE3 FPGA1_SPARE3 T22 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE2 FPGA1_SPARE2 AB7 Out No 0 No Spare signal from VBPCI FPGA. FPGA1_SPARE1 FPGA1_SPARE1 N2 Out No 0 No Spare signal from VBPCI FPGA. Notes: 1. The output enable signal for these signals is registered therefore the signals will tri-state within two PCI_CLK cycles after TRISTATE_N is asserted. These signals are tri-stated when CCA_RST_N or PCI_RST_N is asserted. 2. The output enable signal for these signals is registered therefore the signals will tri-state within two CLK_25 cycles after TRISTATE_N is asserted. These signals are tri-stated when CCA_RST_N is asserted. 3.3 Functional Requirements 3.3.1 Clock CLK25, CLK20 and PCI_CLK are generated from separate oscillators and are therefore asynchronous. The frequencies of the CLK25 and CLK20 clocks are set to avoid the COM frequencies. [FRD_NGNICVBPCI_CLK_0120>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_CLK_0120>DERIVED" ] The NG_NICVBPCI FPGA shall operate from the three clock inputs defined in Table 2. Table 2 – NG_NICVBPCI Clock Inputs Clock Name Frequency Function CLK25 24.9975MHz ± 50 ppm VbPCI Master interface, DPRAM interface, IPD CLK20 19.998MHz ± 50 ppm Reserved PCI_CLK 50.000MHz ± 50 ppm PCI Client interface 3.3.2 Reset CCA_RST_N is a CCA level reset signal that is generated by the NG_NICCORE's FPGA and input into NG_NICVBPCI FPGA. This signal is the primary reset control for the all internal NG_NICVBPCI FPGA logic. The NG_NICVBPCI FPGA Reset signal (CCA_RST_N) is asserted to force the logic in the NG_NICVBPCI FPGA to a deterministic state. In addition, the NG_NICVBPCI FPGA has the local input reset signal, PCI_RST_N from the CPU, which resets the PCI target interface and associated functions on the 50 MHz clock domain. [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0330" ] [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0360 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0360" ] [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0370 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0370" ] [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0380 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0380" ] [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0400 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0400" ] [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0430 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0430" ] [FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0448 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0448" ] The bi-directional and output pins of the NG_NICVBPCI FPGA shall be initialized to their reset state, as defined in Table 1 when CCA_RST_N is asserted. [FRD_NGNICVBPCI_RST _0140>HRD_NGNIC_Func_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0140>HRD_NIC_Func_0330" ] The assertion of CCA_RST_N shall initialize the memory-mapped registers in NG_NICVBPCI FPGA. Commentary: The reset value requirement for each register is defined in a subsequent section(s) of this document. [FRD_NGNICVBPCI_RST _0150>HRD_NGNIC_Func_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0150>HRD_NGNIC_Func_0330" ] The NG_NICVBPCI FPGA shall asynchronously assert and synchronously de-assert all internal reset signals, relative to their corresponding clock domains. [FRD_NGNICVBPCI_RST _0160>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0160>DERIVED" ] When PCI_RST_N is asserted the NG_NICVBPCI FPGA shall complete all the following: · Forces all PCI configuration registers, state machine and output drivers to a reset state as defined throughout this document. · All PCI bus 0 outputs and bidirectional signals must be tri-stated. 3.3.2.1 Backplane VbPCI Bus 1 Reset Control The Dual NIC configuration contains bus masters for two independent PCI busses (PCI BUS 1 and PCI BUS 2). Since the NIC is the master for both busses, the logic used to generate the reset signal to all clients originates with the NIC. There are Four (4) discrete outputs used to operate the backplane reset logic in the MAU cabinet. Two (2) discrete outputs for PCI bus 1 located on NIC module and two discrete outputs for PCI Bus 2 located on PM module. One discrete output of the PCI1 pair, called “Backplane PCI bus 1 RST#”, is used to directly control the VB_RST_N line on its respective PCI BUS 1. A ‘0’ written to this discrete output will drive the VB_RST_N line to the asserted state (low). A ‘1’ written to this discrete output will drive the RST# line to the de-asserted state (high). The second discrete output is called “Backplane reset lockout 1”. Writing a ‘1’ to this discrete output will prevent the VB_RST_N line from resetting the client module. Writing a ‘0’ to this discrete output will allow the VB_RST_N backplane signal to reset each client. The purposes of the “Backplane reset lockout 1” signal are: 3. First, it allows BIT S/W to exercise the backplane reset signal without actually resetting clients, 4. Second, the design of the BIC on each client is such that the reset lockout signal, when asserted, prevents the client from resetting the BIC. Independent reset control of the two PCI busses is necessary due to the fact that in some MAU cabinets, with separate power supplies for the clients on the two backplane busses, it is possible that clients on PCI bus 2 must be reset independently of clients on PCI bus 1. Upon power up reset or system reset to the NIC, clients on both backplanes will be held in reset. i.e. VB_RST_N will be in the asserted state and VB_RST_LOCK will be in the de-asserted state. Reset for the VbPCI client can originate either by the VB_RST_N (DOUT20 PCI bus 1 reset#), or by the NIC module itself (CCA_RST_N). VB_RST_LOCK (DOUT19) is an active high signal that prohibits these sources from resetting the VbPCI client. [FRD_NGNICVBPCI_RST _0170>HRD_NGNICM_Mod_0060 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0170>HRD_NGNICM_Mod_0060" ] [FRD_NGNICVBPCI_RST _0170>HRD_NGNIC_Func_0240 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0170>HRD_NGNIC_Func_0240" ] [FRD_NGNICVBPCI_RST _0170>HRD_NGNIC_Func_0360 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0170>HRD_NGNIC_Func_0360" ] When VB_RST_LOCK (DOUT19 PCI bus 1 reset lockout) is de-asserted, either of the following conditions shall assert VB_RST_N to reset the VbPCI Bus 1 clients: · when DOUT20 (PCI bus 1 reset#) is asserted · when NIC’s CCA_RST_N is asserted. [FRD_NGNICVBPCI_RST _0180>HRD_NGNIC_Func_0190 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0180>HRD_NGNIC_Func_0190" ] [FRD_NGNICVBPCI_RST _0180>HRD_NGNIC_Func_0370 XE \f "TRACETAG" "FRD_NGNICVBPCI_RST _0180>HRD_NGNIC_Func_0370" ] VB_RST_LOCK (DOUT19 VbPCI bus 1 reset lockout) output shall be de-asserted when CCA_RST_N (VbPCI bus 1 PS power valid) is de-asserted. Commentary: This is to prevent asserted high signals from driving voltage onto a backplane that may not be powered. 3.3.3 Monitors 3.3.3.1 Isolated Window Pulse Detector (IPD) The NIC Heartbeat Monitor (HBM) includes two functional parts: the Window Pulse Detector (WPD) which is incorporated into the NG_NICCORE FPGA and the Isolated Window Pulse Detector (IPD) which is incorporated in the NG_NICVBPCI FPGA. The IPD requires pulses spaced at a certain interval to keep the output IPD_VALID high. If the IPD times out and sets the IPD_VALID output low, the Driver Power to the ASCB bus drivers is disabled. The Isolated Window Pulse Detector (IPD) uses a 25MHz clock that is independent from the WPD clock to establish the window between the pulses. If the WPD stops sending pulses to the IPD or sends pulses too fast to the IPD because of a failed processor or a power supply fault, the IPD will go into the invalid state within 55.5 ms. If the WPD goes invalid then the IPD monitor is not satisfied and the IPD_VALID signal is de-asserted. The IPD will remain in the invalid state until the WPD becomes satisfied and starts sending pulses at the proper rate once again. After the CPU is reset (or upon a power-up condition), the IPD functions will remain in the invalid state until the IPD detects IPD_STROBE_N (active low) pulses within time limits specified above. [FRD_NGNICVBPCI_IPD_0190>HRD_NGNIC_CoreFunc_0720 XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0190>HRD_NGNIC_CoreFunc_0720" ] [FRD_NGNICVBPCI_IPD_0190> HRD_NGNIC_CoreSafe_0040 XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0190>HRD_NGNIC_CoreFunc_0720" ] The Isolated Window Pulse Detector (IPD) shall use the independent clock, 25 MHz, to establish the window for the IPD_STROBE_N pulses. Commentary: WPD operates from 20 MHz clock, so IPD has to operate from independent (from WPD) 25 MHz clock. [FRD_NGNICVBPCI_IPD_0210>HRD_NGNIC_CoreFunc_0753 XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0210>HRD_NGNIC_CoreFunc_0753" ] [FRD_NGNICVBPCI_IPD_0210>HRD_NGNIC_CoreFunc_0754 XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0210>HRD_NGNIC_CoreFunc_0754" ] If a time interval of 12.3 to 25.2 ms is detected between two falling edges of the IPD_STROBE_N signal, the IPD circuit shall assert the IPD_VALID output pin active high. Commentary: The state of the IPD_VALID output pin can be read by the CPU on DIN28. [FRD_NGNICVBPCI_IPD_0220>HRD_NGNIC_CoreFunc_0752 XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0220>HRD_NGNIC_CoreFunc_0752" ] When no falling edges have been detected on IPD_STROBE_N (DIN27) or the time between falling edges is less than 12.3 ms or more than 25.2 ms, the IPD logic shall complete the following sequence: 1. Wait for 55.5 ± 0.5 ms (IPD logic “time out” period) 2. Set IPD_VALID (DIN28) to the invalid state (LOW) [FRD_NGNICVBPCI_IPD_0221>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0221>DERIVED" ] The NG_NICVBPCI FPGA shall ignore IPD_STROBE_N (DIN27) during the IPD logic “time out” period. [FRD_NGNICVBPCI_IPD_0230>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0230>DERIVED" ] When CCA_RST_N is asserted the NG_NICVBPCI FPGA shall de-assert IPD_VALID. [FRD_NGNICVBPCI_IPD_0240>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_IPD_0240>DERIVED" ] After CCA_RST_N is de-asserted, if exactly two falling edges of IPD_STROBE_N are detected with a time interval between 12.3 ms – 25.2ms, the IPD shall assert IPD_VALID to valid state. Commentary: This requirement assumes that a 12.5 ms timer will be started with the first IPD_STROBE_N pulse (after reset or power up). The requirement assumes no synchronization between the pulses and the timing circuits. The circuit monitors a free running (asynchronous) window of 25.2ms for exactly one IPD_STROBE_N events. When this case occurs, the output of the monitor changes from invalid to valid. It is not necessary to wait for the IPD logic “time out” period when CCA_RST_N transitions to the de-asserted state. The “time out” period only applies when IPD_VALID is asserted. 3.3.3.2 Power Monitors Internal discrete outputs are provided to test each of the power supply monitors. Each monitor has a Fail High and Fail Low discrete associated with it. All monitors are tested with the same procedure. If the discrete output “Fail High” set to a ‘1’, the monitor discrete input should show “invalid” and the Local_PV discrete input should indicate invalid. If the discrete output “Fail High” set to a ‘0’, the monitor discrete input should show “valid” and the Local_PV discrete should indicate valid. If the discrete output “Fail Low” set to a ‘1’, the Monitor input should show “invalid” and the Local_PV should indicate invalid. If the discrete output “Fail Low” set to a ‘0’, the monitor discrete input should show “valid” and the Local_PV discrete should indicate valid. Table 3 – Local Power Supply Monitor Test Discrete Outputs Register Signal Name Reset value Description DOUT 32 FAIL_1_5V_HI 0 Discrete Output Bit 32, Local PS 1.5V Overvoltage Test Dout32, active high DOUT 33 FAIL_1_5V_LOW 0 Discrete Output Bit 33, Local PS 1.5V Undervoltage Test Dout33, active high DOUT 34 FAIL_3_3V_HI 0 Discrete Output Bit 34, Local PS 3.3V Overvoltage Test Dout34, active high DOUT 35 FAIL_3_3V_LOW 0 Discrete Output Bit 35, Local PS 3.3V Undervoltage Test Dout35, active high [FRD_NGNICVBPCI_SAFE_0250>HRD_NGNIC_CoreSafe_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_SAFE_0250>HRD_NGNIC_CoreSafe_0120" ] The NG_NICVBPCI FPGA shall provide DOUTS shown in Table 3 for testing the Local Power Supplies. Commentary: A power supply test discrete output must be set to the active state for at least 5 ms before the power supply monitor circuit will indicate an invalid condition. [FRD_NGNICVBPCI_MON_0260>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_MON_0260>DERIVED" ] The NG_NICVBPCI FPGA shall support PCI Bus 0 writes of the DOUT register and specifically the outputs defined by Table 3. [FRD_NGNICVBPCI_MON_0280>HRD_NGNIC_CoreFunc_1100 XE \f "TRACETAG" "FRD_NGNICVBPCI_MON_0280>HRD_NGNIC_CoreFunc_1100" ] The reset values for the POL monitors Discrete Outputs shall be defined By Table 3. 3.3.4 PCI Busses 3.3.4.1 Configuration of PCI Busses The NIC CCA is required to support the “plug and play” requirements of the PCI specification and is required to interrogate and allocate memory space for two backplane VbPCI busses at power-up. The NIC CCA has three PCI busses: PCI Bus 0, VbPCI Bus 1, and VbPCI Bus 2 (only present on dual NIC modules). PCI Bus 0 is local bus to the NextGen NIC CCA. This bus is accessed through the MPC8280 processor, NIC Core FPGA, and NIC VbPCI FPGA. VbPCI Bus 1 is defined as the backplane bus connected on a single NextGen NIC module and the non-mezzanined bus connection on a Dual NextGen NIC module. The NG_NICVBPCI FPGA controls VbPCI Bus 1. VbPCI Bus 2 is defined as the mezzanined backplane bus connected on a Dual NextGen NIC module, and the PM-NIC VbPCI Master FPGA controls this bus. To configure the PCI busses, the NIC supports the preferred PCI “configuration mechanism #1” which defines two 32-bit locations in “I/O space” at address 0CF8H (register “CONFIG_ADDR”) and address 0CFCH (register “CONFIG_DATA”) for configuring PCI devices. The bus number entered into bits 23-16 of the configuration address register identify which bus (0 – 2) the configuration access is intended for. The device number entered into bits 15 - 11 of the configuration address register identifies which slot the configuration access is aimed at. During a configuration access, hardware will assert one AD signal within the range AD (31:11). Each of the AD lines in this range is connected to a different IDSEL line, one for each slot. Device number 0 asserts AD31, device number 1 will assert AD30, and device number 3 will assert AD29 and so on. For VbPCI Busses 1 and 2, the general rule for the IDSEL distribution has been most significant address bit (AD31) is tied to the slot adjacent to the respective NIC connector (either VbPCI Bus 1 or VbPCI Bus 2 connector). The next slot over would have the next address bit (AD30) tied to IDSEL and so on. Routing on the backplane to connect the IDSEL to its respective address bit should be as short as possible. From the NIC CPU’s perspective, the physical memory address range for the PCI Bus 0 interface is from 6100:0000h through 62FF:FFFFh (32 Mbytes). The physical memory address range for the VbPCI Bus 1 interface is from 2000:0000h through 2FFF:FFFFh (256 Mbytes). The physical memory address range for the VbPCI Bus 2 interface is from 3000:0000h through 3FFF:FFFFh (256 Mbytes). The physical memory address range for broadcast data to all VbPCI devices is from 4000:0000h through 4FFF:FFFFh (256 Mbytes), of which 128K bytes are presently used. 3.3.5 PCI Client Bus Interface The NG_NICVBPCI FPGA provides a PCI bus client interface (PCI Bus 0) to allow S/W accesses to the following resources within the FPGA: · External EEPROM memory · External NIC Dual-Port RAM memory (left port) · External Real-Time Clock · External Temperature Monitor · External VbPCI Bus 1 · Internal Discrete Inputs/Outputs registers · External APM interface · External Fan Interface The NG_NICVBPCI interprets the PCI protocol into actions that will be performed in the system. The assertion of the PCI_FRAME_N input signal marks the initiation of a PCI transaction. The NG_NICVBPCI logic will decode the address and other control inputs to execute the commanded host operation (i.e. read DMA register, write DOUTs, etc.). To end the transaction, the FPGA will produce a PCI_TRDY_N output signal back to the host, allowing it to begin another transaction. All accesses are mutually exclusive by nature since only one address can be decoded at a time. Commentary: Any reference to “clocks” in this section will be referring to the PCI_CLK input (50 MHz). Any reference to the term “access time” (for a host access) will be referring to the number of full PCI_CLK cycles from the start of a data phase to the assertion of PCI_TRDY_N. The NG_NICVBPCI PCI Bus 0 interface is based on the PCI Local Bus Specification Revision 2.2. The NG_NICVBPCI Interface is not fully compliant with this specification. The PCI Bus is well documented in its corresponding specification. Refer to the reference list at the beginning of this document. [FRD_NGNICVBPCI_PCI_0290>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0290>DERIVED" ] The NG_NICVBPCI shall implement 32 bit PCI Target Interface Bus protocol bus transactions as defined in PCI local bus specification Revision 2.2, Sections 3.3.1-3.3.2 and 3.3.3.1-3.3.3.2 (and its subsections) [FRD_NGNICVBPCI_PCI_0300>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0300>DERIVED" ] The NG_NICVBPCI shall implement the required PCI signals as defined in PCI local Bus specification Sections 2.2.1 - 2.2.3 and 2.2.5 3.3.5.1 PCI Bus Operations and Address spaces [FRD_NGNICVBPCI_PCI_0310>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0310>DERIVED" ] The NG_NICVBPCI shall support the PCI bus operations indicated in Table 4 as operations to implement if the NG_NICVBPCI is the addressed target (Claim if Target) Table 4 – Supported PCI bus operations PCI Bus Command PCI address phase C/BE(3:0) NG NIC VbPCI Bus response* NG NIC VbPCI action* Interrupt Acknowledge 0h Ignored Ignored Special Cycle 1h Ignored Ignored I/O Read 2h Claim if Target I/O read I/O Write 3h Claim if Target I/O write Reserved 4h Ignored Ignored Reserved 5h Ignored Ignored Memory Read 6h Claim if Target Memory Read Memory Write 7h Claim if Target Memory Write Reserved 8h Ignored Ignored Reserved 9h Ignored Ignored Config. Read Ah Ignored Ignored Config. Write Bh Ignored Ignored Memory Read Multiple Ch Claim if Target Memory Read Dual Address Cycle Dh Ignored Ignored Memory Read Line Eh Claim if Target Memory Read Memory Write & Invalidate Fh Claim if Target Memory Write *Ignored means the NG_NICVBPCI FPGA will not acknowledge the operation. [FRD_NGNICVBPCI_PCI_0330>HRD_NGNIC_CoreIO_0310 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0330>HRD_NGNIC_CoreIO_0310" ] The NG_NICVBPCI PCI bus Memory map shall be as defined in Table 5. Commentary: A multi-FPGA transaction is one in which the transaction is processed by both FPGAs, but only the NG_NICVBPCI FPGA claims and terminates the transaction on PCI Bus 0. The NG_NICCORE FPGA completes the transaction like any other PCI access, but never drives signals on PCI Bus 0. The NG_NICCORE FPGA asserts the CORE_DONE_N signal to indicate that it is done processing the transaction. The NG_NICVBPCI FPGA will process the transaction and wait until CORE_DONE_N is asserted before terminating the cycle on PCI Bus 0. Table 5 – NG_NICVBPCI FPGA PCI Memory Space Address Map Block Size Starting Address Ending Address Notes APM 16 MB 7E00:0000H 7EFF:FFFFH Auto DMA 16 MB 7B00:0000H 7BFF:FFFFH Multi-FPGA transaction RTC/ Temp. Sensors 16 MB 7900:0000H 79FF:FFFFH VbPCI Bus 1 Last Command Register 4K 7810:B000H 7810:BFFFH VbPCI Bus 1 Last Address Register 4K 7810:A000H 7810:AFFFH DINs 1 MB 7310:0000H 731F:FFFFH DOUTs 1 MB 7210:0000H 721F:FFFFH FPGA ID 1 MB 7190:0000H 7190:FFFFH NIC DPRAM Left 128K 6000:0000H 6001:FFFFH ASCB DPRAM left port Internal DPRAM (L) 4K 6002:0000H 6002:0FFFH Internal DPRAM (R) 4K 6202:0000H 6202:0FFFH VbPCI Broadcast 256 MB 4000:0000H 4FFF:FFFFH Write only. Multi-FPGA transaction System Error Test 16MB 2F00:0000H 2FFF:FFFFH VbPCI Bus 1 251 MB 2000:0000H 2F00:0000H Parity Error Test 4K 0000:0054H [FRD_NGNICVBPCI_PCI_0340>HRD_NGNIC_CoreIO_0320 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0340>HRD_NGNIC_CoreIO_0320" ] The NG_NICVBPCI PCI bus I/O map shall be as defined in Table 6. Table 6 – NG_NICVBPCI FPGA PCI I/O Space Address Map Block Size Starting Address Ending Address Notes PCI (Local, Bus 1, Bus 2) 4 bytes 0CF8H 0CFBH PCI Configuration Address Register. Multi-FPGA transaction. PCI (Local, Bus 1, Bus 2) 4 bytes 0CFCH 0CFFH PCI Configuration Data Register [FRD_NGNICVBPCI_PCI_0350>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0350>DERIVED" ] PCI accesses to the address ranges shown in Table 5 shall be terminated by the NG_NICVBPCI FPGA by setting PCI_TRDY_N to the asserted state. [FRD_NGNICVBPCI_PCI_0355>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0355>DERIVED" ] PCI accesses to addresses shown in Table 5 that are identified as Multi-FPGA transaction shall not be terminated by the NG_NIC_VbPCI until CORE_DONE_N is asserted or the PCI target latency time out period has been exceeded while IM_HERE_N input remains asserted. Commentary: See 3.3.5.4 for the definition of the PCI target latency timeout period. IM_HERE_N identifies dual card configuration of NIC. [FRD_NGNICVBPCI_PCI_0360>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0360>DERIVED" ] PCI accesses to the Configuration Address Register shown in Table 6 shall be terminated by the NG_NICVBPCI FPGA by setting PCI_TRDY_N to the asserted state. [FRD_NGNICVBPCI_PCI_0365>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0365>DERIVED" ] PCI write accesses to the Configuration Address Register shown in Table 6 shall not be terminated by the NG_NIC_VbPCI until CORE_DONE_N is asserted or the PCI target latency time out period has been exceeded while IM_HERE_N input remains asserted. Commentary: See 3.3.5.4 for the definition of the PCI target latency timeout period IM_HERE_N identifies dual card configuration of NIC.. [FRD_NGNICVBPCI_PCI_0370>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0370>DERIVED" ] PCI accesses to the Configuration Data register shall be terminated by the NG_NICVBPCI FPGA if the contents of the Config. Address Register indicate that VbPCI Bus 1 is the target bus for the configuration transaction as shown Table 7. Table 7 – PCI Configuration Space Accesses Description Contents of Config. Address Register Terminated by NG_NICVBPCI FPGA VbPCI Bus 2 1_XXXXXXX_XXXXXX10_XXXXX_XXX_YYYYYY_YYb No VbPCI Bus 1 1_XXXXXXX_XXXXXX01_XXXXX_XXX_YYYYYY_YYb Yes All others ---- No Note: X and Y denote don’t cares [FRD_NGNICVBPCI_PCI_0380>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0380>DERIVED" ] NG_NICVBPCI shall claim all PCI Bus memory address space transactions within its address spaces listed in Table 5 when no PCI address/command parity errors are present by asserting the PCI_DEVSEL_N signal. 3.3.5.2 PCI Bus Data Path Access To support the big endian to little endian mapping issue, the PCI client interface will swap all four data bytes (during the data phase, but not address phase). [FRD_NGNICVBPCI_MON_0385> DERIVED XE \f "TRACETAG" " FRD_NGNICVBPCI_MON_0385>Derived" ] PCI accesses to the NG_NICCORE FPGA shall swap bytes during the data phase of any transaction. PCI bus Byte Lane 0 (LSByte) will be swapped with Internal bus Byte Lane 3, PCI bus byte lane 1 will be swapped with Internal bus byte lane 2, PCI bus byte lane 2 will be swapped with internal bus byte lane 1 and PCI bus byte lane 3 (MSByte) will be swapped with internal bus byte lane 0. [FRD_NGNICVBPCI_MON_0386> DERIVED XE \f "TRACETAG" " FRD_NGNICVBPCI_MON_0386>Derived" ] PCI accesses to the NG_NICCORE FPGA shall swap byte enables during the data phase of any transaction. PCI bus C_BE0_n (LSByte) will be swapped with Internal bus Byte Enable 3, PCI bus C_BE1_n will be swapped with Internal bus Byte Enable 2, PCI bus C_BE2_n will be swapped with internal bus Byte Enable 1 and PCI bus C_BE3_n (MSByte) will be swapped with internal bus Byte Enable 0. 3.3.5.3 PCI Data Bursting [FRD_NGNICVBPCI_PCI_0390>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0390>DERIVED" ] NG_NICVBPCI shall support the PCI Bus burst ordering as indicated in Table 8. Table 8 – PCI Burst Ordering Address Phase Burst Order NIC VbPCI Target Action PCI_AD1 PCI_AD0 0 0 Linear Incrementing Linear Incrementing 0 1 Reserved Target Abort 1 0 Cache-line Wrap Mode Target Abort 1 1 Reserved Target Abort Commentary: The NG_NICVBPCI monitors the boundaries of the 16MB partitions during burst transactions to burst accessible memory spaces. If the address crosses the 16MB memory partition boundary (e.g. DINS into DOUTS), the target will perform a target abort for the last allocated location within the memory region. The target abort will only occur if the transaction is to continue beyond the last allocated memory location. A single access to the last location or a burst up to the last location won't generate a target abort. [FRD_NGNICVBPCI_PCI_0400>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0400>DERIVED" ] For the burst accessible devices listed in Table 9 the NG_NICVBPCI shall issue target abort for any PCI Bus burst access outside the memory mapped address boundaries listed in Table 5. [FRD_NGNICVBPCI_PCI_0410>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0410>DERIVED" ] The NG_NICVBPCI shall not claim the transaction if an address/command cycle has parity errors. [FRD_NGNICVBPCI_PCI_0420>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0420>DERIVED" ] If the NG_NICVBPCI detects a parity error during the address/command cycle, it shall assert PCI_SERR_N. 3.3.5.4 PCI Bus Access latency The PCI protocol supports a variety of bus transfers. Bus transactions can be burst or non-burst. Transfer widths can be 8, 16, or 32-bits. Not all combinations of transactions and transfer widths are supported for each resource the host can access. The NG_NICVBPCI provides access to three basic resource types: internal register based, external shared and external handshake based resources. Access latency to internal register based resources is tightly bounded. Access latency to external shared resources is loosely bounded and access latency to external handshake based resources is unbounded. [FRD_NGNICVBPCI_PCI_0425>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0425>DERIVED" ] The NG_NICVBPCI FPGA PCI target latency timeout period shall be 1937 ± 1 PCI_CLK cycles for any data phase of a PCI Bus 0 transaction. Commentary: If any data phase of a PCI Bus 0 transaction that has been claimed by the NG_NICVBPCI FPGA take more than 1937 cycles to complete, the transaction will be terminated by a target abort. This is a deviation from the PCI Revision 2.2 specification which states that a target must issue a retry if it cannot complete the first data phase in 16 clock cycles. This deviation is required to allow accesses to the APM to complete. Refer to 3.3.7 for a description of the APM interface. [FRD_NGNICVBPCI_PCI_0430>HRD_NGNIC_CoreIO_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0430>HRD_NGNIC_CoreIO_0330" ] [FRD_NGNICVBPCI_PCI_0430>HRD_NGNIC_CoreIO_0340 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0430>HRD_NGNIC_CoreIO_0340" ] PCI accesses to the NG_NICVBPCI subfunctions shown in Table 5 shall require no more than the specified amount of time to complete as shown in Table 9. Table 9 – Required PCI Bus maximum access times Block Name Read Clocks* Write Clocks* Access types supported External NIC DPRAM left port 28-16 22-16 32 bit, 16 bit, 8 bit External Real Time clock/ External Temperature Monitor 16 19 32 bit APM 1937 1937 32 bit, 16 bit, 8 bit Internal DMA register 16 26 32 bit Internal FPGA ID register 16 N/A 32 bit DINs 16 N/A 32 bit DOUTs 16 19 32 bit Internal DPRAM left port 28-16 22-16 32 bit, 16 bit, 8 bit Internal DPRAM right port 9-1 7-1 32 bit, 16 bit, 8 bit * For burst accesses, the first number indicates how many PCI clock cycles are required to complete the first access; the second number shows how many cycles are required to complete subsequent accesses. [FRD_NGNICVBPCI_PCI_0440>HRD_NGNIC_CoreIO_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0440>HRD_NGNIC_CoreIO_0330" ] The NG_NICVBPCI shall support PCI Byte Enables and Access Types as indicated in Table 9. [FRD_NGNICVBPCI_PCI_0450>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0450>DERIVED" ] The NG_NICVBPCI shall provide PCI access to internal registers and shared external resources using non-burst memory read/write bus accesses as indicated in Table 9. [FRD_NGNICVBPCI_PCI_0460>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0460>DERIVED" ] The NG_NICVBPCI shall support minimum PCI bus access times defined by Table 9 for PCI burst and non-burst accesses to external handshake based resources. 3.3.6 VbPCI Bus 1 Master Functions The NG_NICVBPCI FPGA Master Function allows the NIC CPU to perform the following functions: · PCI Memory Reads and Writes on the VbPCI backplane (PCI bus 1) and to the User DPRAM which interfaces through the VbPCI client. · PCI Configuration Reads and Writes on the VbPCI backplane (PCI bus1) and to the configuration registers in the VbPCI client via the configuration address and configuration data registers. · Reads to the VbPCI bus 1 last address and PCI bus 1 last command registers which contain the last address and command (respectively) that were issued on the VbPCI backplane (PCI bus 1). · Write to the VbPCI bus 1 test address and data registers. The NG_NICVBPCI PCI Master interface is based on the PCI Local Bus Specification Revision 2.1. The NG_NICVBPCI Master Interface is not fully compliant with this specification. See Primus Epic( Virtual Backplane Network( requirements, EB7031405. The following deviations to PCI Local Bus Specification 2.1 exist for the VbPCI interface: · The NIC may broadcast information to all user modules in the MAU during a single memory write transaction called a broadcast write. · Relaxed timing specifications exist on certain PCI signals. · Bit 1 of the PCI Header Command Configuration Register is internally hardwired to ‘1’ allowing users to accept memory accesses from power up. · The VB_NIC_GNT_N signal is used to qualify PCI configuration and memory accesses. · Burst configuration accesses to Configuration Register are not allowed. · During broadcast write transactions the VbPCI master generates the VB_DEVSEL_N and VB_TRDY_N signals. Commentary: For systems with VbPCI bridge Revision IDs up to (and including) version 6, plug-n-play software cannot use/assign a Base Address Register the value of 00xxxxxxh (in any present PCI device). If a Base Address Register value of 00xxxxxxh is assigned to any present PCI device (with a system that includes VbPCI Bridge devices with Revision IDs up to (and including) version 6), memory conflicts will occur with VbPCI bridges which are strapped not for Frame Buffer Arrangement Two (the two independent Frame Buffer Arrangement). NOTE: Any reference to clocks in this section will be referring to the CLK_25 input (24.9975 MHz). Any reference to the term “access time” (for a host access) will be referring to the number of full CLK_25 cycles from the start of a data phase to the assertion of PCI_TRDY_N. [FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0010 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0020" ] [FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0020 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0020" ] [FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0030 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0030" ] [FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0040 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0040" ] [FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0085 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0040" ] The NG_NICVBPCI FPGA shall implement 32 bit PCI Master Interface Bus protocol bus transactions as defined in PCI local bus specification Revision 2.1, Sections 3.3.1-3.3.2 and 3.3.3.1-3.3.3.2 (and its subsections) [FRD_NGNICVBPCI_PCI_0490>HRD_NGNIC_BP_0100 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0490>HRD_NGNIC_BP_0100" ] The NG_NICVBPCI FPGA shall implement the required PCI signals as defined in PCI local Bus specification Revision 2.1, Sections 2.2.1 - 2.2.5. Table 10 shows the memory map for VbPCI backplane (PCI bus 1 and VbPCI broadcast). Table 10 – VbPCI Bus 1 Memory Map Region Starting Address Ending Address Access Data bits VbPCI Bus 1 2000:0000H 2FFF:FFFFH Read/Write D(31:0) VbPCI Broadcast 4000:0000H 4FFF:FFFFH Write D(31:0) Table 11 shows how the PCI bus commands are decoded on the VbPCI backplane. Refer to the PCI Specification version 2.1 for more information on PCI bus transactions. Table 11 – PCI Bus Command Definitions VB_C_BE_N(3:0) PCI bus command 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write [FRD_NGNICVBPCI_PCI_0500>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0500>DERIVED" ] The NG_NICVBPCI FPGA shall support byte, word, double word aligned CPU accesses to all of the address regions defined in Table 10. Commentary: This does not imply that burst transfers (>1 data phase) are supported for any non-dword aligned addresses. [FRD_NGNICVBPCI_PCI_0510>HRD_NGNIC_BP_0102 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0510>HRD_NGNIC_BP_0102" ] [FRD_NGNICVBPCI_PCI_0510>HRD_NGNIC_FUNC_0085 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0510>HRD_NGNIC_BP_0102" ] The NG_NICVBPCI FPGA shall implement the VbPCI master signals VB_FRAME_N, VB_IRDY_N, and VB_PERR_N as sustained tri-state signals during master transactions performed across the VbPCI backplane (PCI bus 1). Commentary: The PCI protocol requires that the above signals be implemented as sustained tri-state signals. These signals will be driven low during assertion and, when released, will be driven high for one clock before being tri-stated by the NG_NICVBPCI FPGA. See chapter 2 of the Local PCI specification version 2.1 for more information on sustained tri-state signals. [FRD_NGNICVBPCI_PCI_0520>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0520>DERIVED" ] The NG_NICVBPCI FPGA shall implement the VbPCI master signal VB_SERR_N as an open drain signal during master transactions performed across the VbPCI backplane (PCI bus 1). 3.3.6.1.1 VbPCI Memory Reads and Writes [FRD_NGNICVBPCI_PCI_0550>HRD_NGNIC_Func_0030 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0550>HRD_NGNIC_Func_0030" ] A CPU Memory Write in the VbPCI Bus 1 or the VbPCI Broadcast address range shown in Table 10 shall cause the FPGA to perform a PCI Memory Write on the VbPCI Bus 1. [FRD_NGNICVBPCI_PCI_0551>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0551>DERIVED" ] VbPCI Master Functions shall assert VB_DEVSEL_N after VB_FRAME_N was asserted followed by VB_TRDY_N assertion two CLK25 periods later when CPU writes into the VbPCI Broadcast address range. Commentary: The VbPCI Master responds to decoded-owned Broadcast Memory Write transactions as the target agent and the VbPCI Client snoops the write data of the transaction. Since broadcast transactions target all of the devices on the VbPCI bus, the transaction is claimed and terminated by the bus master. The timing here is a legacy requirement necessary for client BICs to correctly recognize broadcast operations [FRD_NGNICVBPCI_PCI_0552.>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0552>DERIVED" ] The NG_NICVBPCI FPGA shall implement the VbPCI target signals VB_TRDY_N and VB_DEVSEL_N as sustained tri-state signals when CPU writes into the VbPCI Broadcast address range. [FRD_NGNICVBPCI_PCI_0560>HRD_NGNIC_Func_0020 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0560>HRD_NGNIC_Func_0020" ] A CPU Memory Read in the VbPCI bus 1 address range shown in Table 10 shall cause the FPGA to perform a PCI Memory Read on the VbPCI Bus 1. Commentary: Reads to the VbPCI Broadcast address range are not supported. 3.3.6.1.2 VbPCI Bus 1 Configuration Reads and Writes Table 12 shows the I/O address map associated with VbPCI Bus 1 configuration cycle generation registers. This is a PCI to PCI bridge functionality refer to section 3.7.4 of the Local PCI specification version 2.1 for more information on how bridges should generate type 0 configuration cycles. Table 12 – VbPCI Bus 1 I/O Address Map I/O Register Address CPU_A(15:2) Access Data Bits CONFIG_ADDR 0CF8H Read/Write D(31:0) CONFIG_DATA 0CFCH Read/Write D(31:0) [FRD_NGNICVBPCI_PCI_0570>HRD_NGNIC_Func_0060 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0570>HRD_NGNIC_Func_0060" ] A double word CPU I/O Write to the CONFIG_ADDR address shown in Table 12 shall cause the register to be written. Commentary: When the CPU writes to the CONFIG_ADDR location, it is actually writing to two registers (or three if the dual-slot NIC mezzanine card is installed). The NIC Core FPGA implements the CONFIG_ADDR register for Local PCI Bus 0. The NG_NICVBPCI FPGA contains the CONFIG_ADDR register for VbPCI Bus 1. And the CONFIG_ADDR register for VBPCI Bus 2 is in the PM-NIC VbPCI Master FPGA (on dual-slot NIC mezzanine card). Because this is a “shared” register, only one of the FPGAs can terminate the CPU access. This is done by the NIC VbPCI FPGA. Furthermore, during CPU reads of the CONFIG_ADDR register, only the NIC VbPCI FPGA drives the data on PCI Bus 0. [FRD_NGNICVBPCI_PCI_0580>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0580>DERIVED" ] The NG_NICVBPCI FPGA shall assert PCI_TRDY_N (PCI local bus 0) during CPU accesses, and drive the PCI_AD (PCI 0) bus during CPU read accesses, to the CONFIG_ADDR register. [FRD_NGNICVBPCI_PCI_0590>HRD_NGNIC_Func_0070 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0590>HRD_NGNIC_Func_0070" ] If bits 31, 17, and 16 of the CONFIG_ADDR register contain 1, 0, and 1 respectively, as shown in Table 13, a CPU I/O Write to the CONFIG_DATA address shown in Table 12 shall cause the FPGA to perform a PCI Configuration Write on VbPCI Bus 1. [FRD_NGNICVBPCI_PCI_0600>HRD_NGNIC_Func_0070 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0600>HRD_NGNIC_Func_0070" ] If bits 31, 17 and 16 of the CONFIG_ADDR register contain 1, 0, and 1 respectively, as shown in Table 13, a CPU I/O Read to the CONFIG_DATA address shown in Table 12 shall cause the FPGA to perform a PCI Configuration Read on VbPCI Bus 1. Table 13 – CONFIG_ADDR Register D31 D30-D18 D17-D16 D15-D11 D10-D8 D7-D2 D1-D0 Enable Don’t Care PCI Bus Number Device Number Function Number Register Number Don’t Care ‘1’ = Enable ‘0’ = Disable “00” = Local Bus 0 “01” = VbPCI Bus 1 “10” = VbPCI Bus 2 [FRD_NGNICVBPCI_PCI_0610>HRD_NGNIC_Func_0075 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0610>HRD_NGNIC_Func_0075" ] During a PCI Configuration Read or PCI Configuration Write, the NG_NICVBPCI FPGA shall translate the value stored in bits 15:11 of the CONFIG_ADDR register to an address that is driven on the VB_AD bus for the address phase of the PCI transaction, as shown in Table 14. Table 14 – Translation of CONFIG_ADDR to VB_AD VB_AD (31:23) VB_AD(22:11) VB_AD (10:8) VB_AD (7:2) VB_AD (1:0) CONFIG_ADDR (15:11) Function Number Register Number “00000” “100000000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00001” “010000000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00010” “001000000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00011” “000100000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00100” “000010000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00101” “000001000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00110” “000000100” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “00111” “000000010” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” “01000” “000000001” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” Others “000000000” all bits ‘0’ CONFIG_ADDR(10:8) CONFIG_ADDR(7:2) “00” 3.3.6.1.3 VbPCI Error Handling The NIC VbPCI Master provides error detection and reporting. This section describes how the NG_NICVBPCI Master handles different error (or interrupt) conditions. Errors detected by the VbPCI Master are reported by asserting internal error signals for each detected error. The system error (SERR) and parity error (PERR) signals are used to report errors on the VbPCI bus. The VbPCI Master function receives and generates VB_SERR_N (system error) and VB_PERR_N (parity error) during PCI transactions on the VbPCI backplane. The VbPCI Master function also receives a VB_STOP_N signal. Whenever VB_SERR_N occurs or if the VB_STOP_N signal is asserted, the VbPCI Master function ends the transaction on the VbPCI backplane and sends VB_SERR_INT_L and VB_STOP_INT_L interrupts to the NIC CPU. Whenever VB_PERR_N occurs the VbPCI Master function sends VB_PERR_INT_L interrupt to the NIC CPU. [FRD_NGNICVBPCI_PCI_0620>HRD_NGNIC_Func_0100 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0620>HRD_NGNIC_Func_0100" ] If VB_DEVSEL_N has not been asserted five CLK_25 clock cycles after the NICVBPCI FPGA asserts VB_FRAME_N, the FPGA shall assert VB_SERR_N for one CLK_25 clock cycle, complete the PCI Bus 0 transaction, and terminate the VbPCI Bus 1 transaction by master abort. Commentary: Master abort is defined in section 3.3.3.1 of the PCI Local Bus Specification. [FRD_NGNICVBPCI_PCI_0630>HRD_NGNIC_Func_0110 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0630>HRD_NGNIC_Func_0110" ] If VB_TRDY_N has not been asserted sixteen CLK_25 clocks cycles after the NICVBPCI FPGA asserts VB_FRAME_N, the FPGA shall assert VB_SERR_N for one CLK_25 clock cycle, complete the PCI Bus 0 transaction, and complete the VbPCI Bus 1 transaction. Commentary: Completion of operation is defined as a regular transaction completion by master. Master simply indicates that given data phase is the last to be performed. Refer to section 3.3.3.1 of the PCI Local Bus Specification. [FRD_NGNICVBPCI_PCI_0635>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0630>HRD_NGNIC_Func_0110" ] If VB_SERR_N is asserted due to VB_DEVSEL_N or VB_TRDY_N timeout error during PCI0 read operation the NICVBPCI FPGA shall return all 1’s on PCI Bus 0 PCI_AD lines. [FRD_NGNICVBPCI_PCI_0640>HRD_NGNIC_Func_0085 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0640>HRD_NGNIC_Func_0090" ] [FRD_NGNICVBPCI_PCI_0640>HRD_NGNIC_Func_0090 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0640>HRD_NGNIC_Func_0090" ] VB_PERR_N shall be asserted if VB_PAR does not provide even parity across VB_AD(31:0) and VB_C_BE_N(3:0) during the data phase of a read on VbPCI Bus 1. Commentary: Correct even parity occurs when the number of 1’s on VB_AD(31:0), VB_C_BE_N(3:0), and VB_PAR is an even number. Commentary: A VbPCI client must always assert VB_PERR_N two clocks after a data transfer in which an error occurred. Once VB_PERR_N is asserted it must remain asserted until two clocks following the actual transfer. See PCI rev.2.1 spec, section 3.8.2.1. [FRD_NGNICVBPCI_PCI_0645>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0640>HRD_NGNIC_Func_0090" ] When VB_SERR_N is asserted during broadcast operation VbPCI FPGA shall complete transaction on VbPCI Bus 1. Commentary: Since Broadcast operation is a deviation form PCI spec error handling behavior for such operation has to be defined. During broadcasts VbPCI master acts both as Master and slave (drives VB_TRDY_N and VB_TRDY_N). Strategy was defined to complete broadcast operation (master Completion) in order to gracefully bring PCI bus 1 to Idle state. PCI spec expects SERR_N to result in complete system reset, this may not be the case for NG_NIC. CPU will be informed about error condition by means of VB_SERR_N_INT (see below). [FRD_NGNICVBPCI_PCI_0650>HRD_NGNIC_Func_0235 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0650>HRD_NGNIC_Func_0235" ] [FRD_NGNICVBPCI_PCI_0650>HRD_NGNIC_Func_0237 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0650>HRD_NGNIC_Func_0237" ] VB_PERR_INT_L shall be asserted for a time period of to four to seven PCI_CLK clock cycles when VB_PERR_N is asserted. [FRD_NGNICVBPCI_PCI_0660>HRD_NGNIC_Func_0200 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0660>HRD_NGNIC_Func_0200" ] [FRD_NGNICVBPCI_PCI_0660>HRD_NGNIC_Func_0210 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0660>HRD_NGNIC_Func_0210" ] VB_SERR_INT_L shall be asserted for a time period of to four to seven PCI_CLK clock cycles when VB_SERR_N is asserted. [FRD_NGNICVBPCI_PCI_0670>HRD_NGNIC_Func_0220 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0670>HRD_NGNIC_Func_0220" ] [FRD_NGNICVBPCI_PCI_0670>HRD_NGNIC_Func_0230 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0670>HRD_NGNIC_Func_0230" ] When VB_STOP_N is asserted, the NG_NICVBPCI FPGA shall assert VB_STOP_INT_L for a time period of five to eight PCI_CLK clock cycles and terminate the VbPCI Bus 1 transaction as defined in section 3.3.3.2 of the PCI Local Bus Specification. 3.3.6.2 VbPCI Bus Request/ Bus Arbitration The VB_NIC_GNT_N line provided to all clients on the backplane PCI bus 1 is used to enable clients to respond to backplane transactions from the master. The NIC is the only master on VBPCI bus (PCI bus 1). Each module (or each slot) is supplied with an REQ_N line and a GNT_N line. These lines will be used for fault isolation functions. NOTE: The ability to have multiple VbPCI bus masters is not required in the MAU system, so this functionality is removed. [FRD_NGNICVBPCI_PCI_0680>HRD_NGNIC_Func_0250 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0680>HRD_NGNIC_Func_0250" ] [FRD_NGNICVBPCI_PCI_0680>HRD_NGNIC_Func_0260 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0680>HRD_NGNIC_Func_0260" ] NG_NICVbPCI Master Function shall drive signal VB_NIC_GNT_N low for all transactions. Commentary: See chapter 3.4 of the Local PCI specification version 2.1 for more information. 3.3.6.3 VbPCI Test Registers To facilitate testing of the VbPCI bus, test registers are built into the hardware. The System Error Test register is located in the CPU address region for VbPCI Bus 1. CPU writes to the each System Error Test register (2F000000 for VbPCI Bus 1 and 3F000000 for VbPCI Bus 2 if mezzanine card is connected). Writing to these registers will generate a PCI write transaction with incorrect even parity during the address phase. All BICs will assert SERR# simultaneously and set the SERR# error bit in their status registers. Upon detection of the SERR# backplane signal, the SERR interrupt will be asserted by the NG_NICVBPCI FPGA The Parity Error Test register is a PCI Configuration register that is accessed via the CONFIG_ADDR and CONFIG_DATA registers. To test that each BIC asserts PERR# correctly, the master performs a PCI write to a client’s Parity Error Test register with incorrect even parity during the data phase. Each target will assert PERR# and set PERR# error bit in their status register. Upon detection of the PERR# backplane signal, the PERR# interrupt will be asserted by the NG_NICVBPCI FPGA. NOTE: To generate incorrect even parity, VB_PAR will be driven such that the number of 1’s on VB_AD(31:0), VB_C_BE_N(3:0), and VB_PAR is an odd number. [FRD_NGNICVBPCI_PCI_0690>HRD_NGNIC_Safe_0005 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0690>DERIVED" ] A CPU Memory Write to the System Error Test register shown in Table 15 shall cause the NG_NICVBPCI FPGA to generate incorrect even parity on VB_PAR during the address phase of the PCI Memory Write transaction. Table 15 – VbPCI Bus 1 Test Memory Map Register CPU Address Decoded Address Bits* Access Type Data Bits 31:24 7:2 System Error Test 2F00:0000H 2FH x Write N/A Parity Error Test 0000:0054H X 15H Write N/A * The decoded address bits show how the register addresses are shadowed within the FPGA. [FRD_NGNICVBPCI_PCI_0700>HRD_NGNIC_Safe_0005 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0700>DERIVED" ] A PCI Configuration Write to the Parity Error Test register shown in Table 15 shall cause the NG_NICVBPCI FPGA to generate incorrect even parity on VB_PAR during the data phase of the VbPCI Configuration Write transaction. This is accomplished by first performing a CPU I/O Write to the CONFIG_ADDR register (0CF8H) with D31 = ‘1’, D17-D16 = “01”, and D7-D2 = “010101”. Any subsequent CPU I/O Write to the CONFIG_DATA register (0CFCH) executes a PCI Configuration Write to the Parity Error Test register. 3.3.6.4 VbPCI Bus 1 Last Transaction Registers The NIC module has up to three PCI busses. These three busses are PCI Bus 0 (local PCI), VbPCI Bus 1, and VbPCI Bus 2 (only present on dual NIC modules). The NG_NICVBPCI FPGA provides the interface to VbPCI Bus 1. The VbPCI Bus 1 last command register is a read-only register that contains the command value for the last PCI transaction that was performed on VbPCI Bus 1. The VbPCI Bus 1 last address register is also read-only and contains the address value for the last PCI transaction. The VbPCI Bus1 last command register and last address register may assist in software diagnosis of errors that triggered STOP_N, PERR_N and SERR_N interrupts [FRD_NGNICVBPCI_PCI_0710>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0710>DERIVED" ] The CPU Address and Access Type for the VbPCI Bus 1 Last Transaction registers shall be as defined in Table 16. [FRD_NGNICVBPCI_PCI_0720>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0720>DERIVED" ] The VbPCI Bus 1 Last Transaction registers shall be initialized to the Reset Value shown in Table 16 when CCA_RST_N is asserted. Table 16 – VbPCI Bus 1 Last Transaction Memory Map Register Name CPU Address Decoded Address bits* Access Type Data Width Reset Value 31:20 15:12 VbPCI Bus 1 Last Command 7810:B000H 781H BH Read D(3:0) FH VbPCI Bus 1 Last Address 7810:A000H 781H AH Read D(31:0) FFFF_FFFCH * The decoded address bits show how the register addresses are shadowed within the FPGA. [FRD_NGNICVBPCI_PCI_0730>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0730>DERIVED" ] A CPU Memory read of the VbPCI Bus 1 Last Command register shall return the state of the PCI command/byte enable bus (VB_C_BE_N) during the address phase of the last transaction on VbPCI Bus 1, as shown in Table 17. Table 17 – VbPCI Bus 1 Last Command Register D31-D4 D3-D0 all bits ‘0’ VB_C_BE_N(3:0) [FRD_NGNICVBPCI_PCI_0740>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0740>DERIVED" ] A CPU Memory read of the VbPCI Bus 1 Last Address register shall return the state of the PCI address/data bus (VB_AD) during the address phase of the last transaction on VbPCI Bus 1, as shown in Table 18. Table 18 – VbPCI Bus 1 Last Address Register D31-D2 D1-D0 VB_AD(31:2) “00” [FRD_NGNICVBPCI_PCI_0750>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0750>DERIVED" ] CPU Memory writes to the VbPCI Bus 1 Last Transaction registers shall be terminated with no action taken (Read only). [FRD_NGNICVBPCI_PCI_0760>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0760>DERIVED" ] The PCI bus 1 last address register shall contain the most recent address issued on VB_AD(31:2) on the VbPCI backplane. [FRD_NGNICVBPCI_PCI_0770>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0770>DERIVED" ] The PCI bus 1 last command register shall contain the most recent bus command issued on VB_C_BE_N(3:0) on the VbPCI backplane. 3.3.7 Aircraft Personality Module (APM) Interface The APM (Aircraft Personality Module) will be mounted external to the MAU cabinet and connected to the NIC through its front connector. The interface to the NIC will be based on a Serial Peripheral Interface (SPI) protocol. The certified configuration of the aircraft can be read through this interface to compare against the actual configuration for Return to Service considerations. The digital portion of the APM interface is contained in the NG_NICVBPCI FPGA. The Serial Peripheral Interface (SPI) port built into the NG_NICVBPCI FPGA. The SPI controller generates APM_CLK 1.5625 MHz by dividing the CLK_25 (25 MHz) down. The SPI controller has a number of memory mapped registers. The current APM contains a 16Kbyte serial EEPROM. The EEPROM internal status register indicates if a write is in progress and allows control over the write protect mechanisms available in the part. See the Xicor X25128 (or Catalyst CAT25C128) data sheet for more information on the configuration of the status register. The 16Kbyte contiguous block starts at address 7E010000h. One byte to four bytes may be written before the EEPROM begins its internal write process. After the internal write process has started the EEPROM can take up to 10ms to finish the write cycle. Byte, word or double word accesses may be made to the APM. The hardware interface to the APM always does 32 bit accesses, so double word accesses provide the most efficient use of the interface. Accesses to the APM are controlled by an 8 bit address mapped command that is generated on every CPU access to the APM, see Table 19. The EEPROM memory must be write-enabled by setting the Write Enable Latch (WEL) issuing the WREN instruction before every write access. The WEL bit is reset automatically after every write access to the serial EEPROM memory of status register. To write data to the Xicor X25128 (or Catalyst CAT25C128) EEPROM memory array, the user issues the write instruction, followed by the address and then the data to be written. This is 32 clock min. operation. APM_CS must go high and remain high for the duration of the operation. NOTE: Since board level inverting Schmitt triggers are applied on all APM interface signals FPGA must compensate for this fact and all APM signals at FPGA pins have inverted polarity with regard to levels described in datasheets of the respective eeprom devices. The host may continue to write up to 32 bytes of data to the Xicor X25128 (or Catalyst CAT25C128). The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. To read data from the Xicor X25128 (or Catalyst CAT25C128) EEPROM, the APM_CS is first pulled high to select the device. The 8-bit read instruction is transmitted to the Xicor X25128 (or Catalyst CAT25C128), followed by the 16-bit address. After the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the APM_DO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached the address counter rolls over to address $0000 allowing the read cycle to be continued. See the Xicor X25128 (or Catalyst CAT25C128) data sheet for more information. [FRD_NGNICVBPCI_APM_0775> HRD_NGNIC_Func_0680 XE \f "TRACETAG" "FRD_NGNICVBPCI_PCI_0770>DERIVED" ] The NG_NIC_VBPCI FPGA shall implement protocol per Xicor X25128 and CAT25C128 datasheet to allow correct operation with APM module using either of the parts. Table 19 – APM Register Memory Map Register Name CPU Address Decoded Address Bits* Access Type Reset Value 31:24 16,13,12 APM Status** 7E00:0000H 7EH 000b Read/Write undefined APM WREN*** 7E00:1000H 7EH 001b Write N/A APM WRDI*** 7E00:2000H 7EH 01-b Write N/A APM MEM 7E01:0000H 7EH 1—b Read/Write N/A * The decoded address bits show how the register addresses are shadowed within the FPGA. ** The status register is located in the APM, external to the FPGA. *** WREN and WRDI are address-mapped instructions that are sent serially to the APM. [FRD_NGNICVBPCI_APM_0780>HRD_NGNIC_Func_0662 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0780>HRD_NGNIC_Func_0662" ] [FRD_NGNICVBPCI_APM_0780>HRD_NGNIC_Func_0666 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0780>HRD_NGNIC_Func_0666" ] The access type, reset value, and actual decoded CPU address bits for the APM registers and memory shall be as defined in Table 19. [FRD_NGNICVBPCI_APM_0790>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0790>DERIVED" ] APM_CLK shall be held at ‘1’ when no CPU bus cycle is accessing the APM. Commentary: The Serial Clock controls the serial bus timing for data input and output. Addresses, or data present on the SDI pin are latched on the rising edge of the clock input, while data on the SDO pin change after the falling edge of the clock input. Data input is sampled on the first rising edge of APM_SCK after chip select goes low. APM_SCK is static, allowing the user to stop the clock and then resume operations. [FRD_NGNICVBPCI_APM_0800>HRD_NGNIC_Func_0664 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0800>HRD_NGNIC_Func_0664" ] APM_CLK shall be a 1.5625 ± 0.008 MHz clock. [FRD_NGNICVBPCI_APM_0810>HRD_NGNIC_Func_0668 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0810>HRD_NGNIC_Func_0668" ] The APM Interface shall accept byte, word, and double word writes from the CPU. Commentary: During an APM Status Register write, PCI_AD(31:24) data bits are written to the 8 bit status register. The 14 bit starting byte memory address for APM Memory Writes is constructed from PCI_AD (13:2) address and a 2-bit value derived from the CPU Byte Enables, see Table 20. After the APM Status Register is loaded, the APM Serial Data Out Register will be shifted by one bit from the LSB to MSB every APM_CLK cycle. APM_DO will be connected to the MSB of the APM Serial Data Out Register Table 20 – APM Serial Data Out (SDO) Register ACCESS TYPE SDO BITS 55-48 SDO BITS 47-40 SDO BITS 39-34 SDO BITS 33-32 SDO BITS 31-24 SDO BITS 23-16 SDO BITS 15-8 SDO BITS 7-0 APM STATUS READ 0000:0101 PCI_D31-24 DONT CARE DONT CARE DONT CARE Don’t CARE DONT CARE DONT CARE APM STATUS WRITE 0000:0001 PCI_D31-24 DONT CARE DONT CARE DONT CARE Don’t CARE DONT CARE DONT CARE APM WREN WRITE 0000:0110 PCI_A15-8 PCI_A7-2 DONT CARE DONT CARE Don’t CARE DONT CARE DONT CARE APM WRDI WRITE 0000:0100 PCI_A15-8 PCI_A7-2 DONT CARE DONT CARE Don’t CARE DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 0000 0000:0010 PCI_A15-8 PCI_A7-2 00 PCI_D7-0 PCI_D15-8 PCI_D23-16 PCI_D31-24 APM MEM WRITE, PCI_BE(3:0)_N = 1110 0000:0010 PCI_A15-8 PCI_A7-2 00 PCI_D7-0 Don’t CARE DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 1101 0000:0010 PCI_A15-8 PCI_A7-2 01 PCI_D15-8 Don’t CARE DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 1011 0000:0010 PCI_A15-8 PCI_A7-2 10 PCI_D23-16 Don’t CARE DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 0111 0000:0010 PCI_A15-8 PCI_A7-2 11 PCI_D31-24 Don’t CARE DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 1100 0000:0010 PCI_A15-8 PCI_A7-2 00 PCI_D7-0 PCI_D15-8 DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 1001 0000:0010 PCI_A15-8 PCI_A7-2 01 PCI_D15-8 PCI_D23-16 DONT CARE DONT CARE APM MEM WRITE, PCI_BE(3:0)_N = 0011 0000:0010 PCI_A15-8 PCI_A7-2 10 PCI_D23-16 PCI_D31-24 DONT CARE DONT CARE APM MEM READ 0000:0011 PCI_A15-8 PCI_A7-2 00 PCI_D7-0 PCI_D15-8 PCI_D23-16 PCI_D31-24 [FRD_NGNICVBPCI_APM_0820>HRD_NGNIC_Func_0662 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0820>HRD_NGNIC_Func_0662" ] [FRD_NGNICVBPCI_APM_0820>HRD_NGNIC_Func_0668 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0820>HRD_NGNIC_Func_0668" ] At the start of a CPU bus Read access of the APM, the desired APM data shall be placed onto the CPU Data Bus as indicated in Table 21. Commentary: All CPU Reads of the APM memory return 4 bytes with byte (0) being the word location addressed by PCI_A(13:2). A CPU Read of the APM Status register returns the 8 bits in PCI_D(31:24) as shown in Table 21. [FRD_NGNICVBPCI_APM_0830>HRD_NGNIC_Func_0662 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0830>HRD_NGNIC_Func_0662" ] [FRD_NGNICVBPCI_APM_0830>HRD_NGNIC_Func_0674 XE \f "TRACETAG" "FRD_NGNICVBPCI_APM_0830>HRD_NGNIC_Func_0662" ] During APM accesses, the APM serial data shall be sent and received MSB first. Table 21 – APM Serial Data In (SDI) Register Access TYPE PCI_D (31:24) PCI_D (23:16) PCI_D (15:8) PCI_D (7:0) APM MEM READ APM MEM BYTE (3) APM MEM BYTE (2) APM MEM BYTE (1) APM MEM BYTE (0) APM STATUS READ APM STATUS (7:0) DONT CARE DONT CARE DONT CARE 3.3.8 FPGA ID and Modul ID The FPGA Rev.Num. register is a read-only register. S/W reads of the Module ID return an ID byte that is specific to a particular module type and FPGA Revision number byte. The Module ID byte consists of bits 0 though bit 7. Bits 0 and 1 indicate that Mezzanine Connection exists or not. Two bits are used in order to preserve even parity across the byte. The Module ID bits 7:2 are hard wired in the NG_NICVBPCI. The FPGA Revision Number Byte is hardwired in the NG_NICVBPCI. [FRD_NGNICVBPCI_ID_0840>HRD_NGNIC_CoreFunc_1240 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0840>HRD_NIC_CoreFunc_1240" ] [FRD_NGNICVBPCI_ID_0840>HRD_NGNICM_Mod_0070 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0840>HRD_NGNICM_Mod_0070" ] The CPU Address and Access Type for the NG_NICVBPCI FPGA revision number register shall be as defined in Table 22. Table 22 – FPGA Revision Register Memory Map Register Name CPU Address Decoded Address Bits* Access Type Data Width Reset Value 31:20 FPGA Rev.Num. 7190:0000H 719H Read D(31:0) Don't Care * The decoded address bits show how the register addresses are shadowed within the FPGA. [FRD_NGNICVBPCI_SAFE_0850>HRD_NGNIC_CoreSafe_0130 XE \f "TRACETAG" "FRD_NGNICVBPCI_SAFE_0850>HRD_NGNIC_CoreSafe_0130" ] [FRD_NGNICVBPCI_ID_0850>HRD_NGNICM_Mod_0090 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0850>HRD_NGNICM_Mod_0090" ] [FRD_NGNICVBPCI_ID_0850> HRD_NGNIC_CoreFunc_1210 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0850>HRD_NGNICM_Mod_0090" ] [FRD_NGNICVBPCI_ID_0850> HRD_NGNIC_CoreFunc_1220 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0850>HRD_NGNICM_Mod_0090" ] The internal representation of the FPGA Rev. Num. register shall be as described in Figure 3 – 3. Commentary: The module ID includes an 8th bit for use as a parity bit. 31 24 23 16 15 8 7 0 00h 00h FPGA Rev Num Module ID Figure 3 – FPGA Rev. Register format [FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080" ] The NG_NICVBPCI FPGA revision number shall be an 8-bit binary number. [FRD_NGNICVBPCI_ID_0862> HRD_NGNIC_CoreFunc_1200 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080" ] [FRD_NGNICVBPCI_ID_0862> HRD_NGNIC_CoreFunc_1250 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080" ] The Module ID shall be ACh when the IM_here_n signal/input pin is de-asserted. [FRD_NGNICVBPCI_ID_0864> HRD_NGNICM_Mod_0040 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080" ] [FRD_NGNICVBPCI_ID_0864> HRD_NGNIC_CoreFunc_1200 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080" ] [FRD_NGNICVBPCI_ID_0864> HRD_NGNIC_CoreFunc_1250 XE \f "TRACETAG" "FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080" ] The Module ID shall be 2Dh when the IM_here_n signal/input pin is asserted. 3.3.9 Discrete Outputs The discrete output interface allows S/W to set/clear external pins on the FPGA or internal signals within the FPGA. Each discrete output bit (or group of bits) is given a unique register address for S/W access. To support DEOS each register address is mapped on a 4K boundary. Each register is writeable using the PCI data bus. The reads for each DOUT address contain all discrete output values arranged according to their DOUT number. During a S/W write to any of the Discrete output registers within the NG_NICVBPCI FPGA, the value of PCI data bus bit defined in Table 23 is written into the addressed Discrete Output Register. For S/W reads, the discrete outputs belong to one of two groups. A S/W read from any Discrete output register address associated with a particular group will return the state of all supported discrete outputs within that group. Unused outputs will return '0' in their corresponding group's bit position. Douts 0 - 31 belong to discrete output group 1 and Douts 32 - 63 belong to discrete output group 2. [FRD_NGNICVBPCI_DIO_0870>HRD_NGNIC_CoreFunc_0830 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0870>HRD_NGNIC_CoreFunc_0830" ] The CPU Address for the Discrete Output (DOUT) registers shall be as defined in Table 23. [FRD_NGNICVBPCI_DIO_0880>HRD_NGNIC_CoreFunc_0830 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0880>HRD_NGNIC_CoreFunc_0830" ] [FRD_NGNICVBPCI_DIO_0880>HRD_NGNIC_CoreFunc_0820 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0880>HRD_NGNIC_CoreFunc_0820" ] The NG_NICVBPCI discrete outputs shall be write-addressable as shown in Table 23. [FRD_NGNICVBPCI_DIO_0890>HRD_NGNIC_Func_0265 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0890>HRD_NIC_Func_0265" ] [FRD_NGNICVBPCI_DIO_0890>HRD_NGNIC_Func_0270 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0890>HRD_NIC_Func_0265" ] [FRD_NGNICVBPCI_DIO_0890>HRD_NGNIC_Func_0280 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0890>HRD_NIC_Func_0265" ] When the CPU writes to the Discrete Output registers, the value on the PCI data bus bit defined in the Write Data Bit column of Table 23 shall be latched in to the corresponding DOUT. [FRD_NGNICVBPCI_DIO_0900>HRD_NGNIC_CoreFunc_0830 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0900>HRD_NGNIC_CoreFunc_0830" ] [FRD_NGNICVBPCI_DIO_0900>HRD_NGNIC_CoreFunc_0820 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0900>HRD_NGNIC_CoreFunc_0820" ] The NG_NICVBPCI discrete outputs, DOUT31-0, shall be read addressable at the addresses indicated in Table 23 for DOUTS Group 1. [FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0830 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0830" ] [FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0820 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0820" ] [FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_Safe_0180 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0820" ] The NG_NICVBPCI discrete outputs, DOUT63-32, shall be read addressable at the addresses indicated in Table 23 for DOUTS Group 2. Table 23 – Discrete Output Registers Memory Map Register Name (DOUT Number) Discrete Output CPU Address Decoded Address Bits* Write Data Bit Read data Bit 31:16 15:12 DOUTs Group 1 Discrete Output 0 Reserved** 7210:0000H 7210H 0000b PCI_D(0) PCI_D(0) Discrete Output 11 PSBUS 0 7210:B000H 7210H 1011b PCI_D(0) PCI_D(11) Discrete Output 12 PSBUS 1 7210:B000H 7210H 1011b PCI_D(1) PCI_D(12) Discrete Output 13 PSBUS 2 7210:B000H 7210H 1011b PCI_D(2) PCI_D(13) Discrete Output 14 PSBUS 3 7210:B000H 7210H 1011b PCI_D(3) PCI_D(14) Discrete Output 15 PSBUS 4 7210:B000H 7210H 1011b PCI_D(4) PCI_D(15) Discrete Output 19 VB_RST_LOCK 7211:3000H 7211H 0011b PCI_D(0) PCI_D(19) Discrete Output 20 VB_RST_N 7211:4000H 7211H 0100b PCI_D(0) PCI_D(20) DOUTs Group 2 Discrete Output 32 Fail_1_5V_Hi 7212:0000H 7212H 0000b PCI_D(0) PCI_D(0) Discrete Output 33 Fail_1_5V_low 7212:1000H 7212H 0001b PCI_D(0) PCI_D(1) Discrete Output 34 Fail_3_3V_Hi 7212:2000H 7212H 0010b PCI_D(0) PCI_D(2) Discrete Output 35 Fail_3_3V_Low 7212:3000H 7212H 0011b PCI_D(0) PCI_D(3) Discrete Output 39 FAN_ON1 7212:7000H 7212H 0111b PCI_D(0) PCI_D(7) Discrete Output 40 FAN_ON2 7212:8000H 7212H 1000b PCI_D(0) PCI_D(8) Discrete Output 41 FAN_ON3 7212:9000H 7212H 1001b PCI_D(0) PCI_D(9) Discrete Output 42 FAN_ON4 7212:A000H 7212H 1010b PCI_D(0) PCI_D(10) Discrete Output 43 VB_SLOT_RST0 7212:B000H 7212H 1011b PCI_D(0) PCI_D(11) Discrete Output 44 VB_SLOT_RST1 7212:B000H 7212H 1011b PCI_D(1) PCI_D(12) Discrete Output 45 VB_SLOT_RST2 7212:B000H 7212H 1011b PCI_D(2) PCI_D(13) Discrete Output 46 VB_SLOT_RST3 7212:B000H 7212H 1011b PCI_D(3) PCI_D(14) Discrete Output 47 VB_SLOT_RST4 7212:B000H 7212H 1011b PCI_D(4) PCI_D(15) Discrete Output 48 VB_SLOT_RST5 7212:B000H 7212H 1011b PCI_D(5) PCI_D(16) Discrete Output 49 VB_SLOT_RST6 7212:B000H 7212H 1011b PCI_D(6) PCI_D(17) Discrete Output 50 VB_SLOT_RST7 7212:B000H 7212H 1011b PCI_D(7) PCI_D(18) Discrete Output 51 SLOT_SERR_RST 7213:3000H 7213H 0011b PCI_D(0) PCI_D(19) Discrete Output 52 DPRAM_CHIP_SEL 7213:4000H 7213H 0100b PCI_D(0) PCI_D(20) Discrete Output 53 APM_SHDN_N 7213:5000H 7213H 0101b PCI_D(0) PCI_D(21) * The decoded address bits show how the register addresses are shadowed within the FPGA. ** This Reserved bit is a read/write register, but it is not connected to an output pin on the FPGA. [FRD_NGNICVBPCI_DIO_0920>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0920>DERIVED" ] During CPU reads of the Discrete Outputs registers, the bits of the PCI data bus not listed in Table 23 shall return a logic '0' in their corresponding group bit positions. [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_Func_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330" ] [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_Func_0350 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330" ] [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_Func_0360 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330" ] [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_Func_0370 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330" ] [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_Func_0380 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330" ] [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_Func_0440 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330" ] [FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_CoreFunc_0038 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_CoreFunc_0038" ] Discrete Output register bits shall be initialized to the Reset Value shown in Table 24 when CCA_RST_N is asserted. Table 24 – Discrete Outputs DOUT BIT Discrete Output Description Reset Value Comment 0 Reserved 0 1-10 Not used 0 11 PSBUS 0* Power supply #1 output discrete bus, Bit 0 0 External output 12 PSBUS 1* Power supply #1 output discrete bus, Bit 1 0 External output 13 PSBUS 2* Power supply #1 output discrete bus, Bit 2 0 External output 14 PSBUS 3* Power supply #1 output discrete bus, Bit 3 0 External output 15 PSBUS 4* Power supply #1 output discrete bus, Bit 4 0 External output 16-18 Not used 0 19 VB_RST_LOCK VbPCI Bus 1 Reset Lockout 0 External output 20 VB_RST_N VbPCI Bus 1 Reset 0 External output 21-31 Not used 0 32 Fail_1_5V_Hi Local PS 1.5V Ove rvoltage Test 0 External output 33 Fail_1_5V_low Local PS 1.5V Under rvoltage Test 0 External output 34 Fail_3_3V_Hi Local PS 3.3V Over voltage Test 0 External output 35 Fail_3_3V_Low Local PS 3.3V Under voltage Test 0 External output 36-38 Not used 0 39 FAN_ON1 Fan 1 on/off. ‘1’ turns on MAU fan #1 0 External output 40 FAN_ON2 Fan 1 on/off. ‘1’ turns on MAU fan #2 0 External output 41 FAN_ON3 Fan 1 on/off. ‘1’ turns on MAU fan #3 0 External output 42 FAN_ON4 Fan 1 on/off. ‘1’ turns on MAU fan #4 0 External output 43 VB_SLOT_RST0 Independent reset for module at slot 0 1 External output 44 VB_SLOT_RST1 Independent reset for module at slot 1 1 External output 45 VB_SLOT_RST2 Independent reset for module at slot 2 1 External output 46 VB_SLOT_RST3 Independent reset for module at slot 3 1 External output 47 VB_SLOT_RST4 Independent reset for module at slot 4 1 External output 48 VB_SLOT_RST5 Independent reset for module at slot 5 1 External output 49 VB_SLOT_RST6 Independent reset for module at slot 6 1 External output 50 VB_SLOT_RST7 Independent reset for module at slot 7 1 External output 51 SLOT_SERR_RST Reset for all SERR# latches 0 Internal signal 52 DPRAM_Chip_Sel Select between NIC DPRAM bank 0 and LAN DPRAM bank 1 0 Internal signal 53 APM_SHDN_N Indicated that APM power is shot down 1 External output 54-63 Not used 0 * These discretes were provided to satisfy top level HRD requirement HRD_NGNIC_Func_0270. 3.3.10 Discrete Inputs The discrete input interface allows the S/W read-only access to external pins on the FPGA or internal signals generated in the FPGA. The discrete inputs are packed into two 32-bit words, bit-mapped per DIN number. The NG_NICVBPCI terminates the bus cycle with the assertion of PCI_TRDY_N. To satisfy DEOS’s address partitioning, copies of these double-words are available on 4-kbyte boundaries. This block also contains a special discrete inputs register that can be accessed at address 7312:0004H. When S/W reads from this address, the values of the fan monitor fault flags are returned, and at the end of the read cycle the flags are set to ‘1’, which indicates the fans are running. Refer to section 3.3.14 for more detailed information on the Fan Monitor function. [FRD_NGNICVBPCI_DIO_0940>HRD_NGNIC_CoreFunc_0800 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0940>HRD_NGNIC_CoreFunc_0800" ] All discrete inputs in the NG_NICVBPCI shall be readable from the PCI bus at addresses indicated in Table 25 with bit mapping as shown in Table 26 and Table 27. [FRD_NGNICVBPCI_DIO_0950>HRD_NGNIC_Func_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0950>HRD_NIC_Func_0330" ] The Discrete Inputs registers shall be initialized to the Reset Value shown in Table 26 and Table 27 when CCA_RST_N is asserted. [FRD_NGNICVBPCI_DIO_0960>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0960>DERIVED" ] PCI host writes to the Discrete Inputs registers shall be terminated by the NG_NICVBPCI FPGA by target abort, but have no affect on the state of the NG_NICVBPCI discrete inputs. Table 25 – Discrete Input Registers Memory Map Register Name CPU Address Decoded Address bits* Access Type 31:20 19:12 3:2 Lower Discrete Inputs 7310:0000H 731H xxH x0b Read Upper Discrete Inputs 7310:0004H 731H xxH x1b Read Fan Read/Set Status Register 7312:0004H 731H 20H 01b Read * The decoded address bits show how the register addresses are shadowed within the FPGA. [FRD_NGNICVBPCI_DIO_0970>HRD_NGNIC_CoreFunc_0810 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0970>HRD_NGNIC_CoreFunc_0810" ] CPU reads of the Discrete Inputs registers shall return the state of the discrete inputs on the appropriate PCI data bit as described in Table 26 and Table 27. [FRD_NGNICVBPCI_DIO_0980>HRD_NGNIC_Func_0470 XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0980>HRD_NIC_Func_0470" ] When the Fan Read/Set Status register is read, DINs 60-63 shall be set to ‘1’ at the end of the read access. Commentary: The fan status register will reset at power-up to an all fault condition (0’s). During SW initialization, SW will read the register, which will clear the faults, thus initializing it to a non-fault condition. [FRD_NGNICVBPCI_DIO_0990>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DIO_0990>DERIVED" ] The NG_NICVBPCI shall return logic ‘0’ for each unused discrete inputs when read by the PCI host. Table 26 – Lower Discrete Inputs Register Bit Definition DIN Number Internal Signal Name I/O Signal Name Reset Value** Description 0-5 N/A Not used 6 hst_id0 HOSTIDBUS0 N/A Host ID Bit 0, Host ID discrete inputs indicates the type of chassis in which the NIC is installed. MAU, DU, radio cabinet, etc. 7 hst_id1 HOSTIDBUS1 N/A Host ID Bit 1, Host ID discrete inputs indicates the type of chassis in which the NIC is installed. MAU, DU, radio cabinet, etc. 8 hst_id2 HOSTIDBUS2 N/A Host ID Bit 2, Host ID discrete inputs indicates the type of chassis in which the NIC is installed. MAU, DU, radio cabinet, etc. 9 hst_id3 HOSTIDBUS3 N/A Host ID Bit 3, Host ID discrete inputs indicates the type of chassis in which the NIC is installed. MAU, DU, radio cabinet, etc. 10 hst_id4 HOSTIDBUS4 N/A Host ID Bit 4, Host ID discrete inputs indicates the type of chassis in which the NIC is installed. MAU, DU, radio cabinet, etc. 11 Chn_a_b_N HOSTIDBUS5 N/A Channel A/B#, A ‘1’ indicates that the NIC is connected to channel A, a ‘0’ indicates that the NIC is connected to channel B. 12 hst_ch_par HOSTIDBUS6 N/A Host Channel Parity, This signal is used to maintain even parity across the Host ID and Channel A/B# discrete Inputs. 13-26 N/A Not used 27 IPD_STROBE_N IPD_STROBE_N ‘1’ Set to ‘0’ If falling edge of IPD_STROBE_N is detected. Set to ‘1’ on rising edge of IPD_STROBE_N. 28 Ipd_valid IPD_VALID 0 IPD Monitor valid 29 I2C_BUSY N/A 0 DIN 29 (busy) will be set to ‘1’ when an I2C read or write transfer is in progress. 30 auto_dma_busy AUTO_DMA_DONE_N 0 Auto DMA Busy, A ‘1’ indicates that the Auto DMA state machine is currently transferring (or preparing to transfer) a block of data. (i.e. VbPCI or PMNIC DMA is in progress) 31 I2C_DONE N/A 1 DIN31, done, will be set to ‘1’ when current read/ write transaction completed. Table 27 – Upper Discrete Inputs and Fan Read/Set Status Register Bit Definition DIN Number Internal signal Name I/O Signal Name Reset Value** Description 32 ps1din0 PSBUS 5 N/A Power supply #1 discrete input (Fan Override). Indicates that P/S internal temperature is hot enough to require airflow. 33-35 N/A 0 Not used 36 error_while_dma 0 ‘1’ indicates that Local PCI bus 0 transaction was rejected because VbPCI bus 1 or VbPCI bus 2 DMA is in progress. 37 ps1onaux PSBUS 8 N/A Power Supply on Auxiliary, A ‘1’ indicates that power supply #1 is on auxiliary power. 38 ps1noaux PSBUS 7 N/A PS1 no Aux, A ‘1’ indicates that power supply #1 has no auxiliary power. 39 ps1otemp PSBUS 6 N/A PS1 Over Temperature, A ‘0’ indicates that power supply #1 is in an over temperature condition. 40-45 N/A 0 Not used 46 Apm_pwr_fail_N APM_PWR_FAIL_N N/A A ’0’ indicates that power supply for APM module fail 47-49 N/A 0 Not used 50 Slot0_serr_n SLOT_SERR_N0 1 A ’0’ indicates that module at slot 0 generate system error signal 51 Slot1_serr_n SLOT_SERR_N1 1 A ’0’ indicates that module at slot 1 generate system error signal 52 Slot2_serr_n SLOT_SERR_N2 1 A ’0’ indicates that module at slot 2 generate system error signal 53 Slot3_serr_n SLOT_SERR_N3 1 A ’0’ indicates that module at slot 3 generate system error signal 54-55 N/A 0 Not used 56 Slot4_serr_n SLOT_SERR_N4 1 A ’0’ indicates that module at slot 4 generate system error signal 57 Slot5_serr_n SLOT_SERR_N5 1 A ’0’ indicates that module at slot 5 generate system error signal 58 Slot6_serr_n SLOT_SERR_N6 1 A ’0’ indicates that module at slot 6 generate system error signal 59 Slot7_serr_n SLOT_SERR_N7 1 A ’0’ indicates that module at slot 7 generate system error signal 60 Fan1_sensed N/A 0 A ‘1’ indicates that fan #1 tachometer detects fan is operating 61 Fan2_sensed N/A 0 A ‘1’ indicates that fan #2 tachometer detects fan is operating 62 Fan3_sensed N/A 0 A ‘1’ indicates that fan #3 tachometer detects fan is operating 63 Fan4_sensed N/A 0 A ‘1’ indicates that fan #4 tachometer detects fan is operating 3.3.11 Automatic DMA During each ASCB-D frame, data received over the ASCB-D network and stored in the NIC DPRAM must be sent over the VbPCI bus to users. Also, data to be transmitted must be moved from the users to the NIC. In order to move this large amount of data in the shortest time possible, the CPU is removed from the data-moving task. The automatic DMA state machine will, under software control, transfer a block of up to 128K bytes of data out of the DPRAM onto the VbPCI. It can also retrieve a block of up to 128K bytes of data from a user on the VbPCI and place it into the DPRAM. The data block must be double word aligned. To start a DMA transfer, software must write to the three DMA address registers shown in Table 28. The DMA start address register holds the start address of the device that data will be read from. The DMA destination address register holds the start address of the device that data will be written to. The DMA end address register holds the last address to be accessed in the DPRAM minus 2 double words. This means that the Auto DMA function can only be used to perform transfers of more than two double words. After these three registers have been written, the DMA state machine will request access to the NIC DPRAM and to VbPCI Bus 1. Once access is granted, the transfer will begin. For example, to move 20 double words from DPRAM starting at address 60000C00h to a user module starting at address 200B0000h software would write 60000C00h (the starting address) to address 7B000000h, 200B0000h (the destination address) to address 7B000004 and 60000C4Ch – 8 = 60000C44 (ending address – 2 double words) to address 7B000008h. To move data between these two addresses but in the other direction, the data written to the first two registers would be reversed, but the data written to the third register would remain the same. Software can poll Discrete Input 30 (which is provided by the NG_NICVBPCI FPGA) to determine when the DMA transfer is complete. Alternatively, a DMA done interrupt can be configured to notify SW when the DMA transfer is done. When the PM_NIC_BIC FPGA (on PM module) is ready to start a transfer it will assert AUTO_DPREQ3_N to request access to the NIC DPRAM. It will then wait until AUTO_DPGNT3_N is asserted (access to the NIC DPRAM is granted) before starting the transfer. An auto fill DMA mode is provided to allow the S/W to initialize shared memory areas within client modules or to initialize the NIC DPRAM. This mode is initiated by writing the 32 bit fill value (e.g. 00000000) into the DMA autofill value register before loading the DMA address registers (7B000000H - 7B000008H). The autofill transfer will take place, by writing the fill value to the block of memory beginning at the destination address. The number of locations filled is defined exactly as a normal DMA transfer. Fill mode to the broadcast addresses is also supported. The DMA logic remains in autofill mode until the specified transfer is completed. To perform another autofill operation, register 7B00000CH must again be loaded with the fill value prior to loading the rest of the DMA registers. Table 28 – Auto DMA Registers Register Address Decoded Address Bits* Access Data bits 31:24 3:2 DMA Source Address 7B00:0000H 7BH 00b Read/Write D(31:0)/D(31:2) DMA Destination Address 7B00:0004H 7BH 01b Read/Write D(31:0)/D(31:2) DMA End Address 7B00:0008H 7BH 10b Read/Write D(31:0)/D(16:2) DMA Autofill Value 7B00:000CH 7BH 11b Read/Write D(31:0)/D(31:0) * The decoded address bits show how the register addresses are shadowed within the FPGA. The NG_NICVBPCI FPGA will support double word, aligned CPU writes to the DMA address region defined in Table 28. [FRD_NGNICVBPCI_DMA_1010>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1010>DERIVED" ] A CPU write to the Auto DMA register addresses shall cause the appropriate DMA register to be written with the value on the CPU data bits, as shown in Table 28 if a DMA transfer is not in progress. [FRD_NGNICVBPCI_DMA_1011>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1011>DERIVED" ] When CPU writes to the DMA registers while a DMA transfer is in-progress NG_NICVBPCI FPGA shall prevent the assertion of PCI_DEVSEL_N by the PCI client for DMA register accesses. Commentary: if the CPU writes to the DMA registers during a DMA transfer the FPGA will not acknowledge the transaction with assertion DEVSEL#. The resulting PCI transaction will end in a master abort and be signaled to the software through the existing SERR# and/or Master Abort registers and interrupts. [FRD_NGNICVBPCI_DMA_1020>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1020>HRD_NGNIC_Func_0120" ] The DMA Source Address register value shall be used as the start address of the memory resource (NIC DPRAM or VbPCI Bus 1 or Internal DRAM) that will be read from during a DMA transfer. [FRD_NGNICVBPCI_DMA_1030>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1030>HRD_NGNIC_Func_0120" ] The DMA Destination Address register value shall be used as the start address of the memory resource (NIC DPRAM, Internal DPRAM, VbPCI Broadcast, or VbPCI Bus 1) that will be written to during a DMA transfer. [FRD_NGNICVBPCI_DMA_1040>HRD_ HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1040>HRD_ HRD_NGNIC_Func_0120" ] The DMA End Address register value shall be used as the last address to be accessed in the NIC DPRAM or Internal DPAM minus two double words for a DMA transfer. Commentary: When Dout52 indicates that DMA shall use internal DPRAM software is responsible for assuring that end address register is programmed with value that is not outside of 4K address space of internal memory otherwise DMA transaction will wrap around to the beginning of internal DPRAM. [FRD_NGNICVBPCI_DMA_1045>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1050>HRD_NGNIC_Func_0130" ] The number of DWORDS for DMA transfer shall be given by a difference of end address register value and start address register value or destination address register value plus two depending on which respective register contains value in NIC DPRAM or Internal DPRAM address range. [FRD_NGNICVBPCI_DMA_1050>HRD_NGNIC_Func_0130 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1050>HRD_NGNIC_Func_0130" ] The max number of bytes per DMA transfer shall be no more than 128 Kbyte. [FRD_NGNICVBPCI_DMA_1060>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1060>HRD_NGNIC_Func_0120" ] The DMA Autofill Value register data shall be used as a fill value for a DMA transfer with autofill. [FRD_NGNICVBPCI_DMA_1070>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1070>HRD_NGNIC_Func_0120" ] The Auto DMA function shall perform an autofill operation if the CPU writes to the Autofill Value register prior writing to the last of the other three Auto DMA registers. [FRD_NGNICVBPCI_DMA_1075>Derived XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1075>Derived" ] The Auto DMA function shall allow CPU writes to the DMA Source Address, DMA Destination Address, and DMA End Address registers in any order. [FRD_NGNICVBPCI_DMA_1080>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1080>HRD_NGNIC_Func_0120" ] The FPGA shall perform a DMA transfer from the NIC DPRAM to VbPCI Bus 1 (without autofill) when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has not been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the NIC DPRAM address range (6000:0000H to 6001:FFFCH). · The value in the DMA Destination Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). · DOUT52 (DPRAM_CHIP_SEL) is not asserted. [FRD_NGNICVBPCI_DMA_1085>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1085>HRD_NGNIC_Func_0120" ] The FPGA shall perform a DMA transfer from the internal DPRAM to VbPCI Bus 1 (without autofill) when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has not been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the NIC DPRAM address range (6000:0000H to 6000:0FFCH) or Internal DPRAM address range(6002:0000H to 6002:0FFCH) · The value in the DMA Destination Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). · DOUT52 (DPRAM_CHIP_SEL) is asserted. [FRD_NGNICVBPCI_DMA_1090>HRD_NGNIC_Func_0140 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1090>HRD_NGNIC_Func_0140" ] The FPGA shall perform a DMA transfer from the NIC DPRAM to VbPCI Broadcast (without autofill) when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has not been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the NIC DPRAM address range (6000:0000H to 6001:FFFCH). · The value in the DMA Destination Address register is within the VbPCI Broadcast address range (4000:0000H to 4FFF:FFFCH). · AUTO_DPREQ3_N and IM_HERE_N are asserted or IM_HERE is not asserted. · DOUT52 (DPRAM_CHIP_SEL) is not asserted. [FRD_NGNICVBPCI_DMA_1095>HRD_NGNIC_Func_0140 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1095>HRD_NGNIC_Func_0140" ] The FPGA shall perform a DMA transfer from the internal DPRAM to VbPCI Broadcast (without autofill) when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has not been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the NIC DPRAM address range (6000:0000H to 6000:0FFCH) or Internal DPRAM address range(6002:0000H to 6002:0FFCH) · The value in the DMA Destination Address register is within the VbPCI Broadcast address range (4000:0000H to 4FFF:FFFCH). · AUTO_DPREQ3_N and IM_HERE_N are asserted or IM_HERE is not asserted. · DOUT52 (DPRAM_CHIP_SEL) is asserted. [FRD_NGNICVBPCI_DMA_1100>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1100>HRD_NGNIC_Func_0120" ] The FPGA shall perform a DMA transfer from VbPCI Bus 1 to the NIC DPRAM (without autofill) when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has not been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). · The value in the DMA Destination Address register is within the NIC DPRAM address range (6000:0000H to 6001:FFFCH). · DOUT52 (DPRAM_CHIP_SEL) is not asserted. [FRD_NGNICVBPCI_DMA_1105>HRD_NGNIC_Func_0120 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1105>HRD_NGNIC_Func_0120" ] The FPGA shall perform a DMA transfer from VbPCI Bus 1 to the Internal DPRAM (without autofill) when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has not been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). · The value in the DMA Destination Address register is within the NIC DPRAM address range (6000:0000H to 6000:0FFCH) or Internal DPRAM address range(6002:0000H to 6002:0FFCH) · DOUT52 (DPRAM_CHIP_SEL) is asserted. [FRD_NGNICVBPCI_DMA_1110>HRD_NGNIC_Func_0160 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1110>HRD_NGNIC_Func_0160" ] [FRD_NGNICVBPCI_DMA_1110>HRD_NGNIC_Func_0174 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1110>HRD_NGNIC_Func_0160" ] The FPGA shall perform an autofill DMA transfer to the NIC DPRAM when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). · The value in the DMA Destination Address register is within the NIC DPRAM address range (6000:0000H to 601F:FFFCH). · DOUT52 (DPRAM_CHIP_SEL) is not asserted. [FRD_NGNICVBPCI_DMA_1115>HRD_NGNIC_Func_0160 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1115>HRD_NGNIC_Func_0160" ] [FRD_NGNICVBPCI_DMA_1115> HRD_NGNIC_Func_0609 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1115>HRD_NGNIC_Func_0160" ] The FPGA shall perform an autofill DMA transfer to the Internal DPRAM when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). · The value in the DMA Destination Address register is within the NIC DPRAM address range (6000:0000H to 6000:0FFCH) or Internal DPRAM address range(6002:0000H to 6002:0FFCH) · DOUT52 (DPRAM_CHIP_SEL) is asserted. [FRD_NGNICVBPCI_DMA_1120>HRD_NGNIC_Func_0160 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1120>HRD_NGNIC_Func_0160" ] [FRD_NGNICVBPCI_DMA_1120>HRD_NGNIC_Func_0150 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1120>HRD_NGNIC_Func_0160" ] The FPGA shall perform an autofill DMA transfer to VbPCI Bus 1 when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the NIC DPRAM address range (6000:0000H to 601F:FFFCH). · The value in the DMA Destination Address register is within the VbPCI Bus 1 address range (2000:0000H to 2FFF:FFFCH). [FRD_NGNICVBPCI_DMA_1130>HRD_NGNIC_Func_0160 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1130>HRD_NGNIC_Func_0160" ] The FPGA shall perform an autofill DMA transfer to VbPCI Broadcast when the following conditions are met: · The DMA Autofill Value register shown in Table 28 has been written since the last DMA transfer. · The DMA Source Address, DMA Destination Address, and DMA End Address registers shown in Table 28 have been written since the last DMA transfer. · The value in the DMA Source Address register is within the NIC DPRAM address range (6000:0000H to 601F:FFFCH). · The value in the DMA Destination Address register is within the VbPCI Broadcast address range (4000:0000H to 4FFF:FFFCH). · AUTO_DPREQ3_N and IM_HERE_N are asserted or IM_HERE is not asserted. [FRD_NGNICVBPCI_DMA_1140>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1140>DERIVED" ] The AUTO_DMA_DONE_N output shall be de-asserted while the NG_NICVBPCI FPGA performs a DMA transfer (normal or autofill) or while the AUTO_BUSY3_N input asserted low. [FRD_NGNICVBPCI_DMA_1180>HRD_NGNIC_Func_0090 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1180>HRD_NGNIC_Func_0090" ] During a DMA transfer in which VbPCI Bus 1 is the source, VB_PERR_N shall be asserted if VB_PAR does not provide even parity across VB_AD(31:0) and VB_C_BE_N(3:0) during the data phase of a read on VbPCI Bus 1. Commentary: Correct even parity occurs when the number of 1’s on VB_AD(31:0), VB_C_BE_N(3:0), and VB_PAR is an even number. Table 29 below shows what the other PCI data bus bits are driven to on reads to the DMA address registers. The count value for the DMA start address and the DMA destination address registers increments after each read/write during the DMA transfer. [FRD_NGNICVBPCI_DMA_1190>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1190>DERIVED" ] A CPU read of an Auto DMA register shall cause the appropriate Auto DMA register data to be driven on the CPU data bits as shown in Table 29. [FRD_NGNICVBPCI_DMA_1191>HRD_NGNIC_Func_0330 XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1191>HRD_NGNIC_Func_0330" ] The Auto DMA registers shall be initialized to the reset values shown in Table 29 when CCA_RST_N is asserted. [FRD_NGNICVBPCI_DMA_1192>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1192>DERIVED" ] If the CPU accesses the VbPCI buses while AUTO_DMA_DONE_N is not asserted, NG_NICVBPCI FPGA shall reject the transaction by performing a target abort and set DIN 36 (error_while_dma) to ‘1’. Commentary: if the CPU tries to access VbPCI bus 1 or bus 2 while a DMA transfer is active on these buses, the FPGA will claim the transaction by asserting DEVSEL#. After detecting that the AUTO_DMA_DONE_N signal is not asserted, the FPGA will issue a target abort. [FRD_NGNICVBPCI_DMA_1193>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1193>DERIVED" ] DIN 36 (error_while_dma) shall be set to ‘0’ at the start of each DMA transfer on VbPCI bus 1 or VbPCI bus 2. [FRD_NGNICVBPCI_DMA_1200>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1200>DERIVED" ] The Read Count Value in the DMA Source Address register shall increment by one each time the source (DPRAM or VbPCI bus) is read during the DMA transfer until last location is accessed. [FRD_NGNICVBPCI_DMA_1210>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1210>DERIVED" ] The Write Count Value in the DMA Destination Address register shall increment by one each time the destination (DPRAM or VbPCI bus) is written during the DMA transfer until last location is accessed. Table 29 – Auto DMA Register Bit Definition Register Data Bits Reset Value D31-D17 D16-D2 D1-D0 DMA Source Address Source Address Read Count Value “00” 0000_0000H DMA Destination Address Destination Address Write Count Value “00” 0000_0000H DMA End Address 6000H End Address “00” 6000_0000H DMA Autofill Value Autofill (31:0) 0000_0000H [FRD_NGNICVBPCI_DMA_1220>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1220>DERIVED" ] The AUTO_DMA_DONE_N signal shall be asserted when all the bytes specified in the DMA End Address register have been transferred which indicated that DMA transfer is done. [FRD_NGNICVBPCI_DMA_1221>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1221>DERIVED" ] NG_NICVBPCI FPGA shall stop DMA transaction and return DMA to Idle state if VB_SERR_N, VB_PERR_N or VB_STOP_N signal is asserted during transfer. Commentary: The assertion of VB_SERR#, VB_PERR# or VB_STOP# will cause a latch of the last address of the transaction and generate the Interrupt to CPU. [FRD_NGNICVBPCI_DMA_1222>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DMA_1222>DERIVED" ] NG_NICVBPCI FPGA shall stop a DMA transfer from the NIC DPRAM to VbPCI bus 1 and return DMA to Idle state when either one of the following conditions are met: · If VB_DEVSEL_N has not been asserted five CLK_25 clock cycles after the NICVBPCI FPGA asserts VB_FRAME_N during a DMA transfer to VbPCI bus 1, · If VB_TRDY_N has not been asserted sixteen CLK_25 clocks cycles after the NICVBPCI FPGA asserts VB_FRAME_N during a DMA transfer to VbPCI bus 1. 3.3.12 NIC Dual-Port RAM Interface A dual-port RAM configuration is used as a bridge between the on-card resources and the VbPCI backplane. The NG_NICVBPCI FPGA controls access to the DPRAM. The DPRAM holds data that is to be transferred to and from the VbPCI busses. The dual-port RAM, IDT70V3579S, is arranged as 32Kbytes x 36-bits wide to allow for double-word FPGA accesses. The IDT70V3579S has an internal address counter, which facilitates PCI Bus burst access. The NG_NICVBPCI FPGA performs PCI Bus address decoding and generates a Dual Port RAM Address Strobe, NIC_ADS_N, and every Local PCI Bus Address Phase. The NG_NICVBPCI FPGA supports bursting to the IDT70V3579S, by asserting Dual Port RAM Count Enable, NIC_CNTEN_N. During Read Phase of PCI Bus access to the Dual Port RAM, the NG_NICVBPCI generates Dual Port RAM Output Enable, NIC_OE_N and drives High the signal Dual Port RAM Read Write Low, NIC_RD_WR_N. Port 1 (Left port) is accessed through NG_NICVBPCI FPGA and is shared between the Auto DMA function, the Auto DMA function in the PM-NIC VbPCI Master FPGA (applies to dual NIC modules only), and the NIC CPU. The NIC CPU accesses Port 1 (Left port) at 6000:0000H – 6001:FFFFH. Port 2 (Right port) of the DPRAM is handled by the NIC Core FPGA and is dedicated to data exchange between the DPRAM and the ASCB Bus, TX Control, TX FIFO, and TX Time Stamp. Port 2 is accessed by the NIC CPU via 6200:0000H – 62FF:FFFFH. [FRD_NGNICVBPCI_DPR_1230>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1230>DERIVED" ] The NG_NICVBPCI FPGA shall generate all NIC DPRAM control signals necessary for the Left port (Port 1) of the dual-port RAM, IDT part number IDT70V3579S or equivalent. Commentary: NG_NICVBPCI FPGA will generate control signals to NIC DPRAM (future provision DPRAM Bank 0) : NIC_RW _N, NIC_OE_N, NIC_ADS_N, NOC_CE0_N, NIC_CE1_B0_N, NIC_CNTEN_N, NIC_BE_N(3:0), NIC_A(16:2), NIC_D(31:0) signals. The chip select control signals will be synchronized to the CLK_25 clock signal. [FRD_NGNICVBPCI_DPR_1240>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1240>DERIVED" ] The NG_NICVBPCI FPGA shall read the left port of the NIC DPRAM only if the requested PCI read access is to the valid DPRAM address range 6000:0000-6001:FFFFH. [FRD_NGNICVBPCI_DPR_1250>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1250>DERIVED" ] The NG_NICVBPCI FPGA shall write the left port of the NIC DPRAM only if the requested PCI write access is to the valid DPRAM address range 6000:0000-6001:FFFFH. [FRD_NGNICVBPCI_DPR_1260>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1260>DERIVED" ] The NG_NICVBPCI FPGA shall support PCI burst reads and writes to the DPRAM address range 6000:0000-6001:FFFFH. [FRD_NGNICVBPCI_DPR_1270>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1270>DERIVED" ] Write accesses to DPRAM memory shall be byte lane selectable [FRD_NGNICVBPCI_DPR_1280>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1280>DERIVED" ] The NIC DPRAM interface signals shall be driven by NG_NICVBPCI FPGA and not driven by the DPRAM memory devices when the bus is idle and IM_HERE_N signal is de-asserted. [FRD_NGNICVBPCI_DPR_1281>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1281>DERIVED" ] The NIC DPRAM interface signals with exception of NIC_CE0_N and NIC_CE1_B0 shall be tri-stated by NG_NICVBPCI FPGA when AUTO_DPGNT3_N and IM_HERE_N signals are asserted and AUTO_BUSY3_N is asserted. [FRD_NGNICVBPCI_DPR_1282>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1282>DERIVED" ] The NIC_CE0_N signal shall be driven inactive by NG_NICVBPCI FPGA when the bus is idle and IM_HERE_N signal is asserted. [FRD_NGNICVBPCI_DPR_1283>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1283>DERIVED" ] The NIC_CE0_N signal shall be driven active by NG_NICVBPCI FPGA when any of the following is true: 1. AUTO_DPGNT3_N, IM_HERE_N and DOUT52 (DPRAM_CHIP_SEL) signals are asserted and AUTO_DMA_DONE_N is de-asserted 2. DMA operation on Vbpci Bus 1 is programmed and DOUT52 (DPRAM_CHIP_SEL) is asserted [FRD_NGNICVBPCI_DPR_1284>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1284>DERIVED" ] The NIC_CE0_N signal shall be driven active by NG_NICVBPCI FPGA when a requested PCI Bus 0 read/write access is to the valid DPRAM address range 6000:0000-6001:FFFFH. Commentary: When the DPRAM data bus is idle and PM NIC card is not installed, the NG_NICVBPCI FPGA should drive all data bus bits to ‘0’ and all control signals to inactive state. When PM NIC card is installed it will drive DPRAM data bus and all but NIC_CE0_N control signals inactive. In case that PM NIC is installed and there is a DMA operation on VbPCI bus2 programmed (not a broadcast) then NG_NICVBPCI FPGA must assert NIC_CE0_N signal to allow for PM NIC access to NIC DPRAM. Commentary: For all related BROADCAST requirements see DMA transfer, section 3.3.11. 3.3.12.1 DPRAM Arbitration The NICVBPCI FPGA serves as the arbiter for the various resources that can access port 1 of the NIC DPRAM. These resources include the CPU, the Auto DMA functions onto VbPCI Bus 1, and Auto DMA functions onto VbPCI Bus 2 in the PM-NIC VbPCI Master FPGA (for dual NIC modules). [FRD_NGNICVBPCI_DPR_1290>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1290>DERIVED" ] The NIC DPRAM arbitration priority shall be as shown in Table 30. Table 30 – NIC DPRAM Arbitration Priority Priority Function Comment 1 Auto DMA NIC- VbPCI Bus 1 1 Auto DMA PM- VbPCI Bus 2 2 CPU Local PCI Bus 0 Note that there is no arbitration between the two Auto DMA functions because they are never intended to be activated SW at the same time. Therefore, S/W must not attempt to perform Auto DMA transfers on VbPCI Bus 1 and VbPCI Bus 2 at the same time, unless it’s done using the VbPCI Broadcast address range. [FRD_NGNICVBPCI_DPR_1300>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1300>DERIVED" ] When any two functions are requesting DPRAM simultaneously bus shall be granted to the requestor with higher priority per table 30. [FRD_NGNICVBPCI_DPR_1310>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1310>DERIVED" ] The NG_NICVBPCI FPGA shall de-assert AUTO_DPGNT3_N when AUTO_BUSY3_N is asserted. [FRD_NGNICVBPCI_DPR_1320>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1320>DERIVED" ] When any of the following occurs: 1. CPU DPRAM access is in progress 2. Auto DMA transfer to VbPCI Bus 1 is active the NG_NICVBPCI FPGA shall assert AUTO_EXCUSE_ME_N. Commentary: Assertion of AUTO_EXCUSE_ME_N causes PM NIC to release (tristate) its NIC DPRAM control signals and allows the NG_NICVBPCI FPGA to access the DPRAM. If the PM NIC card is not installed (IM_HERE_N de-asserted), then AUTO_EXCUSE_ME_N has no meaning. [FRD_NGNICVBPCI_DPR_1330>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1320>DERIVED" ] The NG_NICVBPCI FPGA shall de-assert AUTO_EXCUSE_ME_N when DPRAM bus is granted during broadcast transactions, VbPCI bus2 only DMA operations or when DMA transaction is completed. Commentary: DMA transaction is completed when no DMA transaction is active (either on bus 1 or 2 or both) as indicated by AUTO_DMA_BUSY DIN. 3.3.12.2 External DPRAM memory Interface timing [FRD_NGNICVBPCI_DPR_1340>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1340>DERIVED" ] The NIC DPRAM Memory interface outputs generated by the NG_NICVBPCI FPGA shall have a maximum clock to output pin delay (To) of 32 ns relative to the rising edge of the CLK_25 input pin. Commentary: Refer to Figure 4 for a timing waveform. [FRD_NGNICVBPCI_DPR_1350>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1350>DERIVED" ] The NIC DPRAM interface outputs generated by the NG_NICVBPCI FPGA shall have a minimum clock to output pin delay (To) of 0 ns relative to the rising edge of the CLK_25 input pin. Commentary: Refer to Figure 4 for a timing waveform. [FRD_NGNICVBPCI_DPR_1360>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1360>DERIVED" ] The NG_NICVBPCI FPGA’s NIC DPRAM interface input pins shall have a minimum setup time (Tsu) of 0.8 ns relative to the rising edge of the CLK_25 input pin. Commentary: Refer to Figure 4 for a timing waveform. Tsu is defined in a manner used in component data sheets. [FRD_NGNICVBPCI_DPR_1370>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1370>DERIVED" ] The NG_NICVBPCI FPGA’s NIC DPRAM interface input pins shall have a minimum hold time (Th) of 0 ns relative to the rising edge of the CLK_25 input pin. Commentary: Refer to Figure 4 for a timing waveform. Th is defined in a manner used in component data sheets. Figure 4 – DPRAM Signal timing [FRD_NGNICVBPCI_DPR_1380>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1380>DERIVED" ] The NIC DPRAM interface timing to perform a read operation shall have the signal relationship shown in Figure 5. Figure 5 – DPRAM Memory Read Cycle [FRD_NGNICVBPCI_DPR_1390>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1390>DERIVED" ] The NIC DPRAM interface timing to perform a write operation shall have the signal relationship shown in Figure 6. Figure 6 – DPRAM Memory Write Cycle 3.3.12.3 Internal DPRAM Interface The NG_NICVBPCI FPGA contains an internal DPRAM that is organized as 1024 by 32 bits wide. The CCA has provisions to add an external LAN DPRAM chip (DPRAM Bank 1), IDT70V3579S that will expand the LAN DPRAM address range to 128 kbytes. When the requested address on either port matches the address range of the internal memory (memory range 6002:0000H to 6002:0FFFH or 6202:0000H to 6202:0FFFH) the access will be directed to the internal DPRAM. This solution is intended to simplify clock zone (50MHz to 25MHz) crossing and improve LAN performance by providing a fast DPRAM memory for LAN data. DOUT 52 is provided for DPRAM bank switching mechanism. [FRD_NGNICVBPCI_DPR_1400>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1400>DERIVED" ] The NG_NICVBPCI FPGA shall provide minimum 4 Kbyte Internal DPRAM organized as 1024x32 wide. [FRD_NGNICVBPCI_DPR_1410>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1410>DERIVED" ] The NG_NICVBPCI FPGA shall read/ write the Internal DPRAM Left Port only if the requested PCI bus 0 read/write access is to the valid DPRAM address range 6002:0000 -6002:0FFFH. [FRD_NGNICVBPCI_DPR_1420>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1420>DERIVED" ] The NG_NICVBPCI FPGA shall read/ write the Internal DPRAM Right Port only if the requested PCI Bus 0 read/write access is to the valid DPRAM address range 6202:0000 -6202:0FFFH. [FRD_NGNICVBPCI_DPR_1430>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1430>DERIVED" ] The NG_NICVBPCI FPGA shall support PCI Bus 0 burst reads and writes to the Internal DPRAM address range 6002:0000 - 6002:0FFFH. [FRD_NGNICVBPCI_DPR_1435>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1435>DERIVED" ] The NG_NICVBPCI FPGA shall support PCI Bus 0 burst reads and writes to the Internal DPRAM address range 6202:0000 - 6202:0FFFH. [FRD_NGNICVBPCI_DPR_1440>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1440>DERIVED" ] Write accesses to Internal DPRAM memory shall be byte lane selectable. Commentary: Only DWORD bursts are supported. [FRD_NGNICVBPCI_DPR_1450>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1450>DERIVED" ] When CPU access Internal DPRAM address range, control signals OE_N and CE_N for External the Dual Port Memory shall be de-asserted. Commentary: All other control signals will operate normally. [FRD_NGNICVBPCI_DPR_1451>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1451>DERIVED" ] When AUTO_DPGNT3_N and IM_HERE_N signals are asserted and DOUT52 is set to 1, NG_NICVBPCI FPGA shall translate PM NIC DPRAM access into internal DPRAM access by driving NIC_CE0_N signal inactive and generating necessary control signals sequence for internal DPRAM. [FRD_NGNICVBPCI_DPR_1460>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_DPR_1460>DERIVED" ] The Internal DPRAM interface shall obey the same arbitration rules as the External DPRAM. 3.3.13 Real-Time Clock / Temperature Monitor Interface A real time clock (RTC) provides a central resource for user modules requiring a sense of real time. The RTC maintains seconds, minutes, hours, day, date, month, and year information (up to 2099). The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM-bar/PM indicator. Two programmable time-of-day alarms and a programmable square-wave output are provided. Address and data are transferred serially through an I2C bidirectional bus. The clock also contains 236 bytes of battery-backed SRAM for use by software A small lithium battery will power the clock in the absence of power for approximately 10 years. The MAU temperature is monitored by the NIC through the use of a temperature-to-digital converter chip. The Digital Temperature sensor measures temperature with accuracy ±3 deg C. The monitor continuously measures the temperature and stores it in an internal register once every 64 second. Software can read this register at any time to retrieve the last measured temperature. New values are loaded only when a change in the temperature value occurs. The min temperature conversion time is 125 msec, and max time is 200 msec. The NG_NICVBPCI FPGA interfaces to the real-Time Clock and Temperature Monitor using I2C serial bus. For more information on the real-Time Clock and Temperature Monitor, refer to Dallas Semiconductor Maxim’s MAX DS3232 datasheet. The I2C serial interface is comprised of two wires: a serial clock, RTC_SCL, and a bi‑directional serial data line, RTC_SDA. RTC_SCL is sourced by the NG_NICVBPCI FPGA. The I2C controller, which resides inside the NG_NICVBPCI FPGA, generates RTC_SCL by dividing the CLK_25 (24.9975 MHz) down to 333.3 kHz (400kHz derated by ~1.2x). The I2C controller has a number of memory mapped registers. PCI Bus accesses are posted to the I2C controller and converted into I2C access. A read/write of an I2C register requires 2 PCI Bus accesses. A PCI Bus access of an I2C address does not return the data of the addressed register, but initiates an access to that addressed register. Once the PCI bus has initiated an I2C operation, the PCI bus must poll the DIN29/I2C_BUSY bit to determine if the operation has completed and the I2C Read Return Data Register is ready. If no I2C acknowledge occurs during the I2C transaction, the busy discrete will be removed. If a PCI access is attempted while the I2C bus interface is busy (DIN29/I2C_BUSY is asserted), it will terminate with no action taken. The RTC interface consists of four I2C registers as defined in Figure 9. Up to four I2C transactions (one per register) may be requested at a time. If an I2C transaction is not active (DIN29 / I2C_BUSY not asserted), a PCI Bus write access to an I2C register will initiate an I2C transaction on the I2C bus. If the I2C bus is busy, a PCI Bus write access will queue up a new I2C transaction in the I2C register if the register does not already contain a pending transaction (I2C Register bit 29, I2C_BUSY asserted). If the I2C register contains a pending or active transaction, the PCI Bus write will result in a target abort on PCI Bus 0. An I2C register may be read at any time. If the register contains an active transaction (bit 29, I2C_BUSY asserted), the status of the current transaction will be returned. If the register contains a completed transaction, the results of the last transaction will be returned Table 31 – RTC memory map Register Name PCI Address Decoded Address Bits* Access Type PCI Data Width (R/W) 31:20 15:12 Temperature Monitor 7900:0000H 790H 0H Read/Write D(31:0)/D(24,15:0) RTC address 7900:1000H 790H 1H Read/Write D(31:0)/D(24,15:0) RTC control/status reg. 7900:2000H 790H 2H Read/Write D(31:0)/D(24,15:0) RTC SRAM start address 7900:3000H 790H 3H Read/Write D(31:0)/D(24,15:0) * The decoded address bits show how the register addresses are shadowed within the FPGA. [FRD_NGNICVBPCI_I2C_1470>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1470>DERIVED" ] The NG_NICVBPCI FPGA shall support an I2C Serial Bus Interface as defined in DS3232 I2C RTC with SRAM Datasheet protocol, inclusive of the signals RTC_SDA and RTC_SCL. [FRD_NGNICVBPCI_I2C_1480>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1480>DERIVED" ] The NG_NICVBPCI FPGA shall operate as a master only on I2C Bus. Commentary: I2C bus interface does not support multiple masters. [FRD_NGNICVBPCI_I2C_1490>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1490>DERIVED" ] The NG_NICVBPCI FPGA shall support non-burst Memory Read and Memory Write accesses to the Real-Time Clock address region defined in Table 31. [FRD_NGNICVBPCI_I2C_1500>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1500>DERIVED" ] The NG_NICVBPCI FPGA shall only support one byte read/write accesses over the I2C interface as defined in Figure 7 and Figure 8. [FRD_NGNICVBPCI_I2C_1510>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1510>DERIVED" ] When a 32-bit write to a RTC/Temp Monitor register is performed and I2C_BUSY (DIN29) is de‑asserted, the NICVBPCI FPGA shall initiate the requested transaction over the I2C interface (RTC_SDA and RTC_SCL) per the format described in the DS3232 I2C RTC with SRAM Datasheet. Commentary: The I2C transaction is a write as defined in Figure 7, or a read as defined in Figure 8. [FRD_NGNICVBPCI_I2C_1511>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1511>DERIVED" ] If I2C_BUSY (DIN29) is asserted and a 32-bit write to a RTC/Temp Monitor register is performed, the NICVBPCI FPGA shall update the register per the format shown in Figure 9 and set bit 28 (Busy) to ‘1’. Commentary: Busy indicates that a transaction is active or pending in the I2C queue. [FRD_NGNICVBPCI_I2C_1512>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1512>DERIVED" ] If the Busy bit (bit 28) of an RTC/Temp Monitor register is set and a 32-bit write to the register is performed, the NICVBPCI FPGA shall discard the data and return target abort on PCI Bus 0. Commentary: The current transaction and the contents of the register will not be affected by the requested write access. Slave address R/ W Address/ Register Data transferred S 1 1 0 1 0 0 0 0 A X X X X X X X X A X X X X X X X X A P S – start; A – acknowledge; P –stop; R/W_N - read/write or direction bit; Slave address + W_N bit = D0H. Figure 7 – I2C Write Data Format Commentary: This is the Slave receiver mode (DS3232 write mode): Serial data and clock are received by the DS3232. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS3232 address, which is 1101000X, where X = 0/1 for R/W_N direction bit. After receiving and decoding the slave address byte, the DS3232 outputs an acknowledge on SDA. After the DS3232 acknowledges the slave address + write bit, the master transmits a word address to the DS3232. This sets the register pointer on the DS3232, with the DS3232 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS3232 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write [FRD_NGNICVBPCI_I2C_1520>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1520>DERIVED" ] When a CPU read from a RTC/ Temp. Monitor registers is performed, the NICVBPCI FPGA shall return the contents of the register as defined in Figure 9. Slave address R/ W Address/ Register Slave address R/ W Data transferred S 1101000 0 A XXXXXXXX A S 1101000 1 A XXXXXXXX N P S – start; A – acknowledge; N – not acknowledge P –stop; R/W_N - read/write or direction bit; Slave address + R bit = D1H. Figure 8 – I2C Read Data Format Commentary: This is the Slave transmitter mode (DS3232 read mode). Serial data is transmitted on SDA by the DS3232. The slave address byte contains the 7-bit DS3232 address, which is 1101000X, where X = 0/1 for R/W# direction bit. After receiving and decoding the slave address byte, the DS3232 outputs an acknowledge on SDA. The DS3232 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS3232 must receive a not acknowledge to end a read. [FRD_NGNICVBPCI_I2C_1530>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1530>DERIVED" ] The I2C Data shall transfer with the most significant bit (MSB) first. [FRD_NGNICVBPCI_I2C_1540>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1540>DERIVED" ] The NG_NICVBPCI FPGA shall generate the RTC_SCL clock signal at a frequency of 333.3  ± 1.67 kHz. Commentary: DS3232 fast mode frequency 400 kHz derated by ~1.2x. [FRD_NGNICVBPCI_I2C_1550>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1550>DERIVED" ] The RTC_SDA serial data signal shall be open drain input/output. [FRD_NGNICVBPCI_I2C_1551>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1551>DERIVED" ] The RTC_SCL serial clock signal shall be an open drain output. [FRD_NGNICVBPCI_I2C_1560>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1560>DERIVED" ] The NG_NICVBPCI FPGA shall initiate data transfer only when I2C bus is not busy. Commentary: Bus is not busy when there are no read/write transactions in progress. [FRD_NGNICVBPCI_I2C_1570>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1570>DERIVED" ] When CCA_RST_N is asserted, the NG_NICVBPCI FPGA shall drive I2C interface in a known state as defined in MAX DS3232 datasheet, pulling signals RTC_SDA and RTC_SCL low. Commentary: If the FPGA holds RTC_SCL low for more than 35 ms, DS3232 resets the internal I2C interface. [FRD_NGNICVBPCI_I2C_1571>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1571>DERIVED" ] When CCA_RST_N is de-asserted, the RTC_SDA and RTC_SCL signals shall remain low until the first write to any of the four I2C Bus registers in Table 32. Commentary: This will reset the I2C interface if SW does not access the RTC registers for at least 35ms following a CCA reset. [FRD_NGNICVBPCI_I2C_1572>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1572>DERIVED" ] The first valid write to any of the four I2C bus registers in Table 32 following CCA_RST_N de-assertion shall cause the RTC_SDA signal to be tri-stated (high*) for one 333Khz clock period, followed by the I2C_SCL signal being tri-stated (high*) for one 333Khz clock period, followed by the I2C data stream for the requested transaction. Commentary: Ensures graceful exit of the reset state without implying a STOP to the RTC. [FRD_NGNICVBPCI_I2C_1573>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1573>DERIVED" ] The RTC_SDA and RTC_SCL signals shall be tri-stated (high*) after the I2C transaction completes. Commentary: Normal parked state of an I2C bus. *Since these lines are open-drain, the master can only drive LOW or OPEN. [FRD_NGNICVBPCI_I2C_1580>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1580>DERIVED" ] The NG_NICVBPCI FPGA shall service SW access to the addresses listed in Table 32 in the order they occur. Commentary: HW provides arbitration in circular queue manner. [FRD_NGNICVBPCI_I2C_1590>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1590>DERIVED" ] If the Data fault bit set to ‘1’, the NG_NICVBPCI FPGA shall place the I2C interface into a known state by toggling the RTC_SCL clock signal up to 20 clock cycles or until RTC_SDA is asserted high. Commentary: The fault recovery requires synchronization between FPGA and DS3232. Refer to DS3232 specification. [FRD_NGNICVBPCI_I2C_1600>HRD_NGNIC_Func_0730 XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1600>HRD_NGNIC_Func_0730" ] The NG_NICVBPCI FPGA I2C Bus Interface registers shall be addressable as shown in Table 32. Table 32 – I2C Bus Register Description and Address Map Register Name / Description PCI Bus Address I2C Bus Address Range* Data Register Size Temperature Monitor 7900:0000H 11H – 12H 1 Byte RTC address 7900:1000H 00H – 0DH 1 Byte RTC control/status reg. 7900:2000H 0EH, 0FH 1 Byte RTC SRAM address 7900:3000H 14H – 0FFH 1 Byte * The I2C address is what is forwarded as the I2C Bus command byte (which is the device register being read from or written to.) [FRD_NGNICVBPCI_I2C_1610>HRD_NGNIC_Func_0730 XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1610>HRD_NGNIC_Func_0730" ] The NG_NICVBPCI FPGA shall decode each of four individual PCI Bus address read/write access to address from Table 32 into four registers with the format shown in Figure 9. 31 30 29 28 27 26 25 24 23 16 15 8 7 0 Field Status bits N/A Address/Register Data Reset 1 0 0 0 0 0 0 0 00000000 00000000 000000000 Read/Write R R R R R R R W N/A Read/Write Read/Write Figure 9 – I2C Register Format Commentary: Status bits definition: 24 bit – Read/ write bit; 25 bit – Illegal command, when address/register range not compliant with CPU address range; 26 bit – No slave present, when RTC device not in place; 27 bit – Data fault; 28 bit – Busy bit, when transaction in progress; 29, 30 - reserved 31 bit - Done [FRD_NGNICVBPCI_I2C_1620>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1620>DERIVED" ] The status bit 24 shall be written by SW and when set to a 1, indicates that SW wants to perform a read transaction and when set to ‘0’ indicates that SW wants to perform a write transaction on the I2C bus. [FRD_NGNICVBPCI_I2C_1630>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1630>DERIVED" ] The NG_NICVBPCI FPGA shall set bit 25 (illegal command) to ‘1’ when the CPU attempts to access an illegal I2C Bus address range in the I2C internal memory map, and set the bit to ‘0’ when a valid address is decoded. Commentary: See Table 32 for CPU address map to Internal RTC/ Temp. Monitor memory mapping. An attempt to access an illegal I2C Bus address will result in a target abort on PCI Bus 0. [FRD_NGNICVBPCI_I2C_1640>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1640>DERIVED" ] The NG_NICVBPCI FPGA shall set bit 26 (no slave present) to ‘1’ if the Acknowledge bit for a slave address is not asserted by the RTC, and set the bit to ‘0’ if the Acknowledge bits are asserted for all slave addresses during an I2C transaction. Commentary: The no slave present bit is not “sticky”. The fault bit is cleared if a subsequent I2C transaction from the same request register (79000:0000 – 7900:3000) to the RTC completes successfully. [FRD_NGNICVBPCI_I2C_1650>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1650>DERIVED" ] The NG_NICVBPCI FPGA shall set bit 27 (data fault) to ‘1’ if the Acknowledge bit for any data byte is not asserted by the RTC, and set the bit to ‘0’ if the RTC Acknowledges all data bytes written by the NG_NICVBPCI FPGA during an I2C transaction. Commentary: The data fault bit is not “sticky”. The fault bit is cleared if a subsequent I2C transaction from the same request register (79000:0000 – 7900:3000) to the RTC completes successfully. [FRD_NGNICVBPCI_I2C_1660>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1660>DERIVED" ] The NG_NICVBPCI FPGA shall set bit 28 (busy) to ‘1’ when an I2C read or write transfer is in progress or pending in the transaction queue, and clear it to ‘0’ when no transaction is requested. [FRD_NGNICVBPCI_I2C_1665>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1665>DERIVED" ] The NG_NICVBPCI FPGA shall set I2C_BUSY (DIN29) to ‘1’ if bit 28 is set in any of the I2C registers, and set it to ‘0’ if bit 28 in all of the I2C registers is not set. [FRD_NGNICVBPCI_I2C_1670>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1670>DERIVED" ] The NG_NICVBPCI FPGA shall set bit 31 (done) to ‘1’ when the current read/ write transaction has been completed and set it to ‘0’ while the current transaction is in progress. [FRD_NGNICVBPCI_I2C_1675>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1675>DERIVED" ] The NG_NICVBPCI FPGA shall set I2C_DONE (DIN31) to ‘1’ if bit 31 is set in all of the I2C registers, and set it to ‘0’ if bit 31 in any of the I2C registers is not set. [FRD_NGNICVBPCI_I2C_1671>DERIVED XE \f "TRACETAG" "FRD_NGNICVBPCI_I2C_1671>DERIVED" ] The I2C Registers shall be initialized to the reset value shown in Figure 9 when CCA_RST_N is asserted. 3.3.14 Fan Monitor The NIC contains logic to monitor up to four cooling fans. The fans are brushless DC motors. Each fan’s operation is independently monitored by digital logic that compares a pulse width proportional to the rotational speed of the fan with a fixed value. If the pulse width is greater than 40ms, the monitor circuit will latch and hold a fault flag indicating that fan speed is less than 80% of its nominal operating speed. The cooling fan monitor operates continuously and requires a S/W algorithm to determine when the fault flags indicate valid faults. The fault flags are special discrete inputs that can be accessed at address 7310:0000H (bits 63 down to 60). When S/W reads from this address, the values of the fault flags are returned, and at the end of the read cycle, the flags are set to ‘1’. When the flags are read, a ‘0’ indicates that the monitor has tripped and that fan speed was less than 80% of nominal. A ‘1’ indicates that the fan is operating within 80% of nominal speed or the monitor logic is measuring pulse period. To allow the monitor logic to log a fault, the minimum delay that S/W should use between reads should be 2 x (40ms + 25%margin) = 100ms. Since a failed fan should be turned off to prevent overheating of control logic, the maximum delay between fault flag monitoring and fan disable should be less than 10 seconds. The Fan Read/Set Status Register located at address 7312:0004H can be read by S/W. Data contents of this register are identical with the FAN_SENSED(1:4) discretes values that can be read at address 7310:0004H. However, a read from 7310:0004H does not set the flags to ‘1’ after the read operation and does not reset the pulse period counters Upon power up or NIC system reset, the fan monitor logic will set all fault flags to ‘0’ (the “fan speed less than 80%” state). 3.3.14.1 Fan Monitor Requirements Fan monitor logic incorporates four timers (one for each fan tachometer input). Each timer has a duration of 40.995ms. When the fan monitors are enabled, each timer waits for the corresponding fan tach input to go high, and then begins counting up. If the fan tach goes low before the timer reaches 40.995ms, the timer is reset to 0 and waits for fan tach to transition high again. If fan tach doesn’t go low within the 40.995ms, the fan status flag is set to ‘0’ (fan stalled), and the timer is frozen at the maximum count. To reset the status flag to ‘1’ (fan running) and restart the timer, the CPU reads the Fan Read/Set Status register. [FRD_NGNICVBPCI_FAN_1680>HRD_NGNIC_Func_0440 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1680>HRD_NGNIC_Func_0440" ] [FRD_NGNICVBPCI_FAN_1680>HRD_NGNIC_Func_0380 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1680>HRD_NGNIC_Func_0380" ] After reset, the four fan monitors shall be disabled (DINs 60-63 set to ‘0’) until the CPU reads the Fan Read/Set Status register at address 7312:0004H. Refer to section 3.3.10 Discrete Inputs for a description of the read behavior of the Fan Read/Set Status register. [FRD_NGNICVBPCI_FAN_1690>HRD_NGNIC_Func_0460 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1690>HRD_NIC_Func_0460" ] [FRD_NGNICVBPCI_FAN_1690>HRD_NGNIC_ Safe_0200 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1690>HRD_NIC_Func_0460" ] If fan monitor 1 is enabled (DIN60 = ‘1’) and FANTACH(1) goes high for greater than 41ms, DIN60 shall be set to ‘0’ (fan not running, fan monitor 1 disabled). [FRD_NGNICVBPCI_FAN_1700>HRD_NGNIC_Func_0460 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1700>HRD_NGNIC_Func_0460" ] [FRD_NGNICVBPCI_FAN_1700>HRD_NGNIC_Safe_0200 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1700>HRD_NGNIC_Func_0460" ] If fan monitor 2 is enabled (DIN61 = ‘1’) and FANTACH(2) goes high for greater than 41ms, DIN61 shall be set to ‘0’ (fan not running, fan monitor 2 disabled). [FRD_NGNICVBPCI_FAN_1710>HRD_NGNIC_Func_0460 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1710>HRD_NGNIC_Func_0460" ] [FRD_NGNICVBPCI_FAN_1710>HRD_NGNIC_Safe_0200 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1710>HRD_NGNIC_Func_0460" ] If fan monitor 3 is enabled (DIN62 = ‘1’) and FANTACH(3) goes high for greater than 41ms, DIN62 shall be set to ‘0’ (fan not running, fan monitor 3 disabled). [FRD_NGNICVBPCI_FAN_1720>HRD_NGNIC_Func_0460 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1720>HRD_NGNIC_Func_0460" ] [FRD_NGNICVBPCI_FAN_1720>HRD_NGNIC_Safe_0200 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1720>HRD_NGNIC_Func_0460" ] If fan monitor 4 is enabled (DIN63 = ‘1’) and FANTACH(4) goes high for greater than 41ms, DIN63 shall be set to ‘0’ (fan not running, fan monitor 4 disabled). [FRD_NGNICVBPCI_FAN_1730>HRD_NGNIC_Func_0460 XE \f "TRACETAG" "FRD_NGNICVBPCI_FAN_1730>HRD_NGNIC_Func_0460" ] Fan monitoring discrete inputs shall be synchronized to CLK_25. Commentary: All inputs have to be registered through two flip-flops to avoid glitches. 3.3.15 Fault Containment Function (FCI) Poor Fault containment is one of the major factors affecting incorrect identification of failed modules. A key weakness with the PCI bus specification is that any failing module (asserting SERR_N), even if it doesn't electrically load down the bus, can prevent communication to all other modules on that bus. In order to support master PCI bridges on the VbPCI busses, each slot is supplied a REQ_N line to the NIC (system slot) for use in arbitration between the masters. A GNT_N line is supplied to each slot to indicate if the master has been granted bus use. These signals currently not used by the VbPCI Master Interface. Future provision for fault isolation monitor functions will use the REQ_N and GNT_N installed traces for routing of individual module resets and SERR_N signals. By using two spare pins from each client module, the groundwork has been set to allow the NIC to monitor which client module failed. To implement actual monitoring functionality on the NG_NICVBPCI FPGA, future BIC redesign activities will be required. [FRD_NGNICVBPCI_FCI_1740>HRD_NGNIC_BP_0800 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1740>HRD_NGNIC_BP_0800" ] The NG_NICVBPCI FPGA shall provide eight independent SLOT_SERR_N input signals. [FRD_NGNICVBPCI_FCI_1750>HRD_NGNIC_BP_0800 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1750>HRD_NGNIC_BP_0800" ] [FRD_NGNICVBPCI_FCI_1750>HRD_NGNIC_Func_0850 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1750>HRD_NGNIC_Func_0850" ] The NG_NICVBPCI FPGA shall provide eight independently controllable VB_SLOT_RST_N output signals for multiple VbPCI Bus 1 clients. Commentary: to monitor SERR_N signals from multiple clients on the PCI Bus1, the unused signal VB_REQ_N(0:7) will be used. This is the a deviation from the PCI 2.1 specification which required SERR_N signal to be implemented as an open-drain shared line which accepts multiple SERR_N signals simultaneously. In this design SERR_N will be a sustained tri-state signal using REQ_N line from each client. To monitor RST_N signals from multiple clients of the PCI Bus 1 unused signals VB_GNT_L (0:7) will be used. [FRD_NGNICVBPCI_FCI_1760>HRD_NGNIC_Func_0860 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1760>HRD_NGNIC_Func_0860" ] The NG_NICVBPCI FPGA shall control the FCI Slot Reset signals by using the DOUTs VB_SLOT_RST_N(7:0)/ DOUT(50:43) as shown in Table 24. Commentary: Refer to DOUTs paragraph 3.3.9. [FRD_NGNICVBPCI_FCI_1770>HRD_NGNIC_Func_0860 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1770>HRD_NGNIC_Func_0860" ] The NG_NICVBPCI FPGA shall support PCI Bus 0 writes/ reads of the DOUT register and specifically the VB_SLOT_RST_N(7:0) discrete outputs DOUT (43:50) as defined by Table 24. [FRD_NGNICVBPCI_FCI_1780> HRD_NGNIC_Func_0448 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1780>Derived" ] The NG_NICVBPCI FPGA shall set up VB_SLOT_RST_N signals to de-asserted state (high) during CCA initialization and until commanded otherwise. [FRD_NGNICVBPCI_FCI_1790>HRD_NGNIC_Func _0865 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1790>HRD_NGNIC_Func _0865" ] The NG_NICVBPCI FPGA shall detect a High to Low transition on any VB_SLOT_SERR_N signal and latch the corresponding VB_SLOT_SERR_N(7:0) bit to the asserted (low) state. [FRD_NGNICVBPCI_FCI_1800>HRD_NGNIC_Func _0870 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1800>HRD_NGNIC_Func _0870" ] The NG_NICVBPCI FPGA shall latch and hold the state of the detected VB_SLOT_SERR_N signals. [FRD_NGNICVBPCI_FCI_1810>HRD_NGNIC_Func _0870 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1810>HRD_NGNIC_Func _0870" ] The VB_SLOT_SERR_N latches shall be initialized to the de-asserted (high) state when CCA_RST_N is asserted low or SLOT_SERR_RST/ DOUT(51) is asserted high. Commentary: the VB_SLOT_SERR latches can be cleared by using DOUT(51) as a common reset for all VB_SLOT_SERR_N signals or hardware reset CCA_RST_N. [FRD_NGNICVBPCI_FCI_1820>HRD_NGNIC_Func _0870 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1820>HRD_NGNIC_Func _0870" ] The state of the detected VB_SLOT_SERR_N signals shall be readable by Software as discrete inputs DINs as defined in Table 27. Commentary: Refer to DINs paragraph 3.3.10. [FRD_NGNICVBPCI_FCI_1830>HRD_NGNIC_Func_0870 XE \f "TRACETAG" "FRD_NGNICVBPCI_FCI_1830>HRD_NGNIC_Func_0870" ] The NG_NICVBPCI FPGA shall initialize VB_SLOT_SERR/ DIN(53:50, 59:56) discrete Inputs to reset value as defined in Table 27. 3.3.16 JTAG and Programming The NG_NICVBPCI will be implemented in a flash based, which has a built in JTAG Test/Programming Port. Please refer to the applicable device data sheet for the definition and characteristics of the JTAG Port. [FRD_NGNICVBPCI_JTAG_1840>HRD_NGNICM_Mod_0047 XE \f "TRACETAG" "FRD_NGNICVBPCI_JTAG_1840>HRD_NGNICM_Mod_0047" ] [FRD_NGNICVBPCI_JTAG_1840>HRD_NGNIC_CoreFunc_1540 XE \f "TRACETAG" "FRD_NGNICVBPCI_JTAG_1840>HRD_NGNIC_CoreFunc_1540" ] The NG_NICVBPCI shall be implemented in an FPGA that has a built in JTAG test port. [FRD_NGNICVBPCI_JTAG_1850>HRD_NGNICM_Mod_0047 XE \f "TRACETAG" "FRD_NGNICVBPCI_JTAG_1850>HRD_NGNICM_Mod_0047" ] [FRD_NGNICVBPCI_JTAG_1850>HRD_NGNIC_CoreFunc_1550 XE \f "TRACETAG" "FRD_NGNICVBPCI_JTAG_1850>HRD_NGNIC_CoreFunc_1550" ] XE \f "TRACETAG" " " The following signals shall be used for the boundary scan chain: FPGA1_TCK Boundary Scan Testability Clock (input only) FPGA1_TDI Boundary Scan Test Data Input (input only) FPGA1_TDO Boundary Scan Test Data Output (output only) B_TMS Boundary Scan Test Mode Select (input only) B_TRSTB_N Boundary Scan Test Reset; Active Low (input only) APPENDIX A TRACEABILITY INDEX APPENDIX A TRACEABILITY INDEX This section shall contain the generated list which maps the requirements contained in this document to their corresponding requirements in the Hardware Requirements Document and other documents. HWEP-73, Hardware Requirements Tracing, defines the methods to be used to trace requirements, including features in the HRD. The need to use tracing techniques for in-progress projects is to be determined at the project level. This template has a trace tag style and includes a trace index macro as described in HWEP-73. FRD_NGNICVBPCI_APM_0780>HRD_NGNIC_Func_0662 46 FRD_NGNICVBPCI_APM_0780>HRD_NGNIC_Func_0666 46 FRD_NGNICVBPCI_APM_0790>DERIVED 46 FRD_NGNICVBPCI_APM_0800>HRD_NGNIC_Func_0664 47 FRD_NGNICVBPCI_APM_0810>HRD_NGNIC_Func_0668 47 FRD_NGNICVBPCI_APM_0820>HRD_NGNIC_Func_0662 48 FRD_NGNICVBPCI_APM_0820>HRD_NGNIC_Func_0668 48 FRD_NGNICVBPCI_APM_0830>HRD_NGNIC_Func_0662 48 FRD_NGNICVBPCI_CLK_0120>DERIVED 23 FRD_NGNICVBPCI_DIO_0870>HRD_NGNIC_CoreFunc_0830 50 FRD_NGNICVBPCI_DIO_0880>HRD_NGNIC_CoreFunc_0820 50 FRD_NGNICVBPCI_DIO_0880>HRD_NGNIC_CoreFunc_0830 50 FRD_NGNICVBPCI_DIO_0890>HRD_NIC_Func_0265 51 FRD_NGNICVBPCI_DIO_0900>HRD_NGNIC_CoreFunc_0820 51 FRD_NGNICVBPCI_DIO_0900>HRD_NGNIC_CoreFunc_0830 51 FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0820 51 FRD_NGNICVBPCI_DIO_0910>HRD_NGNIC_CoreFunc_0830 51 FRD_NGNICVBPCI_DIO_0920>DERIVED 52 FRD_NGNICVBPCI_DIO_0930>HRD_NGNIC_CoreFunc_0038 53 FRD_NGNICVBPCI_DIO_0930>HRD_NIC_Func_0330 53 FRD_NGNICVBPCI_DIO_0940>HRD_NGNIC_CoreFunc_0800 55 FRD_NGNICVBPCI_DIO_0950>HRD_NIC_Func_0330 55 FRD_NGNICVBPCI_DIO_0960>DERIVED 55 FRD_NGNICVBPCI_DIO_0970>HRD_NGNIC_CoreFunc_0810 56 FRD_NGNICVBPCI_DIO_0980>HRD_NIC_Func_0470 56 FRD_NGNICVBPCI_DIO_0990>DERIVED 56 FRD_NGNICVBPCI_DMA_1010>DERIVED 60 FRD_NGNICVBPCI_DMA_1011>DERIVED 60 FRD_NGNICVBPCI_DMA_1020>HRD_NGNIC_Func_0120 60 FRD_NGNICVBPCI_DMA_1030>HRD_NGNIC_Func_0120 60 FRD_NGNICVBPCI_DMA_1040>HRD_ HRD_NGNIC_Func_0120 61 FRD_NGNICVBPCI_DMA_1050>HRD_NGNIC_Func_0130 61 FRD_NGNICVBPCI_DMA_1060>HRD_NGNIC_Func_0120 61 FRD_NGNICVBPCI_DMA_1070>HRD_NGNIC_Func_0120 61 FRD_NGNICVBPCI_DMA_1075>Derived 61 FRD_NGNICVBPCI_DMA_1080>HRD_NGNIC_Func_0120 61 FRD_NGNICVBPCI_DMA_1085>HRD_NGNIC_Func_0120 62 FRD_NGNICVBPCI_DMA_1090>HRD_NGNIC_Func_0140 62 FRD_NGNICVBPCI_DMA_1095>HRD_NGNIC_Func_0140 62 FRD_NGNICVBPCI_DMA_1100>HRD_NGNIC_Func_0120 63 FRD_NGNICVBPCI_DMA_1105>HRD_NGNIC_Func_0120 63 FRD_NGNICVBPCI_DMA_1110>HRD_NGNIC_Func_0160 63 FRD_NGNICVBPCI_DMA_1115>HRD_NGNIC_Func_0160 64 FRD_NGNICVBPCI_DMA_1120>HRD_NGNIC_Func_0160 64 FRD_NGNICVBPCI_DMA_1130>HRD_NGNIC_Func_0160 65 FRD_NGNICVBPCI_DMA_1140>DERIVED 65 FRD_NGNICVBPCI_DMA_1180>HRD_NGNIC_Func_0090 65 FRD_NGNICVBPCI_DMA_1190>DERIVED 65 FRD_NGNICVBPCI_DMA_1191>HRD_NGNIC_Func_0330 65 FRD_NGNICVBPCI_DMA_1192>DERIVED 65 FRD_NGNICVBPCI_DMA_1193>DERIVED 66 FRD_NGNICVBPCI_DMA_1200>DERIVED 66 FRD_NGNICVBPCI_DMA_1210>DERIVED 66 FRD_NGNICVBPCI_DMA_1220>DERIVED 66 FRD_NGNICVBPCI_DMA_1221>DERIVED 66 FRD_NGNICVBPCI_DMA_1222>DERIVED 66 FRD_NGNICVBPCI_DPR_1230>DERIVED 67 FRD_NGNICVBPCI_DPR_1240>DERIVED 67 FRD_NGNICVBPCI_DPR_1250>DERIVED 67 FRD_NGNICVBPCI_DPR_1260>DERIVED 68 FRD_NGNICVBPCI_DPR_1270>DERIVED 68 FRD_NGNICVBPCI_DPR_1280>DERIVED 68 FRD_NGNICVBPCI_DPR_1281>DERIVED 68 FRD_NGNICVBPCI_DPR_1282>DERIVED 68 FRD_NGNICVBPCI_DPR_1283>DERIVED 68 FRD_NGNICVBPCI_DPR_1284>DERIVED 68 FRD_NGNICVBPCI_DPR_1290>DERIVED 69 FRD_NGNICVBPCI_DPR_1300>DERIVED 69 FRD_NGNICVBPCI_DPR_1310>DERIVED 69 FRD_NGNICVBPCI_DPR_1320>DERIVED 69, 70 FRD_NGNICVBPCI_DPR_1340>DERIVED 70 FRD_NGNICVBPCI_DPR_1350>DERIVED 70 FRD_NGNICVBPCI_DPR_1360>DERIVED 70 FRD_NGNICVBPCI_DPR_1370>DERIVED 71 FRD_NGNICVBPCI_DPR_1380>DERIVED 72 FRD_NGNICVBPCI_DPR_1390>DERIVED 73 FRD_NGNICVBPCI_DPR_1400>DERIVED 74 FRD_NGNICVBPCI_DPR_1410>DERIVED 74 FRD_NGNICVBPCI_DPR_1420>DERIVED 74 FRD_NGNICVBPCI_DPR_1430>DERIVED 74 FRD_NGNICVBPCI_DPR_1435>DERIVED 74 FRD_NGNICVBPCI_DPR_1440>DERIVED 74 FRD_NGNICVBPCI_DPR_1450>DERIVED 74 FRD_NGNICVBPCI_DPR_1451>DERIVED 74 FRD_NGNICVBPCI_DPR_1460>DERIVED 75 FRD_NGNICVBPCI_FAN_1680>HRD_NGNIC_Func_0380 82 FRD_NGNICVBPCI_FAN_1680>HRD_NGNIC_Func_0440 82 FRD_NGNICVBPCI_FAN_1690>HRD_NIC_Func_0460 82 FRD_NGNICVBPCI_FAN_1700>HRD_NGNIC_Func_0460 82 FRD_NGNICVBPCI_FAN_1710>HRD_NGNIC_Func_0460 82 FRD_NGNICVBPCI_FAN_1720>HRD_NGNIC_Func_0460 82 FRD_NGNICVBPCI_FAN_1730>HRD_NGNIC_Func_0460 83 FRD_NGNICVBPCI_FCI_1740>HRD_NGNIC_BP_0800 83 FRD_NGNICVBPCI_FCI_1750>HRD_NGNIC_BP_0800 83 FRD_NGNICVBPCI_FCI_1750>HRD_NGNIC_Func_0850 83 FRD_NGNICVBPCI_FCI_1760>HRD_NGNIC_Func_0860 84 FRD_NGNICVBPCI_FCI_1770>HRD_NGNIC_Func_0860 84 FRD_NGNICVBPCI_FCI_1780>Derived 84 FRD_NGNICVBPCI_FCI_1790>HRD_NGNIC_Func _0865 84 FRD_NGNICVBPCI_FCI_1800>HRD_NGNIC_Func _0870 84 FRD_NGNICVBPCI_FCI_1810>HRD_NGNIC_Func _0870 84 FRD_NGNICVBPCI_FCI_1820>HRD_NGNIC_Func _0870 84 FRD_NGNICVBPCI_FCI_1830>HRD_NGNIC_Func_0870 84 FRD_NGNICVBPCI_I2C_1470>DERIVED 76 FRD_NGNICVBPCI_I2C_1480>DERIVED 76 FRD_NGNICVBPCI_I2C_1490>DERIVED 76 FRD_NGNICVBPCI_I2C_1500>DERIVED 76 FRD_NGNICVBPCI_I2C_1510>DERIVED 76 FRD_NGNICVBPCI_I2C_1511>DERIVED 76 FRD_NGNICVBPCI_I2C_1512>DERIVED 77 FRD_NGNICVBPCI_I2C_1520>DERIVED 77 FRD_NGNICVBPCI_I2C_1530>DERIVED 78 FRD_NGNICVBPCI_I2C_1540>DERIVED 78 FRD_NGNICVBPCI_I2C_1550>DERIVED 78 FRD_NGNICVBPCI_I2C_1551>DERIVED 78 FRD_NGNICVBPCI_I2C_1560>DERIVED 78 FRD_NGNICVBPCI_I2C_1570>DERIVED 79 FRD_NGNICVBPCI_I2C_1571>DERIVED 79 FRD_NGNICVBPCI_I2C_1572>DERIVED 79 FRD_NGNICVBPCI_I2C_1573>DERIVED 79 FRD_NGNICVBPCI_I2C_1580>DERIVED 79 FRD_NGNICVBPCI_I2C_1590>DERIVED 79 FRD_NGNICVBPCI_I2C_1600>HRD_NGNIC_Func_0730 79 FRD_NGNICVBPCI_I2C_1610>HRD_NGNIC_Func_0730 80 FRD_NGNICVBPCI_I2C_1620>DERIVED 80 FRD_NGNICVBPCI_I2C_1630>DERIVED 80 FRD_NGNICVBPCI_I2C_1640>DERIVED 81 FRD_NGNICVBPCI_I2C_1650>DERIVED 81 FRD_NGNICVBPCI_I2C_1660>DERIVED 81 FRD_NGNICVBPCI_I2C_1665>DERIVED 81 FRD_NGNICVBPCI_I2C_1670>DERIVED 81 FRD_NGNICVBPCI_I2C_1671>DERIVED 81 FRD_NGNICVBPCI_I2C_1675>DERIVED 81 FRD_NGNICVBPCI_ID_0840>HRD_NGNICM_Mod_0070 49 FRD_NGNICVBPCI_ID_0840>HRD_NIC_CoreFunc_1240 49 FRD_NGNICVBPCI_ID_0850>HRD_NGNICM_Mod_0090 49 FRD_NGNICVBPCI_ID_0860>HRD_NGNICM_Mod_0080 50 FRD_NGNICVBPCI_IO_0010>DERIVED 8 FRD_NGNICVBPCI_IO_0020>DERIVED 8 FRD_NGNICVBPCI_IO_0030>DERIVED 8 FRD_NGNICVBPCI_IO_0040>DERIVED 8 FRD_NGNICVBPCI_IO_0050>DERIVED 8 FRD_NGNICVBPCI_IO_0060>DERIVED 9 FRD_NGNICVBPCI_IO_0070>DERIVED 9 FRD_NGNICVBPCI_IO_0080>DERIVED 9 FRD_NGNICVBPCI_IO_0090>DERIVED 9 FRD_NGNICVBPCI_IO_0100>DERIVED 9 FRD_NGNICVBPCI_IO_0110>DERIVED 9 FRD_NGNICVBPCI_IPD_0190>HRD_NGNIC_CoreFunc_0720 25 FRD_NGNICVBPCI_IPD_0210>HRD_NGNIC_CoreFunc_0753 26 FRD_NGNICVBPCI_IPD_0210>HRD_NGNIC_CoreFunc_0754 26 FRD_NGNICVBPCI_IPD_0220>HRD_NGNIC_CoreFunc_0752 26 FRD_NGNICVBPCI_IPD_0221>DERIVED 26 FRD_NGNICVBPCI_IPD_0230>DERIVED 26 FRD_NGNICVBPCI_IPD_0240>DERIVED 26 FRD_NGNICVBPCI_JTAG_1840>HRD_NGNIC_CoreFunc_1540 84 FRD_NGNICVBPCI_JTAG_1840>HRD_NGNICM_Mod_0047 84 FRD_NGNICVBPCI_JTAG_1850>HRD_NGNIC_CoreFunc_1550 85 FRD_NGNICVBPCI_JTAG_1850>HRD_NGNICM_Mod_0047 85 FRD_NGNICVBPCI_MON_0260>DERIVED 27 FRD_NGNICVBPCI_MON_0280>HRD_NGNIC_CoreFunc_1100 27 FRD_NGNICVBPCI_MON_0385>Derived 33 FRD_NGNICVBPCI_MON_0386>Derived 33 FRD_NGNICVBPCI_PCI_0290>DERIVED 29 FRD_NGNICVBPCI_PCI_0300>DERIVED 29 FRD_NGNICVBPCI_PCI_0310>DERIVED 29 FRD_NGNICVBPCI_PCI_0330>HRD_NGNIC_CoreIO_0310 30 FRD_NGNICVBPCI_PCI_0340>HRD_NGNIC_CoreIO_0320 31 FRD_NGNICVBPCI_PCI_0350>DERIVED 31 FRD_NGNICVBPCI_PCI_0355>DERIVED 31 FRD_NGNICVBPCI_PCI_0360>DERIVED 32 FRD_NGNICVBPCI_PCI_0365>DERIVED 32 FRD_NGNICVBPCI_PCI_0370>DERIVED 32 FRD_NGNICVBPCI_PCI_0380>DERIVED 32 FRD_NGNICVBPCI_PCI_0390>DERIVED 33 FRD_NGNICVBPCI_PCI_0400>DERIVED 33 FRD_NGNICVBPCI_PCI_0410>DERIVED 34 FRD_NGNICVBPCI_PCI_0420>DERIVED 34 FRD_NGNICVBPCI_PCI_0425>DERIVED 34 FRD_NGNICVBPCI_PCI_0430>HRD_NGNIC_CoreIO_0330 34 FRD_NGNICVBPCI_PCI_0430>HRD_NGNIC_CoreIO_0340 34 FRD_NGNICVBPCI_PCI_0440>HRD_NGNIC_CoreIO_0330 35 FRD_NGNICVBPCI_PCI_0450>DERIVED 35 FRD_NGNICVBPCI_PCI_0460>DERIVED 35 FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0020 36 FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0030 36 FRD_NGNICVBPCI_PCI_0480>HRD_NGNIC_Func_0040 36 FRD_NGNICVBPCI_PCI_0490>HRD_NGNIC_BP_0100 36 FRD_NGNICVBPCI_PCI_0500>DERIVED 37 FRD_NGNICVBPCI_PCI_0510>HRD_NGNIC_BP_0102 37 FRD_NGNICVBPCI_PCI_0520>DERIVED 37 FRD_NGNICVBPCI_PCI_0550>HRD_NGNIC_Func_0030 38 FRD_NGNICVBPCI_PCI_0551>DERIVED 38 FRD_NGNICVBPCI_PCI_0552>DERIVED 38 FRD_NGNICVBPCI_PCI_0560>HRD_NGNIC_Func_0020 38 FRD_NGNICVBPCI_PCI_0570>HRD_NGNIC_Func_0060 38 FRD_NGNICVBPCI_PCI_0580>DERIVED 39 FRD_NGNICVBPCI_PCI_0590>HRD_NGNIC_Func_0070 39 FRD_NGNICVBPCI_PCI_0600>HRD_NGNIC_Func_0070 39 FRD_NGNICVBPCI_PCI_0610>HRD_NGNIC_Func_0075 39 FRD_NGNICVBPCI_PCI_0620>HRD_NGNIC_Func_0100 40 FRD_NGNICVBPCI_PCI_0630>HRD_NGNIC_Func_0110 41 FRD_NGNICVBPCI_PCI_0640>HRD_NGNIC_Func_0090 41 FRD_NGNICVBPCI_PCI_0650>HRD_NGNIC_Func_0235 42 FRD_NGNICVBPCI_PCI_0650>HRD_NGNIC_Func_0237 42 FRD_NGNICVBPCI_PCI_0660>HRD_NGNIC_Func_0200 42 FRD_NGNICVBPCI_PCI_0660>HRD_NGNIC_Func_0210 42 FRD_NGNICVBPCI_PCI_0670>HRD_NGNIC_Func_0220 42 FRD_NGNICVBPCI_PCI_0670>HRD_NGNIC_Func_0230 42 FRD_NGNICVBPCI_PCI_0680>HRD_NGNIC_Func_0250 42 FRD_NGNICVBPCI_PCI_0680>HRD_NGNIC_Func_0260 42 FRD_NGNICVBPCI_PCI_0690>DERIVED 43 FRD_NGNICVBPCI_PCI_0700>DERIVED 43 FRD_NGNICVBPCI_PCI_0710>DERIVED 44 FRD_NGNICVBPCI_PCI_0720>DERIVED 44 FRD_NGNICVBPCI_PCI_0730>DERIVED 44 FRD_NGNICVBPCI_PCI_0740>DERIVED 44 FRD_NGNICVBPCI_PCI_0750>DERIVED 44 FRD_NGNICVBPCI_PCI_0760>DERIVED 45 FRD_NGNICVBPCI_PCI_0770>DERIVED 45, 46 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0330 23 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0360 23 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0370 23 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0380 23 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0400 23 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0430 23 FRD_NGNICVBPCI_RST _0130>HRD_NGNIC_Func_0448 23 FRD_NGNICVBPCI_RST _0140>HRD_NIC_Func_0330 23 FRD_NGNICVBPCI_RST _0150>HRD_NGNIC_Func_0330 24 FRD_NGNICVBPCI_RST _0160>DERIVED 24 FRD_NGNICVBPCI_RST _0170>HRD_NGNIC_Func_0240 25 FRD_NGNICVBPCI_RST _0170>HRD_NGNIC_Func_0360 25 FRD_NGNICVBPCI_RST _0170>HRD_NGNICM_Mod_0060 25 FRD_NGNICVBPCI_RST _0180>HRD_NGNIC_Func_0190 25 FRD_NGNICVBPCI_RST _0180>HRD_NGNIC_Func_0370 25 FRD_NGNICVBPCI_SAFE_0250>HRD_NGNIC_CoreSafe_0120 27 FRD_NGNICVBPCI_SAFE_0850>HRD_NGNIC_CoreSafe_0130 49 AW/CRITICAL NOTATION TITLE PAGE CR-1 SECURITY NOTATION PAGE 15101-000 (REV 970213 BCAS ASF5900/ENG_SPEC.DOT) (REV 07/18/2000 OFC97-DATA SERVICES) HONEYWELL INTERNATIONAL INC. _1243158145.vsd _1261392792.vsd MPC8280 I/F Mezz Conn. DPRAM Arbitrator Auto DMA PCI 0 VbPCI Master I/F 25 MHz Internal DPRAM buffer Mezz Conn. Discrete Inputs Host ID Interface PCI Client I/F PCI_CLK I2C Serial I/F IPD Monitor Discrete Outputs POL Monitors Clocks, Reset NG_NIC Core FPGA RTC/Temp. Monitor To VbPCI Bus 2 IPD_strobe_N IPD_valid clk20, clk25, pci_clk CCA_RST# JTAG Bus Add/Data Control VbPCI I/F Auto_dma_done Fault Isolation Slot_serr# Slot_RST# VbPCI Bus 1 EEPROM Front Connector DPRAM I/F Left Port Fan Control APM Interface FAN Tachs NIC DPRAM Left Port P/S Test Bus VbPCI Bus 1 JTAG _1273562769.vsd Ax A1 A2 A3 clk25 NIC_AD[16:2]-address NIC_ADS# NIC_CE# NIC_RW# NIC_AD[31:0]-data NIC_OE# 1 2 3 4 tSA Tclk2add tHA Tclk2add Tclk2add Tclk2add tCLK_OUT tCLK_OUT tSC tCLK_OUT tHC tCLK_OUT tSC tCLK_OUT tHC D1 Tclk2data tSD Tclk2data tHD tSC tCLK_OUT2 tCLK_OUT2 _1238234922.txt Header ( company("Forte Design Systems") product("TimingDesigner") rev("6.504") file("d:\\my_documents\\mau_platforms\\ca3_project\\design\\timing analysis\\vbpci_dpram_rd_single.tdk") date("04/16/2007") time("13:22") format("5.0") baseScale(1000.000000) zoomFactor("0.000568568") simHDL(VHDL) simDelayMechanism(Transport) nextID(97) TimingAnalysisMethod(51) user(date,"") user(description,"") user(designer,"") user(revision,"1.0") generalPrintParams( "printer,,,landscape,clipboard,letter,default,7,4,in,color,scaleable,") diagramPrintParams( "0,6,40000,241000,true,false,1,1,true,false,false,false,all,specified") spreadsheetPrintParams( "0,17,true,false,1,true,all") ) HDLHeader( hdlFile("") checkConstraints(true) checkTimeout(never) command( name("") cmdType(null) )) DefaultLabel( delay(showNameString,"") constraint(showNameString,"") guarantee(showNameString,"") measure(showMeasure,"") store(showNameString,"") wait(showNameString,"") end(showNameString,"") boundary(showIncrement,"") loop(showNameString,"") waveform(showSkip,"","") specifiedclock(showSkip,"","") derivedclock(showSkip,"","") simwaveform(showSkip,"","") bus(showValue,"","") ) DiagramStyle ( waveformFont(winFont("Arial",90) ) rulerFont(winFont("Arial",90) ) relationshipFont(winFont("Arial",90) ) labelFont(winFont("Arial",90) ) annotationFont(winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") ) slotHeight("11") edgeHeight("11") edgeGrade("1.96261") inputPenStyle(0) outputPenStyle(0) inoutPenStyle(0) internalPenStyle(0) vRelationshipPenStyle(0) hRelationshipPenStyle(0) inputPenColor(3) outputPenColor(3) inoutPenColor(3) internalPenColor(3) wavePenWidth("0") relationshipPenWidth("0") wavesOnTop relationshipsOnTop annotationsOnTop showSlopedEdges showUncertainties ) Clock ( objectID(2) name("clk25") minheight("0") periodScale(1000) period(40.000480) dutyCycle(50.000000) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(6) name("NIC_A[16:2]-addr") minheight("0") edges( (invalid,0,0,L), (valid,55480.5,55480.5,label(showText,"Ap","") ), (valid,95481,95481,label(showText,"A1","") ), (valid,135481,135481,label(showText,"A2","") ), (valid,175482,175482,label(showText,"A3","") ), (valid,215482,215482,label(showText,"An","") ), (invalid,255483,255483), (valid,329000,329000), (blank,332723,332723)) hdl( direction(inOut) ) label(showDefault,"","") ) Waveform ( objectID(7) name("NIC_CS#(CE0)") minheight("0") edges( (high,0,0,L), (low,85181,85561), (high,325184,325564), (blank,331723,331723)) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(44) name("NIC_RW#") minheight("0") edges( (low,0,0,L), (high,85181,85561), (low,325184,325564), (blank,330723,330723)) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(49) name("NIC_ADS#") minheight("0") edges( (high,0,0,L), (low,85181,85561), (high,325184,325564), (blank,335000,335000)) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(19) name("NIC_A[31:0]-data") minheight("0") edges( (z,0,0,L), (valid,161502,171062,label(showText,"D1","") ), (valid,203562,211062,label(showText,"D2","") ), (valid,243563,251063,label(showText,"D3","") ), (valid,283563,291063,label(showText,"Dn","") ), (valid,328744,335124), (blank,366723,366723)) hdl( direction(output) ) label(showDefault,"","") ) Waveform ( objectID(9) name("NIC_OE#") minheight("0") edges( (high,0,0,L), (low,85181,85561), (high,325184,325564), (blank,351723,351723)) hdl( direction(input) ) label(showDefault,"","") ) Grid ( "clk25" topWave("clk25") color(8) 1stWidth(0) 2ndWidth(0) 1stStyle(1) 2ndStyle(0) show1st ) Annotation( value("0") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",1) origin(-3029.51,20) edgeCentered ) Annotation( value("1") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",3) origin(-2294.27,20) edgeCentered ) Annotation( value("2") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",5) origin(-1335.63,20) edgeCentered ) Annotation( value("3") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",7) origin(-2154.24,20) edgeCentered ) Annotation( value("4") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",9) origin(-1195.6,20) edgeCentered ) Annotation( value("5") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",11) origin(-1303.31,20) edgeCentered ) Annotation( value("6") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",13) origin(-1411.02,20) edgeCentered ) Annotation( value("7") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",15) origin(-2229.63,20) edgeCentered ) Annotation( value("8") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",17) origin(-1270.99,20) edgeCentered ) Annotation( value("Dual Port RAM Singe Read Access from Left Port, with 1.5 safety factor, pipelined.\r\n") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") origin(0,0) topCenter ) Annotation( value("This timing waveform was created using the IDT70V3579S6\r\n datasheet.") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") origin(0,0) bottomCenter ) EndCycleEvent ( objectID(1) name("end") time(241.000000) showVert hideOnPrinter label(showDefault,"") fromLatestEnd toEarliestBegin ) Delay ( name("Tclk2add") value("[15.48,0]") comment("Actel(tPT+tDP+tDIN+tEOUT+tZL+tPD=11.18)*1.2+Net delay(2.06)") instance(objectID(16) source("clk25",2) target("NIC_A[16:2]-addr",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(47) source("clk25",4) target("NIC_A[16:2]-addr",2) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(54) source("clk25",6) target("NIC_A[16:2]-addr",3) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(55) source("clk25",8) target("NIC_A[16:2]-addr",4) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(56) source("clk25",10) target("NIC_A[16:2]-addr",5) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(57) source("clk25",12) target("NIC_A[16:2]-addr",6) label(showDefault,"") fromLatestBegin toLatestEnd )) Delay ( name("tCLK_OUT") value("[5.18,5.56]") comment("Actel CLK input to output delay(tPY+tICLKQ+tOCLKQ=2.16min, 2.92max)*1.2 +Net delay(2.06)") instance(objectID(28) source("clk25",4) target("NIC_CS#(CE0)",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(48) source("clk25",4) target("NIC_RW#",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(50) source("clk25",4) target("NIC_ADS#",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(77) source("clk25",16) target("NIC_ADS#",2) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(78) source("clk25",16) target("NIC_CS#(CE0)",2) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(79) source("clk25",16) target("NIC_RW#",2) label(showDefault,"") fromLatestBegin toLatestEnd )) Constraint ( name("tSA") value("[([2,2]*[1.5,1.5]),]") comment("DP address setup time") instance(objectID(51) source("NIC_A[16:2]-addr",2) target("clk25",6) MarginValue("[21.52048,]") label(showDefault,"") fromLatestEnd toEarliestBegin slot(4) bottom )) Constraint ( name("tHA") value("[([1,1]*[1.5,1.5]),]") comment("DP address hold time") instance(objectID(52) source("clk25",6) target("NIC_A[16:2]-addr",3) MarginValue("[13.98,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Delay ( name("tCD2") value("[([1,1]*[1.5,1.5]),(([6,6]*[1.5,1.5])+[2.06,2.06])]") comment("DP Clk to data valid +Net delay(2.06)") instance(objectID(53) source("clk25",8) target("NIC_A[31:0]-data",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(74) source("clk25",10) target("NIC_A[31:0]-data",2) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(86) source("clk25",14) target("NIC_A[31:0]-data",4) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(87) source("clk25",12) target("NIC_A[31:0]-data",3) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(92) source("clk25",16) target("NIC_A[31:0]-data",5) label(showDefault,"") fromLatestBegin toLatestEnd )) Constraint ( name("tSC") value("[([2,2]*[1.5,1.5]),]") comment(" DP chip enable set up time") instance(objectID(58) source("NIC_OE#",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom ) instance(objectID(68) source("NIC_CS#(CE0)",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tSW") value("[([2,2]*[1.5,1.5]),]") comment("DP write set up time") instance(objectID(59) source("NIC_RW#",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tSAD") value("[([2,2]*[1.5,1.5]),]") comment(" DP ADS# set up time") instance(objectID(60) source("NIC_ADS#",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tCLKZ") value("[1.5,]") comment("DP Clock high to output High Z") instance(objectID(61) source("clk25",8) target("NIC_A[31:0]-data",1) MarginValue("[0,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Delay ( name("tDC") value("[(([1,1]*[1.5,1.5])+[2.06,2.06]),0]") comment("DP Data out after clk High(1*1.5)+net delay(2.06)") instance(objectID(88) source("clk25",10) target("NIC_A[31:0]-data",2) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(89) source("clk25",14) target("NIC_A[31:0]-data",4) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(91) source("clk25",12) target("NIC_A[31:0]-data",3) label(showDefault,"") fromLatestBegin toLatestEnd )) Constraint ( name("tIHD") value("[0,]") comment("Actel input register data hold time* 1.2") instance(objectID(80) source("clk25",10) target("NIC_A[31:0]-data",2) MarginValue("[3.56,]") label(showDefault,"") fromLatestEnd toEarliestBegin slot(4) bottom ) instance(objectID(81) source("clk25",12) target("NIC_A[31:0]-data",3) MarginValue("[3.56,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tISUD") value("[([0.69,0.69]*[1.2,1.2]),]") comment("Actel input register data setup time(0.43-0.69min)*1.2") instance(objectID(71) source("NIC_A[31:0]-data",1) target("clk25",10) MarginValue("[28.11248,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tHC") value("[([1,1]*[1.5,1.5]),]") comment("DP chip enable hold time") instance(objectID(82) source("clk25",16) target("NIC_CS#(CE0)",2) MarginValue("[3.68,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tHW") value("[([1,1]*[1.5,1.5]),]") comment("write hold time") instance(objectID(83) source("clk25",16) target("NIC_RW#",2) MarginValue("[3.68,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("latency") value("[,]") comment("DP read Latency between first address and first data out (one clk sycle)") instance(objectID(85) source("clk25",6) target("clk25",8) MarginValue("[,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Delay ( name("tOHZ") value("[(([1,1]*[1.5,1.5])+[2.06,2.06]),(([5,5]*[1.5,1.5])+[2.06,2.06])]") comment("Output enable to output high Z+net delay(2.06)") instance(objectID(90) source("NIC_OE#",2) target("NIC_A[31:0]-data",5) label(showDefault,"") fromLatestBegin toLatestEnd )) Delay ( name("tCLK_OUT2") value("[5.18,5.56]") comment("Actel CLK input to output delay(tPY+tICLKQ+tOCLKQ=2.16min, 2.92max)*1.2 +Net delay(2.06)") instance(objectID(93) source("clk25",4) target("NIC_OE#",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(94) source("clk25",16) target("NIC_OE#",2) label(showDefault,"") fromLatestBegin toLatestEnd )) ����� _1238235558.txt Header ( company("Forte Design Systems") product("TimingDesigner") rev("6.504") file("d:\\my_documents\\mau_platforms\\ca3_project\\design\\timing analysis\\vbpci_dpram_wr_single.tdk") date("04/16/2007") time("13:32") format("5.0") baseScale(1000.000000) zoomFactor("0.000568568") simHDL(VHDL) simDelayMechanism(Transport) nextID(109) TimingAnalysisMethod(51) user(date,"") user(description,"") user(designer,"") user(revision,"1.0") generalPrintParams( "printer,,,landscape,clipboard,letter,default,7,5,in,color,scaleable,") diagramPrintParams( "0,6,40000,200000,true,false,1,1,true,false,false,false,all,specified") spreadsheetPrintParams( "0,14,true,false,1,true,all") ) HDLHeader( hdlFile("") checkConstraints(true) checkTimeout(never) command( name("") cmdType(null) )) DefaultLabel( delay(showNameString,"") constraint(showNameString,"") guarantee(showNameString,"") measure(showMeasure,"") store(showNameString,"") wait(showNameString,"") end(showNameString,"") boundary(showIncrement,"") loop(showNameString,"") waveform(showSkip,"","") specifiedclock(showSkip,"","") derivedclock(showSkip,"","") simwaveform(showSkip,"","") bus(showValue,"","") ) DiagramStyle ( waveformFont(winFont("Arial",90) ) rulerFont(winFont("Arial",90) ) relationshipFont(winFont("Arial",90) ) labelFont(winFont("Arial",90) ) annotationFont(winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") ) slotHeight("11") edgeHeight("11") edgeGrade("1.96261") inputPenStyle(0) outputPenStyle(0) inoutPenStyle(0) internalPenStyle(0) vRelationshipPenStyle(0) hRelationshipPenStyle(0) inputPenColor(3) outputPenColor(3) inoutPenColor(3) internalPenColor(3) wavePenWidth("0") relationshipPenWidth("0") wavesOnTop relationshipsOnTop annotationsOnTop showSlopedEdges showUncertainties ) Clock ( objectID(2) name("clk25") minheight("0") periodScale(1000) period(40.000480) dutyCycle(50.000000) hdl( direction(internal) ) label(showDefault,"","") ) Waveform ( objectID(6) name("NIC_AD[16:2]-address") minheight("0") edges( (z,0,0,L), (valid,55480.5,55480.5,label(showText,"A1","") ), (valid,95481,95481,label(showText,"A2","") ), (valid,135481,135481,label(showText,"A3","") ), (valid,175482,175482,label(showText,"A4","") ), (invalid,215482,215482,label(showText,"","") ), (invalid,255483,255483), (blank,291000,291000)) hdl( direction(inOut) ) label(showDefault,"","") ) Waveform ( objectID(107) name("NIC_ADS#") minheight("0") edges( (high,0,0,L), (low,45180.5,45560.5), (high,216000,216000), (blank,269723,269723)) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(7) name("NIC_CE#") minheight("0") edges( (high,0,0,L), (low,85181,85561), (high,125181,125561), (blank,291000,291000)) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(44) name("NIC_RW#") minheight("0") edges( (high,0,0,L), (low,85181,85561), (high,125181,125561), (low,349000,349000), (blank,352723,352723)) hdl( direction(input) ) label(showDefault,"","") ) Waveform ( objectID(19) name("NIC_AD[31:0]-data") minheight("0") edges( (z,0,0,L), (valid,95481,95481,label(showText,"D1","") ), (z,135481,135481,label(showText,"D2","") ), (valid,303000,303000), (blank,306723,306723)) hdl( direction(inOut) ) label(showDefault,"","") ) Waveform ( objectID(9) name("NIC_OE#") minheight("0") edges( (low,0,0,L), (high,85181,85561), (low,125181,125561), (low,290000,290000), (blank,322723,322723)) hdl( direction(input) ) label(showDefault,"","") ) Grid ( "clk25" topWave("clk25") color(8) 1stWidth(0) 2ndWidth(0) 1stStyle(1) 2ndStyle(0) show1st ) Annotation( value("0") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",1) origin(-2186.56,20) edgeCentered ) Annotation( value("1") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",3) origin(-2294.27,20) edgeCentered ) Annotation( value("2") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",5) origin(-1335.63,20) edgeCentered ) Annotation( value("3") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",7) origin(-2154.24,20) edgeCentered ) Annotation( value("4") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",9) origin(-1195.6,20) edgeCentered ) Annotation( value("5") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",11) origin(-1303.31,20) edgeCentered ) Annotation( value("6") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",13) origin(-1411.02,20) edgeCentered ) Annotation( value("7") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",15) origin(-2229.63,20) edgeCentered ) Annotation( value("8") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") Edge("clk25",17) origin(-1270.99,20) edgeCentered ) Annotation( value("Dual Port RAM Single Write Access from Lefr Port, with 1.5 safety factor, pipelined.\r\n") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") origin(0,0) topCenter ) Annotation( value("This timing waveform was created using the IDT70V3579S6\r\n datasheet.") winFont("Arial",80) xFont("-misc-fixed-*-*-*-*-*-120-*-*-*-*-*-1") origin(0,0) bottomCenter ) EndCycleEvent ( objectID(1) name("end") time(200.000000) showVert hideOnPrinter label(showDefault,"") fromLatestEnd toEarliestBegin ) Delay ( name("Tclk2add") value("[15.48,0]") comment("Actel(tPY+tDP+tDIN+tEOUT+tZL+tPD=11.18)*1.2+Net delay(2.06)") instance(objectID(16) source("clk25",2) target("NIC_AD[16:2]-address",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(47) source("clk25",4) target("NIC_AD[16:2]-address",2) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(54) source("clk25",6) target("NIC_AD[16:2]-address",3) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(55) source("clk25",8) target("NIC_AD[16:2]-address",4) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(56) source("clk25",10) target("NIC_AD[16:2]-address",5) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(57) source("clk25",12) target("NIC_AD[16:2]-address",6) label(showDefault,"") fromLatestBegin toLatestEnd )) Delay ( name("tCLK_OUT") value("[5.18,5.56]") comment("Actel CLK input to output delay (tPY+tICLKQ+tOCLKQ=2.16min, 2.92max)*1.2+Net delay(2.06)") instance(objectID(28) source("clk25",4) target("NIC_CE#",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(48) source("clk25",4) target("NIC_RW#",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(78) source("clk25",6) target("NIC_CE#",2) label(showDefault,"") fromLatestBegin toLatestEnd slot(2) ) instance(objectID(79) source("clk25",6) target("NIC_RW#",2) label(showDefault,"") fromLatestBegin toLatestEnd )) Constraint ( name("tSA") value("[([2,2]*[1.5,1.5]),]") comment("DP address setup time") instance(objectID(51) source("NIC_AD[16:2]-address",1) target("clk25",4) MarginValue("[21.52048,]") label(showDefault,"") fromLatestEnd toEarliestBegin slot(3) bottom )) Constraint ( name("tHA") value("[([1,1]*[1.5,1.5]),]") comment("DP address hold time") instance(objectID(52) source("clk25",4) target("NIC_AD[16:2]-address",2) MarginValue("[13.98,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tSC") value("[([2,2]*[1.5,1.5]),]") comment(" DP chip enable set up time") instance(objectID(58) source("NIC_OE#",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom ) instance(objectID(68) source("NIC_CE#",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin slot(2) bottom )) Constraint ( name("tSW") value("[([2,2]*[1.5,1.5]),]") comment("DP write set up time") instance(objectID(59) source("NIC_RW#",1) target("clk25",6) MarginValue("[31.44048,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tHC") value("[([1,1]*[1.5,1.5]),]") comment("DP chip enable hold time") instance(objectID(82) source("clk25",6) target("NIC_CE#",2) MarginValue("[3.68,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Constraint ( name("tHW") value("[([1,1]*[1.5,1.5]),]") comment("DP write hold time") instance(objectID(83) source("clk25",6) target("NIC_RW#",2) MarginValue("[3.68,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Delay ( name("tCLK_OUT2") value("[5.18,5.56]") comment("Actel CLK input to output delay (tPY+tICLKQ+tOCLKQ=2.16min, 2.92max)*1.2+Net delay(2.06)") instance(objectID(93) source("clk25",4) target("NIC_OE#",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(94) source("clk25",6) target("NIC_OE#",2) label(showDefault,"") fromLatestBegin toLatestEnd )) Delay ( name("Tclk2data") value("[15.48,]") comment("Actel(tPY+tDP+tDIN+tEOUT+tZL+tPD=11.18)*1.2+Net delay(2.06)") instance(objectID(96) source("clk25",4) target("NIC_AD[31:0]-data",1) label(showDefault,"") fromLatestBegin toLatestEnd ) instance(objectID(97) source("clk25",6) target("NIC_AD[31:0]-data",2) label(showDefault,"") fromLatestBegin toLatestEnd slot(2) )) Constraint ( name("tSD") value("[([2,2]*[1.5,1.5]),]") comment("DP Input data setup time") instance(objectID(103) source("NIC_AD[31:0]-data",1) target("clk25",6) MarginValue("[21.52048,]") label(showDefault,"") fromLatestEnd toEarliestBegin slot(4) bottom )) Constraint ( name("tHD") value("[([1,1]*[1.5,1.5]),]") comment("DP Input data hold time") instance(objectID(104) source("clk25",6) target("NIC_AD[31:0]-data",2) MarginValue("[13.98,]") label(showDefault,"") fromLatestEnd toEarliestBegin bottom )) Delay ( name("tCLK_OUT") value("[5.18,5.56]") comment("Actel CLK input to output delay (tPY+tICLKQ+tOCLKQ=2.16min, 2.92max)*1.2+Net delay(2.06)") instance(objectID(108) source("clk25",2) target("NIC_ADS#",1) label(showDefault,"") fromLatestBegin toLatestEnd )) �