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首页 数字时钟(数字逻辑)课程设计报告.doc

数字时钟(数字逻辑)课程设计报告.doc

数字时钟(数字逻辑)课程设计报告.doc

上传者: 桀骜少年 2011-10-10 评分 0 0 0 0 0 0 暂无简介 简介 举报

简介:本文档为《数字时钟(数字逻辑)课程设计报告doc》,可适用于IT/计算机领域,主题内容包含数字时钟班级:学号:姓名:指导老师:提交日期:年月日.​ 系统简介:使用VHDL语言编写程序完成数字时钟的功能设计利用软件进行编译和仿真最后利用实验符等。

数字时钟班级:学号:姓名:指导老师:提交日期:年月日.​ 系统简介:使用VHDL语言编写程序完成数字时钟的功能设计利用软件进行编译和仿真最后利用实验箱实现系统。.​ 功能简介:完成时钟的计时、调整整点报时等基础功能完成闹钟的设置、开启和关闭功能整点报时的开启和关闭功能完成日期设定和显示功能。.​ 总体结构逻辑框图:.​ 状态图:.​ 各模块电路图及程序:整体电路连接图:​ 总控制模块:时钟脉冲分频元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcclkdmuxisport(clk:instdlogicclk,clk,clk:outstdlogic)enddcclkdmuxarchitectureclkdmuxofdcclkdmuxissignalc:stdlogicvector(downto)beginprocess(clk)beginifclk'eventandclk=''thenc<=cendifclk<=c()clk<=c()clk<=c()endprocessendclkdmux模式控制元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcmodeisport(clk,btm:instdlogicmode:outstdlogicvector(downto)cr,cr:outstdlogic)enddcmodearchitecturemodeofdcmodeissignalmodx:stdlogicvector(downto)signalc,c:stdlogicbeginprocess(clk,btm)beginifclk'eventandclk=''thenifbtm=''thenmodx<=modxc<=''elsec<=''endifendififmodx=""thenc<=''elsec<=''endifmode<=modxcr<=ccr<=cendprocessendmode调节项目控制元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcmodeisport(clk,btm:instdlogicmode:outstdlogicvector(downto)cr,cr:outstdlogic)enddcmodearchitecturemodeofdcmodeissignalmodx:stdlogicvector(downto)signalc,c:stdlogicbeginprocess(clk,btm)beginifclk'eventandclk=''thenifbtm=''thenmodx<=modxc<=''elsec<=''endifendififmodx=""thenc<=''elsec<=''endifmode<=modxcr<=ccr<=cendprocessendmode数码管显示元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcselisport(clk:instdlogicsel:outstdlogicvector(downto))enddcselarchitectureselofdcselissignalselx:stdlogicvector(downto)beginprocess(clk)beginifclk'eventandclk=''thenselx<=selxendifendprocesssel<=selxendsel模块波形图:​ 时钟模块:时钟秒调节元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcsecondisport(clk,clk,rest,bta:instdlogicmode,set:instdlogicvector(downto)sco,mcen:outstdlogicclks,clks:outstdlogicvector(downto))enddcsecondarchitecturesecondofdcsecondissignals,s:stdlogicvector(downto)signalco,rco,cr:stdlogicbeginprocess(clk,clk,rest,bta,mode,set)beginifclk'eventandclk=''thenifmode=""thenifrest=''thencr<=''elsifset=""andbta=''thencr<=''elsecr<=''endifendifendififcr=''thens<=""s<=""elsifclk'eventandclk=''thenifs=""ands=""thens<=""s<=""co<=''elsifs=""thens<=""s<=sco<=''elses<=sco<=''endifendififmode=""andset=""andbta=''thenrco<=clkmcen<=''elserco<=comcen<=''endifendprocessclks<=sclks<=ssco<=rcoendsecond时钟分调节元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcminiteisport(sco,mcen,clk,rest,bta:instdlogicmode,set:instdlogicvector(downto)mco,hcen:outstdlogicclkm,clkm:outstdlogicvector(downto))enddcminitearchitectureminiteofdcminiteissignalm,m:stdlogicvector(downto)signalrco,co,cr:stdlogicbeginprocess(sco,mcen,clk,rest,bta,mode,set)beginifmode=""andrest=''thencr<=restelsecr<=''endififcr=''thenm<=""m<=""elsifsco'eventandsco=''thenifm=""andm=""thenm<=""m<=""ifmcen=''thenco<=''elseco<=''endifelsifm=""thenm<=""m<=mco<=''elsem<=mco<=''endifendififmode=""andset=""andbta=''thenrco<=clkhcen<=''elserco<=cohcen<=''endifendprocessclkm<=mclkm<=mmco<=rcoendminite时钟小时调节元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydchourisport(mco,hcen,clk,rest,bta:instdlogicmode,set:instdlogicvector(downto)hco,dcen:outstdlogicclkh,clkh:outstdlogicvector(downto))enddchourarchitecturehourofdchourissignalh,h:stdlogicvector(downto)signalrco,co,cr:stdlogicbeginprocess(mco,hcen,clk,rest,bta,mode,set)beginifmode=""andrest=''thencr<=restelsecr<=''endififcr=''thenh<=""h<=""elsifmco'eventandmco=''thenifh=""andh=""thenh<=""h<=""ifhcen=''thenco<=''elseco<=''endifelsifh=""thenh<=""h<=hco<=''elseh<=hco<=''endifendififmode=""andset=""andbta=''thenrco<=clkdcen<=''elserco<=codcen<=''endifendprocessclkh<=hclkh<=hhco<=rcoendhour时钟模块波形图:​ 闹钟模块:闹钟分调节元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcalminiteisport(clk,bta:instdlogicmode,set:instdlogicvector(downto)alm,alm:outstdlogicvector(downto))enddcalminitearchitecturealarmofdcalminiteissignalm,m:stdlogicvector(downto)signalco:stdlogicbeginprocess(clk,bta,mode,set)beginifclk'eventandclk=''thenifmode=""andset=""andbta=''thenifm=""andm=""thenm<=""m<=""elsifm=""thenm<=""m<=melsem<=mendifendifendifendprocessalm<=malm<=mendalarm闹钟小时调节元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcalhourisport(clk,bta:instdlogicmode,set:instdlogicvector(downto)alh,alh:outstdlogicvector(downto))enddcalhourarchitecturealhourofdcalhourissignalh,h:stdlogicvector(downto)beginprocess(clk,bta,mode,set)beginifclk'eventandclk=''thenifmode=""andset=""andbta=''thenifh=""andh=""thenh<=""h<=""elsifh=""thenh<=""h<=helseh<=hendifendifendifendprocessalh<=halh<=hendalhour闹钟与时钟比较控制模块:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcalcontrolisport(clk,clk,clk:instdlogicalc:instdlogicvector(downto)clks,clks,clkm,clkm,clkh,clkh,alm,alm,alh,alh:instdlogicvector(downto)alarm:outstdlogic)enddcalcontrolarchitecturealcontrolofdcalcontrolissignalal,al,al:stdlogicbeginprocess(clk,clk,clk,clks,clks,clkm,clkm,clkh,clkh,alm,alm,alh,alh,alc)beginifclkm=""andclkm=""andclks=""thenifclks=""thenal<=clkelsifclks=""thenal<=clkelsifclks=""thenal<=clkelsifclks=""thenal<=clkelsifclks=""thenal<=clkelseal<=''endifelseal<=''endififclkm=almandclkm=almandclkh=alhandclkh=alhthenifclks=""andclk=''thenal<=clkelseal<=''endifelseal<=''endififalc=""thenal<=(aloral)elsifalc=""thenal<=alelsifalc=""thenal<=alelsifalc=""thenal<=''endifendprocessalarm<=alendalcontrol闹钟与时钟比较控制模块波形图:​ 日期模块日期日调整元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcdayisport(hco,dcen,clk,bta,sm,sm:instdlogicmode,set:instdlogicvector(downto)dco:outstdlogicday,day:outstdlogicvector(downto))enddcdayarchitecturedayofdcdayissignald,d:stdlogicvector(downto)signalrco,co:stdlogicbeginprocess(hco,dcen,clk,bta,mode,set)beginifhco'eventandhco=''thenifsm=''thenifd=""andd=""thend<=""d<=""ifdcen=''thenco<=''elseco<=''endifelsifd=""thend<=""d<=dco<=''elsed<=dco<=''endifelsifsm=''thenifd=""andd=""thend<=""d<=""ifdcen=''thenco<=''elseco<=''endifelsifd=""thend<=""d<=dco<=''elsed<=dco<=''endifelseifd=""andd=""thend<=""d<=""ifdcen=''thenco<=''elseco<=''endifelsifd=""thend<=""d<=dco<=''elsed<=dco<=''endifendifendififmode=""andset=""andbta=''thenrco<=clkelserco<=coendifendprocessday<=dday<=ddco<=rcoendday日期月调整元件:libraryieeeuseieeestdlogicalluseieeestdlogicunsignedallentitydcmonthisport(dco:instdlogicsm,sm:outstdlogicmon,mon:outstdlogicvector(downto))enddcmontharchitecturemonthofdcmonthissignalm,m:stdlogicvector(downto)signalmonth:stdlogicvector(downto)beginprocess(dco)beginifdco'eventanddco=''thenifm=""andm=""thenm<=""m<=""elsifm=""thenm<=""m<=melsem<=mendifendifmonth<=mmifmonth=""thensm<=''sm<=''elsifmonth=""ormonth=""ormonth=""ormonth=""thensm<=''sm<=''elsesm<=''sm<=''endifendprocessmon<=mmon<=mendmonth四(与附加四信号)选一选择器:libraryieeeuseieeestdlogicallentitydcmuxisport(m,m,h,h:instdlogicvector(downto)sel:instdlogicvector(downto)y:outstdlogicvector(downto))enddcmuxarchitecturemuxofdcmuxisbeginprocess(m,m,h,h,sel)begincaseseliswhen""=>y<=mwhen""=>y<=mwhen""=>y<=""when""=>y<=hwhen""=>y<=hwhenothers=>y<=""endcaseendprocessendmux日期模块波形图:​ 显示驱动模块数码管动态显示选择元件:libraryieeeuseieeestdlogicallentitydcchoiceisport(clk:instdlogicset:instdlogicvector(downto)sel:instdlogicvector(downto)g:outstdlogicvector(downto))enddcchoicearchitecturedriveofdcchoiceisbeginprocess(set,sel)beginifset=""andsel=""andclk=''theng<=""elsifset=""andsel=""andclk=''theng<=""elsifset=""andsel=""andclk=''theng<=""elsifset=""andsel=""andclk=''theng<=""elsifset=""andsel=""andclk=''theng<=""elsifset=""andsel=""andclk=''theng<=""elsecaseseliswhen""=>g<=""when""=>g<=""when""=>g<=""when""=>g<=""when""=>g<=""when""=>g<=""when""=>g<=""whenothers=>g<=""endcaseendifendprocessenddrive三选一多路数据选择器:libraryieeeuseieeestdlogicallentitydcmuxisport(clock,date,alarm:instdlogicvector(downto)mode:instdlogicvector(downto)y:outstdlogicvector(downto))enddcmuxarchitecturemuxofdcmuxisbeginprocess(clock,date,alarm,mode)begincasemodeiswhen""=>y<=clockwhen""=>y<=clockwhen""=>y<=alarmwhen""=>y<=datewhenothers=>y<=clockendcaseendprocessendmux七段译码器:libraryieeeuseieeestdlogicallentitydcdisplayisport(x:instdlogicvector(downto)segout:outstdlogicvector(downto))enddcdisplayarchitecturedisayofdcdisplayisbeginprocess(x)begincasexiswhen""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""when""=>segout<=""whenothers=>segout<=""endcaseendprocessenddisay.​ 心得体会这是一次数字逻辑的整体练兵本次课程设计是对VHDL数字逻辑电子设计技术的进一步掌握也是对MAXPLLUS设计工具应用的进一步了解。通过不断地优化算法更改错误关于数字逻辑与系统设计的知识在我脑中大大强化可以我从这次锻炼中获益匪浅。同时必须感谢老师和同学们的帮助让我顺利解决各个问题最终完成课题。

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