关闭

关闭

关闭

封号提示

内容

首页 JESD79-3E DDR3 Spec

JESD79-3E DDR3 Spec .pdf

JESD79-3E DDR3 Spec

luodax
2011-10-10 0人阅读 0 0 0 暂无简介 举报

简介:本文档为《JESD79-3E DDR3 Spec pdf》,可适用于IT/计算机领域

JEDECSOLIDSTATETECHNOLOGYASSOCIATIONJESDEJulyJEDECSTANDARDDDRSDRAMSpecification(RevisionofJESDD,August)NOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounselJEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationallyJEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocessesBysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublicationsTheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpointWithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandardNoclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremetInquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orcall()orwwwjedecorgPublishedby©JEDECSolidStateTechnologyAssociationNorththStreet,SuiteSouthArlington,VAThisdocumentmaybedownloadedfreeofchargehoweverJEDECretainsthecopyrightonthismaterialBydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterialPRICE:PleaserefertothecurrentCatalogofJEDECEngineeringStandardsandPublicationsonlineathttp:wwwjedecorgCatalogcatalogcfmPrintedintheUSAAllrightsreservedPLEASE!DON'TVIOLATETHELAW!ThisdocumentiscopyrightedbyJEDECandmaynotbereproducedwithoutpermissionOrganizationsmayobtainpermissiontoreproducealimitednumberofcopiesthroughenteringintoalicenseagreementForinformation,contact:JEDECSolidStateTechnologyAssociationNorththStreet,SuiteSouthArlington,Virginiaorcall()JEDECStandardNoEContentsScopeDDRSDRAMPackagePinoutandAddressingDDRSDRAMxBalloutusingMODDRSDRAMxBalloutusingMODDRSDRAMxBalloutusingMOStackeddualdieDDRSDRAMxBalloutusingMOStackeddualdieDDRSDRAMxBalloutusingMOStackeddualdieDDRSDRAMxBalloutusingMOQuadstackedQuaddieDDRSDRAMxBalloutusingMOQuadstackedQuaddieDDRSDRAMxBalloutusingMOQuadstackedQuaddieDDRSDRAMxBalloutusingMOPinoutDescriptionDDRSDRAMAddressingMbGbGbGbGbFunctionalDescriptionSimplifiedStateDiagramBasicFunctionalityRESETandInitializationProcedurePowerupInitializationSequenceResetInitializationwithStablePowerRegisterDefinitionProgrammingtheModeRegistersModeRegisterMRModeRegisterMRModeRegisterMRModeRegisterMRDDRSDRAMCommandDescriptionandOperationCommandTruthTableCKETruthTableNoOPeration(NOP)CommandDeselectCommandDLLoffModeDLLonoffswitchingprocedureDLL“on”toDLL“off”ProcedureDLL“off”toDLL“on”ProcedureInputclockfrequencychangeWriteLevelingDRAMsettingforwritelevelingDRAMterminationfunctioninthatmodeProcedureDescriptionWriteLevelingModeExitiJEDECStandardNoEContentsExtendedTemperatureUsageSelfRefreshTemperatureRangeSRTMultiPurposeRegisterMPRFunctionalDescriptionMPRRegisterAddressDefinitionRelevantTimingParametersProtocolExampleACTIVECommandPRECHARGECommandREADOperationREADBurstOperationREADTimingDefinitionsBurstReadOperationfollowedbyaPrechargeWRITEOperationDDRBurstOperationWRITETimingViolationsWriteDataMasktWPRECalculationtWPSTCalculationRefreshCommandSelfRefreshOperationPowerDownModesPowerDownEntryandExitPowerDownclarificationsCasePowerDownclarificationsCasePowerDownclarificationsCaseZQCalibrationCommandsZQCalibrationDescriptionZQCalibrationTimingZQExternalResistorValue,Tolerance,andCapacitiveloadingOnDieTermination(ODT)ODTModeRegisterandODTTruthTableSynchronousODTModeODTLatencyandPostedODTTimingParametersODTduringReadsDynamicODTFunctionalDescription:ODTTimingDiagramsAsynchronousODTModeSynchronoustoAsynchronousODTModeTransitionsSynchronoustoAsynchronousODTModeTransitionduringPowerDownEntryAsynchronoustoSynchronousODTModeTransitionduringPowerDownExitiiJEDECStandardNoEContentsAsynchronoustoSynchronousODTModeduringshortCKEhighandshortCKElowperiodsAbsoluteMaximumRatingsAbsoluteMaximumDCRatingsDRAMComponentOperatingTemperatureRangeACDCOperatingConditionsRecommendedDCOperatingConditionsACandDCInputMeasurementLevelsACandDCLogicInputLevelsforSingleEndedSignalsACandDCInputLevelsforSingleEndedCommandandAddressSignalsACandDCInputLevelsforSingleEndedDataSignalsVrefTolerancesACandDCLogicInputLevelsforDifferentialSignalsDifferentialsignaldefinitionDifferentialswingrequirementsforclock(CKCK#)andstrobe(DQSDQS#)SingleendedrequirementsfordifferentialsignalsDifferentialInputCrossPointVoltageSlewRateDefinitionsforSingleEndedInputSignalsSlewRateDefinitionsforDifferentialInputSignalsACandDCOutputMeasurementLevelsSingleEndedACandDCOutputLevelsDifferentialACandDCOutputLevelsSingleEndedOutputSlewRateDifferentialOutputSlewRateReferenceLoadforACTimingandOutputSlewRateOvershootandUndershootSpecificationsAddressandControlOvershootandUndershootSpecificationsClock,Data,StrobeandMaskOvershootandUndershootSpecificationsohmOutputDriverDCElectricalCharacteristicsOutputDriverTemperatureandVoltagesensitivityOnDieTermination(ODT)LevelsandIVCharacteristicsOnDieTermination(ODT)LevelsandIVCharacteristicsODTDCElectricalCharacteristicsODTTemperatureandVoltagesensitivityODTTimingDefinitionsTestLoadforODTTimingsODTTimingDefinitionsIDDandIDDQSpecificationParametersandTestConditionsIDDandIDDQMeasurementConditionsIDDSpecificationsInputOutputCapacitanceInputOutputCapacitanceiiiJEDECStandardNoEContentsElectricalCharacteristicsACTimingforDDRtoDDRClockSpecificationDefinitionfortCK(avg)DefinitionfortCK(abs)DefinitionfortCH(avg)andtCL(avg)DefinitionfortJIT(per)andtJIT(per,lck)DefinitionfortJIT(cc)andtJIT(cc,lck)DefinitionfortERR(nper)RefreshparametersbydevicedensityStandardSpeedBinsSpeedBinTableNotesElectricalCharacteristicsandACTimingTimingParametersforDDR,DDR,DDR,andDDRTimingParamtersforDDRandDDRSpeedBinsJitterNotesTimingParameterNotes

用户评价(0)

关闭

新课改视野下建构高中语文教学实验成果报告(32KB)

抱歉,积分不足下载失败,请稍后再试!

提示

试读已结束,如需要继续阅读或者下载,敬请购买!

评分:

/45

意见
反馈

立即扫码关注

爱问共享资料微信公众号

返回
顶部

举报
资料