JESD79-3E DDR3 Spec .pdf

JEDECSOLIDSTATETECHNOLOGYASSOCIATIONJESDEJulyJEDECSTANDARDDDRSDRAMSpecification(RevisionofJESDD,August)NOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounselJEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationallyJEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocessesBysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublicationsTheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpointWithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandardNoclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremetInquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orcall()orwwwjedecorgPublishedby©JEDECSolidStateTechnologyAssociationNorththStreet,SuiteSouthArlington,VAThisdocumentmaybedownloadedfreeofchargehoweverJEDECretainsthecopyrightonthismaterialBydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterialPRICE:PleaserefertothecurrentCatalogofJEDECEngineeringStandardsandPublicationsonlineathttp:wwwjedecorgCatalogcatalogcfmPrintedintheUSAAllrightsreservedPLEASE!DON'TVIOLATETHELAW!ThisdocumentiscopyrightedbyJEDECandmaynotbereproducedwithoutpermissionOrganizationsmayobtainpermissiontoreproducealimitednumberofcopiesthroughenteringintoalicenseagreementForinformation,contact:JEDECSolidStateTechnologyAssociationNorththStreet,SuiteSouthArlington,Virginiaorcall()JEDECStandardNoEContentsScopeDDRSDRAMPackagePinoutandAddressingDDRSDRAMxBalloutusingMODDRSDRAMxBalloutusingMODDRSDRAMxBalloutusingMOStackeddualdieDDRSDRAMxBalloutusingMOStackeddualdieDDRSDRAMxBalloutusingMOStackeddualdieDDRSDRAMxBalloutusingMOQuadstackedQuaddieDDRSDRAMxBalloutusingMOQuadstackedQuaddieDDRSDRAMxBalloutusingMOQuadstackedQuaddieDDRSDRAMxBalloutusingMOPinoutDescriptionDDRSDRAMAddressingMbGbGbGbGbFunctionalDescriptionSimplifiedStateDiagramBasicFunctionalityRESETandInitializationProcedurePowerupInitializationSequenceResetInitializationwithStablePowerRegisterDefinitionProgrammingtheModeRegistersModeRegisterMRModeRegisterMRModeRegisterMRModeRegisterMRDDRSDRAMCommandDescriptionandOperationCommandTruthTableCKETruthTableNoOPeration(NOP)CommandDeselectCommandDLLoffModeDLLonoffswitchingprocedureDLL“on”toDLL“off”ProcedureDLL“off”toDLL“on”ProcedureInputclockfrequencychangeWriteLevelingDRAMsettingforwritelevelingDRAMterminationfunctioninthatmodeProcedureDescriptionWriteLevelingModeExitiJEDECStandardNoEContentsExtendedTemperatureUsageSelfRefreshTemperatureRangeSRTMultiPurposeRegisterMPRFunctionalDescriptionMPRRegisterAddressDefinitionRelevantTimingParametersProtocolExampleACTIVECommandPRECHARGECommandREADOperationREADBurstOperationREADTimingDefinitionsBurstReadOperationfollowedbyaPrechargeWRITEOperationDDRBurstOperationWRITETimingViolationsWriteDataMasktWPRECalculationtWPSTCalculationRefreshCommandSelfRefreshOperationPowerDownModesPowerDownEntryandExitPowerDownclarificationsCasePowerDownclarificationsCasePowerDownclarificationsCaseZQCalibrationCommandsZQCalibrationDescriptionZQCalibrationTimingZQExternalResistorValue,Tolerance,andCapacitiveloadingOnDieTermination(ODT)ODTModeRegisterandODTTruthTableSynchronousODTModeODTLatencyandPostedODTTimingParametersODTduringReadsDynamicODTFunctionalDescription:ODTTimingDiagramsAsynchronousODTModeSynchronoustoAsynchronousODTModeTransitionsSynchronoustoAsynchronousODTModeTransitionduringPowerDownEntryAsynchronoustoSynchronousODTModeTransitionduringPowerDownExitiiJEDECStandardNoEContentsAsynchronoustoSynchronousODTModeduringshortCKEhighandshortCKElowperiodsAbsoluteMaximumRatingsAbsoluteMaximumDCRatingsDRAMComponentOperatingTemperatureRangeACDCOperatingConditionsRecommendedDCOperatingConditionsACandDCInputMeasurementLevelsACandDCLogicInputLevelsforSingleEndedSignalsACandDCInputLevelsforSingleEndedCommandandAddressSignalsACandDCInputLevelsforSingleEndedDataSignalsVrefTolerancesACandDCLogicInputLevelsforDifferentialSignalsDifferentialsignaldefinitionDifferentialswingrequirementsforclock(CKCK#)andstrobe(DQSDQS#)SingleendedrequirementsfordifferentialsignalsDifferentialInputCrossPointVoltageSlewRateDefinitionsforSingleEndedInputSignalsSlewRateDefinitionsforDifferentialInputSignalsACandDCOutputMeasurementLevelsSingleEndedACandDCOutputLevelsDifferentialACandDCOutputLevelsSingleEndedOutputSlewRateDifferentialOutputSlewRateReferenceLoadforACTimingandOutputSlewRateOvershootandUndershootSpecificationsAddressandControlOvershootandUndershootSpecificationsClock,Data,StrobeandMaskOvershootandUndershootSpecificationsohmOutputDriverDCElectricalCharacteristicsOutputDriverTemperatureandVoltagesensitivityOnDieTermination(ODT)LevelsandIVCharacteristicsOnDieTermination(ODT)LevelsandIVCharacteristicsODTDCElectricalCharacteristicsODTTemperatureandVoltagesensitivityODTTimingDefinitionsTestLoadforODTTimingsODTTimingDefinitionsIDDandIDDQSpecificationParametersandTestConditionsIDDandIDDQMeasurementConditionsIDDSpecificationsInputOutputCapacitanceInputOutputCapacitanceiiiJEDECStandardNoEContentsElectricalCharacteristicsACTimingforDDRtoDDRClockSpecificationDefinitionfortCK(avg)DefinitionfortCK(abs)DefinitionfortCH(avg)andtCL(avg)DefinitionfortJIT(per)andtJIT(per,lck)DefinitionfortJIT(cc)andtJIT(cc,lck)DefinitionfortERR(nper)RefreshparametersbydevicedensityStandardSpeedBinsSpeedBinTableNotesElectricalCharacteristicsandACTimingTimingParametersforDDR,DDR,DDR,andDDRTimingParamtersforDDRandDDRSpeedBinsJitterNotesTimingParameterNotes