现代内存条技术参数HY5DU56822AT-H

HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T 256M-S DDR SDRAM HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 查询供应商 Rev. 0.4/ May. 02 2 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (Jan. 02) 1) Define Preliminary Specification 2. Revision 0.3 (Mar. 02) 1) Define IDD Specification 2) Added programmable Cas Latrency 1.5 3) Changed VREF value from min (0.49*VDDQ) & max (0.51*VDDQ) to min (VDDQ/2-50mV) & max (VDDQ/2+50mV) 4) Changed ILI (Input Leakage Current) value from +/- 5uA to +/- 2uA 3. Revision 0.4 (May. 02) 1) Added comment of Cas Latrency 1.5 & 3 DESCRIPTION The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Syn- chronous DRAM, ideally suited for the main memory applications which requires large memory density and high band- width. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES PRELIMINARY Rev. 0.4 / May. 02 3 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T • VDD, VDDQ = 2.5V +/- 0.2V • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous - data transaction aligned to bidirectional data strobe (DQS) • x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O • Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) • On chip DLL align DQ and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 1.5, 2, 2.5 and 3 supported • Programmable burst length 2 / 4 / 8 with both sequential and interleave mode • Internal four bank operations with single pulsed /RAS • tRAS Lock-out function supported • Auto refresh and Self refresh supported • 8192 refresh cycles / 64ms • JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch • Full and Half strength driver option controlled by EMRS ORDERING INFORMATION * X means speed grade Part No. Configuration Package HY5DU56422A(L)T-X* 64Mx4 400mil 66pin TSOP-II HY5DU56822A(L)T-X* 32Mx8 HY5DU561622A(L)T-X* 16Mx16 OPERATING FREQUENCY Grade CL2 CL2.5 Remark(CL-tRCD-tRP) - J 133MHz 166MHz DDR333 (2.5-3-3) - M 133MHz 133MHz DDR266 (2-2-2) - K 133MHz 133MHz DDR266A (2-3-3) - H 100MHz 133MHz DDR266B (2.5-3-3) - L 100MHz 125MHz DDR200 (2-2-2) * CL1.5 @ DDR200 supported * CL3 supported Rev. 0.4/ May. 02 4 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T PIN CONFIGURATION ROW AND COLUMN ADDRESS TABLE ITEMS 64Mx4 32Mx8 16Mx16 Organization 16M x 4 x 4banks 8M x 8 x 4banks 4M x 16 x 4banks Row Address A0 - A12 A0 - A12 A0 - A12 Column Address A0-A9, A11 A0-A9 A0-A8 Bank Address BA0, BA1 BA0, BA1 BA0, BA1 Auto Precharge Flag A10 A10 A10 Refresh 8K 8K 8K 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD DNU LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD DNU NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x16 x8 x4x4 x8 x16 400mil X 875mil 66pin TSOP -II 0.65mm pin pitch Rev. 0.4/ May. 02 5 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T PIN DESCRIPTION PIN TYPE DESCRIPTION CK, /CK Input Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. /CS Input Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com- mands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE- CHARGE command is being applied. A0 ~ A12 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). /RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. DM (LDM, UDM) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre- sponds to the data on DQ8-Q15. DQS (LDQS, UDQS) I/O Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. DQ I/O Data input / output pin : Data bus VDD/VSS Supply Power supply for internal circuits and input buffers. VDDQ/VSSQ Supply Power supply for output buffers for noise immunity. VREF Supply Reference voltage for inputs for SSTL interface. NC NC No connection. Rev. 0.4/ May. 02 6 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Command Decoder CLK /CLK CKE /CS /RAS /CAS /WE Address Buffer ADD Bank Control 16Mx4 / Bank0 Column Decoder Column Address Counter Sense AM P 2-bit Prefetch Unit 16Mx4 / Bank1 16Mx4 / Bank2 16Mx4 / Bank3 Mode Register Row Decoder Input Buffer Output Buffer Data Strobe Transmitter Data Strobe Receiver DQS DQS Write Data Register 2-bit Prefetch Unit DQS DQ[0:3] 8 4 4 8 BA DLL Block CLK_DLL CLK, /CLK Mode Register DM FUNCTIONAL BLOCK DIAGRAM (64Mx4) 4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM Rev. 0.4/ May. 02 7 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Command Decoder CLK /CLK CKE /CS /RAS /CAS /WE Address Buffer ADD Bank Control 8Mx8 / Bank0 Column Decoder Column Address Counter Sense AM P 2-bit Prefetch Unit 8Mx8 / Bank1 8Mx8 / Bank2 8Mx8 / Bank3 Mode Register Row Decoder Input Buffer Output Buffer Data Strobe Transmitter Data Strobe Receiver DQS DQS Write Data Register 2-bit Prefetch Unit DQS DQ[0:7] 16 8 8 16 BA DLL Block CLK_DLL CLK, /CLK Mode Register DM FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM Rev. 0.4/ May. 02 8 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Command Decoder CLK /CLK CKE /CS /RAS /CAS /WE Address Buffer ADD Bank Control 4Mx16 / Bank0 Column Decoder Column Address Counter Sense AM P 2-bit Prefetch Unit 4Mx16 / Bank1 4Mx16 / Bank2 4Mx16 / Bank3 Mode Register Row Decoder Input Buffer Output Buffer Data Strobe Transmitter Data Strobe Receiver LDQS, UDQS LDQS UDQS Write Data Register 2-bit Prefetch Unit LDQS, UDQS DQ[0:15] 32 16 16 32 BA DLL Block CLK_DLL CLK, /CLK Mode Register LDM, UDM FUNCTIONAL BLOCK DIAGRAM (16Mx16) 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM Rev. 0.4/ May. 02 9 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE ADDR A10/AP BA Note Extended Mode Register Set H X L L L L OP code 1,2 Mode Register Set H X L L L L OP code 1,2 Device Deselect H X H X X X X 1 No Operation L H H H Bank Active H X L L H H RA V 1 Read H X L H L H CA L V 1 Read with Autoprecharge H 1,3 Write H X L H L L CA L V 1 Write with Autoprecharge H 1,4 Precharge All Banks H X L L H L X H X 1,5 Precharge selected Bank L V 1 Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Self Refresh Entry H L L L L H X 1 Exit L H H X X X 1 L H H H Precharge Power Down Mode Entry H L H X X X X 1 L H H H 1 Exit L H H X X X 1 L H H H 1 Active Power Down Mode Entry H L H X X X X 1 L V V V 1 Exit L H X 1 Note : 1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Rev. 0.4/ May. 02 10 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T WRITE MASK TRUTH TABLE Function CKEn-1 CKEn /CS, /RAS, /CAS, /WE DM ADDR A10/ AP BA Note Data Write H X X L X 1 Data-In Mask H X X H X 1 Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.4/ May. 02 11 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T OPERATION COMMAND TRUTH TABLE-I Current State /CS /RAS /CAS /WE Address Command Action IDLE H X X X X DSEL NOP or power down3 L H H H X NOP NOP or power down3 L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP ILLEGAL4 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4 L L H H BA, RA ACT Row Activation L L H L BA, AP PRE/PALL NOP L L L H X AREF/SREF Auto Refresh or Self Refresh5 L L L L OPCODE MRS Mode Register Set ROW ACTIVE H X X X X DSEL NOP L H H H X NOP NOP L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP Begin read : optional AP6 L H L L BA, CA, AP WRITE/WRITEAP Begin write : optional AP6 L L H H BA, RA ACT ILLEGAL4 L L H L BA, AP PRE/PALL Precharge7 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 READ H X X X X DSEL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Terminate burst L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL L L H H BA, RA ACT ILLEGAL4 L L H L BA, AP PRE/PALL Term burst, precharge L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 WRITE H X X X X DSEL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8 L H L L BA, CA, AP WRITE/WRITEAP Term burst, new write:optional AP Rev. 0.4/ May. 02 12 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T OPERATION COMMAND TRUTH TABLE-II Current State /CS /RAS /CAS /WE Address Command Action WRITE L L H H BA, RA ACT ILLEGAL4 L L H L BA, AP PRE/PALL Term burst, precharge L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 READ WITH AUTOPRE- CHARGE H X X X X DSEL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BA, CA, AP READ/READAP ILLEGAL10 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10 L L H H BA, RA ACT ILLEGAL4,10 L L H L BA, AP PRE/PALL ILLEGAL4,10 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 WRITE AUTOPRE- CHARGE H X X X X DSEL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BA, CA, AP READ/READAP ILLEGAL10 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10 L L H H BA, RA ACT ILLEGAL4,10 L L H L BA, AP PRE/PALL ILLEGAL4,10 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 PRE- CHARGE H X X X X DSEL NOP-Enter IDLE after tRP L H H H X NOP NOP-Enter IDLE after tRP L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP ILLEGAL4,10 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10 L L H H BA, RA ACT ILLEGAL4,10 L L H L BA, AP PRE/PALL NOP-Enter IDLE after tRP L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 Rev. 0.4/ May. 02 13 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T OPERATION COMMAND TRUTH TABLE-III Current State /CS /RAS /CAS /WE Address Command Action ROW ACTIVATING H X X X X DSEL NOP - Enter ROW ACT after tRCD L H H H X NOP NOP - Enter ROW ACT after tRCD L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP ILLEGAL4,10 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10 L L H H BA, RA ACT ILLEGAL4,9,10 L L H L BA, AP PRE/PALL ILLEGAL4,10 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 WRITE RECOVERING H X X X X DSEL NOP - Enter ROW ACT after tWR L H H H X NOP NOP - Enter ROW ACT after tWR L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP ILLEGAL L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL L L H H BA, RA ACT ILLEGAL4,10 L L H L BA, AP PRE/PALL ILLEGAL4,11 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 WRITE RECOVERING WITH AUTOPRE- CHARGE H X X X X DSEL NOP - Enter precharge after tDPL L H H H X NOP NOP - Enter precharge after tDPL L H H L X BST ILLEGAL4 L H L H BA, CA, AP READ/READAP ILLEGAL4,8,10 L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10 L L H H BA, RA ACT ILLEGAL4,10 L L H L BA, AP PRE/PALL ILLEGAL4,11 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 REFRESHING H X X X X DSEL NOP - Enter IDLE after tRC L H H H X NOP NOP - Enter IDLE after tRC L H H L X BST ILLEGAL11 L H L H BA, CA, AP READ/READAP ILLEGAL11 Rev. 0.4/ May. 02 14 HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T OPERATION COMMAND TRUTH TABLE-IV Note : 1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation. 2. All entries assume that CKE was active(high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive(low level), then in power down mode. 4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. 5. If both banks are idle and CKE is inactive(low level), then self refresh mode. 6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Illegal if tRRD is not met. 10. Illegal for single bank, but legal for other banks in multi-bank devices. 11. Illegal for all banks. Current State /CS /RAS /CAS /WE Address Command Action WRITE L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11 L L H H BA, RA ACT ILLEGAL11 L L H L BA, AP PRE/PALL ILLEGAL11 L L L H X AREF/SREF ILLEGAL11 L L L L OPCODE MRS ILLEGAL11 MODE REGISTER ACCESSING H X X X X DSEL NOP - Enter IDLE after tMRD L H H H X NOP NOP - Enter IDLE after tMRD L H