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CD4060BC.pdf

CD4060BC.pdf

上传者: zhuwild 2011-09-13 评分1 评论0 下载107 收藏0 阅读量925 暂无简介 简介 举报

简介:本文档为《CD4060BCpdf》,可适用于电信技术领域,主题内容包含OctoberRevisedJanuaryCDBC•CDBC•CDBCStageRippleCarryBinaryCounters•StageRip符等。

OctoberRevisedJanuaryCDBC•CDBC•CDBCStageRippleCarryBinaryCounters•StageRippleCarryBinaryCounters•StageRippleCarryBinaryCountersFairchildSemiconductorCorporationDSprfwwwfairchildsemicomCDBC•CDBC•CDBCStageRippleCarryBinaryCounters•StageRippleCarryBinaryCounters•StageRippleCarryBinaryCountersGeneralDescriptionTheCDBC,CDBCarestageripplecarrybinarycounters,andtheCDBCisastageripplecarrybinarycounterThecountersareadvancedonecountonthenegativetransitionofeachclockpulseThecountersareresettothezerostatebyalogical“”attheresetinputindependentofclockFeaturesnWidesupplyvoltagerange:VtoVnHighnoiseimmunity:VDD(typ)nLowpowerTTLcompatibility:FanoutofdrivingLordrivingLSnMediumspeedoperation:MHztypatVDD=VnSchmitttriggerclockinputOrderingCode:DevicesalsoavailableinTapeandReelSpecifybyappendingthesuffixletter“X”totheorderingcodeConnectionDiagramsPinAssignmentsforDIPandSOICCDBCTopViewPinAssignmentsforDIP,SOICandSOPCDBCTopViewOrderNumberPackageNumberPackageDescriptionCDBCMMALeadSmallOutlineIntegratedCircuit(SOIC),JEDECMS,”NarrowCDBCNNELeadPlasticDualInLinePackage(PDIP),JEDECMS,”WideCDBCMMALeadSmallOutlineIntegratedCircuit(SOIC),JEDECMS,”NarrowCDBCSJMDLeadSmallOutlinePackage(SOP),EIAJTYPEII,mmWideCDBCNNELeadPlasticDualInLinePackage(PDIP),JEDECMS,”WideCDBCMMALeadSmallOutlineIntegratedCircuit(SOIC),JEDECMS,”NarrowCDBCNNELeadPlasticDualInLinePackage(PDIP),JEDECMS,”WidewwwfairchildsemicomCDBC•CDBC•CDBCConnectionDiagrams(Continued)PinAssignmentsforDIPandSOICCDBCTopViewSchematicDiagramsCDBCCDBCwwwfairchildsemicomCDBC•CDBC•CDBCCDBCCDBTypicalOscillatorConnectionsRCOscillatorCrystalOscillatorwwwfairchildsemicomCDBC•CDBC•CDBCAbsoluteMaximumRatings(Note)(Note)RecommendedOperatingConditionsNote:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteedTheyarenotmeanttoimplythatthedevicesshouldbeoperatedattheselimitsThetablesof“RecommendedOperatingConditions”and“ElectricalCharacteristics”provideconditionsforactualdeviceoperationNote:VSS=VunlessotherwisespecifiedDCElectricalCharacteristics(Note)Note:DatadoesnotapplytooscillatorpointsφandφofCDBCIOHandIOLaretestedoneoutputatatimeSupplyVoltage(VDD)VtoVInputVoltage(VIN)VtoVDDVStorageTemperatureRange(TS)CtoCPackageDissipation(PD)DualInLinemWSmallOutlinemWLeadTemperature(TL)(Soldering,seconds)CSupplyVoltage(VDD)VtoVInputVoltage(VIN)VtoVDDOperatingTemperatureRange(TA)CtoCSymbolParameterConditionsCCCUnitsMinMaxMinTypMaxMinMaxIDDQuiescentDeviceCurrentVDD=V,VIN=VDDorVSSµAVDD=V,VIN=VDDorVSSµAVDD=V,VIN=VDDorVSSµAVOLLOWLevelOutputVoltageVDD=VVVDD=VVVDD=VVVOHHIGHLevelOutputVoltageVDD=VVVDD=VVVDD=VVVILLOWLevelInputVoltageVDD=V,VO=VorVVVDD=V,VO=VorVVVDD=V,VO=VorVVVIHHIGHLevelInputVoltageVDD=V,VO=VorVVVDD=V,VO=VorVVVDD=V,VO=VorVVIOLLOWLevelOutputCurrentVDD=V,VO=VmA(Note)VDD=V,VO=VmAVDD=V,VO=VmAIOHHIGHLevelOutputCurrentVDD=V,VO=VmA(Note)VDD=V,VO=VmAVDD=V,VO=VmAIINInputCurrentVDD=V,VIN=VµAVDD=V,VIN=VµAwwwfairchildsemicomCDBC•CDBC•CDBCACElectricalCharacteristics(Note)CDBC,CDBCTA=C,CL=pF,RL=k,tr=tf=ns,unlessotherwisenotedNote:ACParametersareguaranteedbyDCcorrelatedtestingSymbolParameterConditionsMinTypMaxUnitstPHL,tPLHPropagationDelayTimetoQVDD=VnsVDD=VnsVDD=VnstPHL,tPLHInterstagePropagationDelayTimeVDD=VnsfromQntoQnVDD=VnsVDD=VnstTHL,tTLHTransitionTimeVDD=VnsVDD=VnsVDD=VnstWL,tWHMinimumClockPulseWidthVDD=VnsVDD=VnsVDD=VnstrCL,tfCLMaximumClockRiseandFallTimeVDD=VNoLimitnsVDD=VNoLimitnsVDD=VNoLimitnsfCLMaximumClockFrequencyVDD=VMHzVDD=VMHzVDD=VMHztPHL(R)ResetPropagationDelayVDD=VnsVDD=VnsVDD=VnstWH(R)MinimumResetPulseWidthVDD=VnsVDD=VnsVDD=VnsCINAverageInputCapacitanceAnyInputpFCPDPowerDissipationCapacitancepFwwwfairchildsemicomCDBC•CDBC•CDBCACElectricalCharacteristics(Note)CDBCTA=C,CL=pF,RL=k,tr=tf=ns,unlessotherwisenotedNote:ACParametersareguaranteedbyDCcorrelatedtestingSymbolParameterConditionsMinTypMaxUnitstPHL,tPLHPropagationDelayTimetoQVDD=VnsVDD=VnsVDD=VnstPHL,tPLHInterstagePropagationDelayTimeVDD=VnsfromQntoQnVDD=VnsVDD=VnstTHL,tTLHTransitionTimeVDD=VnsVDD=VnsVDD=VnstWL,tWHMinimumClockPulseWidthVDD=VnsVDD=VnsVDD=VnstrCL,tfCLMaximumClockRiseandFallTimeVDD=VNoLimitnsVDD=VNoLimitnsVDD=VNoLimitnsfCLMaximumClockFrequencyVDD=VMHzVDD=VMHzVDD=VMHztPHL(R)ResetPropagationDelayVDD=VnsVDD=VnsVDD=VnstWH(R)MinimumResetPulseWidthVDD=VnsVDD=VnsVDD=VnsCINAverageInputCapacitanceAnyInputpFCPDPowerDissipationCapacitancepFwwwfairchildsemicomCDBC•CDBC•CDBCPhysicalDimensionsinches(millimeters)unlessotherwisenotedLeadSmallOutlineIntegratedCircuit(SOIC),JEDECMS,”NarrowPackageNumberMALeadSmallOutlinePackage(SOP),EIAJTYPEII,mmWidePackageNumberMDFairchilddoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandFairchildreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecificationsCDBC•CDBC•CDBCStageRippleCarryBinaryCounters•StageRippleCarryBinaryCounters•StageRippleCarryBinaryCountersLIFESUPPORTPOLICYFAIRCHILD’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTOFFAIRCHILDSEMICONDUCTORCORPORATIONAsusedherein:Lifesupportdevicesorsystemsaredevicesorsystemswhich,(a)areintendedforsurgicalimplantintothebody,or(b)supportorsustainlife,and(c)whosefailuretoperformwhenproperlyusedinaccordancewithinstructionsforuseprovidedinthelabeling,canbereasonablyexpectedtoresultinasignificantinjurytotheuserAcriticalcomponentinanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailureofthelifesupportdeviceorsystem,ortoaffectitssafetyoreffectivenesswwwfairchildsemicomPhysicalDimensionsinches(millimeters)unlessotherwisenoted(Continued)LeadPlasticDualInLinePackage(PDIP),JEDECMS,”WidePackageNumberNE

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