TLC2543_DataSheet

TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 � 12-Bit-Resolution A/D Converter � 10-µs Conversion Time Over Operating Temperature � 11 Analog Input Channels � 3 Built-In Self-Test Modes � Inherent Sample-and-Hold Function � Linearity Error . . . ±1 LSB Max � On-Chip System Clock � End-of-Conversion Output � Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2 the Applied Voltage Reference) � Programmable MSB or LSB First � Programmable Power Down � Programmable Output Data Length � CMOS Technology � Application Report Available† description The TLC2543C and TLC2543I are 12-bit, switched- capacitor, successive-approximation, analog-to- digital converters. Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK), and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host. In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range. The TLC2543C is characterized for operation from TA = 0°C to 70°C. The TLC2543I is characterized for operation from TA = –40°C to 85°C. The TLC2543M is characterized for operation from TA = –55°C to 125°C. Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF+ REF– AIN10 AIN9 (TOP VIEW) DB, DW, J, OR N PACKAGE 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 I/O CLOCK DATA INPUT DATA OUT CS AIN3 AIN4 AIN5 AIN6 AIN7 FK OR FN PACKAGE (TOP VIEW) AI N 1 AI N 0 AI N 10 R EF – AI N 2 EO C AI N 8 G ND AI N 9 V C C REF+ TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE PLASTIC CHIP CARRIER PLASTIC CHIP CARRIER PLASTIC DIP PLASTIC DIP (DB)† (DW)† (FK) (FN)† (J) (N) 0°C to 70°C TLC2543CDB TLC2543CDW — TLC2543CFN — TLC2543CN –40°C to 85°C — TLC2543IDW — TLC2543IFN — TLC2543IN –55°C to 125°C — — TLC2543MFK — TLC2543MJ — † Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or TLC2543IFNR. functional block diagram 14-Channel Analog Multiplexer Sample-and- Hold Function 12-Bit Analog-to-Digital Converter (Switched Capacitors) Self-Test Reference Output Data Register 12-to-1 Data Selector and Driver Control Logic and I/O Counters Input Address Register 4 12 12 4 REF+ REF– DATA OUT DATA INPUT I/O CLOCK CS 3 EOC17 18 15 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 2 3 4 5 6 7 8 9 11 12 14 13 16 19 TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AIN0 – AIN10 1–9, 11, 12 I Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input voltage into a capacitance of 60 pF. CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. DATA INPUT 17 I Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. DATA OUT 16 O The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB† value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order. EOC 19 O End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer. GND 10 Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I/O CLOCK 18 I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of the I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. REF+ 14 I Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF– terminal. REF– 13 I Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. VCC 20 Positive supply voltage † MSB/LSB = Most significant bit /least significant bit TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, VO –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Positive reference voltage, Vref+ VCC + 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Negative reference voltage, Vref– –0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak input current, II (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak total input current, II (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: TLC2543C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC2543I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC2543M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted). recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 5 5.5 V Positive reference voltage, Vref+ (see Note 2) VCC V Negative reference voltage, Vref– (see Note 2) 0 V Differential reference voltage, Vref+ – Vref– (see Note 2) 2.5 VCC VCC+0.1 V Analog input voltage (see Note 2) 0 VCC V High-level control input voltage, VIH VCC = 4.5 V to 5.5 V 2 V Low-level control input voltage, VIL VCC = 4.5 V to 5.5 V 0.8 V Clock frequency at I/O CLOCK 0 4.1 MHz Setup time, address bits at DATA INPUT before I/O CLOCK↑, tsu(A) (see Figure 4) 100 ns Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4) 0 ns Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5) 0 ns Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5) 1.425 µs Pulse duration, I/O CLOCK high, twH(I/O) 120 ns Pulse duration, I/O CLOCK low, twL(I/O) 120 ns Transition time, I/O CLOCK high to low, tt(I/O) (see Note 4 and Figure 6) 1 µs Transition time, DATA INPUT and CS, tt(CS) 10 µs TLC2543C 0 70 Operating free-air temperature, TA TLC2543I –40 85 °C TLC2543M –55 125 NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF– convert as all zeros (000000000000). 3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS TLC2543C, TLC2543I UNITPARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High level output voltage VCC = 4.5 V, IOH = –1.6 mA 2.4 VVOH High-level output voltage VCC = 4.5 V to 5.5 V, IOH = –20 µA VCC–0.1 V VOL Low level output voltage VCC = 4.5 V, IOL = 1.6 mA 0.4 VVOL Low-level output voltage VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1 V IOZ High-impedance off-state output VO = VCC, CS at VCC 1 2.5 µAIOZ g current VO = 0, CS at VCC 1 –2.5 µA IIH High-level input current VI = VCC 1 2.5 µA IIL Low-level input current VI = 0 1 –2.5 µA ICC Operating supply current CS at 0 V 1 2.5 mA ICC(PD) Power-down current For all digital inputs,0 ≤ VI ≤ 0.5 V or VI ≥ VCC – 0.5 V 4 25 µA Selected channel leakage Selected channel at VCC, Unselected channel at 0 V 1Selected channel leakage current Selected channel at 0 V, Unselected channel at VCC –1 µA Maximum static analog reference current into REF+ Vref+ = VCC, Vref– = GND 1 2.5 µA Ci Input Analog inputs 30 60 pFCi capacitance Control inputs 5 15 pF † All typical values are at VCC = 5 V, TA = 25°C. electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS TLC2543M UNITPARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High level output voltage VCC = 4.5 V, IOH = –1.6 mA 2.4 VVOH High-level output voltage VCC = 4.5 V to 5.5 V, IOH = –20 µA VCC–0.1 V VOL Low level output voltage VCC = 4.5 V, IOL = 1.6 mA 0.4 VVOL Low-level output voltage VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1 V IOZ High-impedance off-state output VO = VCC, CS at VCC 1 2.5 µAIOZ g current VO = 0, CS at VCC 1 –2.5 µA IIH High-level input current VI = VCC 1 10 µA IIL Low-level input current VI = 0 1 –10 µA ICC Operating supply current CS at 0 V 1 10 mA ICC(PD) Power-down current For all digital inputs,0 ≤ VI ≤ 0.5 V or VI ≥ VCC – 0.5 V 4 25 µA Selected channel leakage Selected channel at VCC, Unselected channel at 0 V 10Selected channel leakage current Selected channel at 0 V, Unselected channel at VCC –10 µA Maximum static analog reference current into REF+ Vref+ = VCC, Vref– = GND 1 2.5 µA Ci Input Analog inputs 30 60 pFCi capacitance Control inputs 5 15 pF † All typical values are at VCC = 5 V, TA = 25°C. TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT EL Linearity error (see Note 5) See Figure 2 ±1 LSB ED Differential linearity error See Figure 2 ±1 LSB EO Offset error (see Note 6) See Note 2 and Figure 2 ±1.5 LSB EG Gain error (see Note 6) See Note 2 and Figure 2 ±1 LSB ET Total unadjusted error (see Note 7) ±1.75 LSB DATA INPUT = 1011 2048 Self-test output code (see Table 3 and Note 8) DATA INPUT = 1100 0 DATA INPUT = 1101 4095 tconv Conversion time See Figures 9–14 8 10 µs tc Total cycle time (access, sample, and conversion) See Figures 9–14and Note 9 10 + total I/O CLOCK periods + td(I/O-EOC) µs tacq Channel acquisition time (sample) See Figures 9–14and Note 9 4 12 I/O CLOCK periods tv Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6 10 ns td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 150 ns td(I/O-EOC) Delay time, last I/O CLOCK↓ to EOC↓ See Figure 7 1.5 2.2 µs td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB/LSB) See Figure 8 100 ns tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB/LSB driven) See Figure 3 0.7 1.3 µs tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 70 150 ns tr(EOC) Rise time, EOC See Figure 8 15 50 ns tf(EOC) Fall time, EOC See Figure 7 15 50 ns tr(bus) Rise time, data bus See Figure 6 15 50 ns tf(bus) Fall time, data bus See Figure 6 15 50 ns td(I/O-CS) Delay time, last I/O CLOCK↓ to CS↓ to abort conversion(see Note 10) 5 µs † All typical values are at TA = 25°C. NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF– convert as all zeros (000000000000). 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point. 7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. 9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7). 10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether the conversion is aborted or the conversion results are valid. TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION _ + C2 0.1 µF C1 10 µF C3 470 pF 50 Ω 15 V 50 Ω –15 V VI AIN0–AIN10 TLC2543 10 Ω U1 C1 10 µF C3 470 pF C2 0.1 µF LOCATION U1 C1 C2 C3 DESCRIPTION OP27 10-µF 35-V tantalum capacitor 0.1-µF ceramic NPO SMD capacitor 470-pF porcelain Hi-Q SMD capacitor PART NUMBER — — AVX 12105C104KA105 or equivalent Johanson 201S420471JG4L or equivalent Figure 1. Analog Input Buffer to Analog Inputs AIN0–AIN10 EOC CL = 50 pF 12 kΩ DATA OUT Test Point VCC RL = 2.18 kΩ CL = 100 pF 12 kΩ Test Point VCC RL = 2.18 kΩ Figure 2. Load Circuits CS DATA OUT 2.4 V 0.4 V 90% 10% tPZH, tPZL tPHZ, tPLZ 0.8 V 2 V Figure 3. DATA OUT to Hi-Z Voltage Waveforms DATA INPUT th(A) 0.8 V 2 V I/O CLOCK Data Valid tsu(A) 0.8 V Figure 4. DATA INPUT and I/O CLOCK Voltage Waveforms TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION Last Clock CS 0.8 V 2 V 0.8 V tsu(CS) 0.8 V I/O CLOCK th(CS) NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing. Figure 5. CS and I/O CLOCK Voltage Waveforms 0.4 V 2.4 V 0.4 V 2.4 V 2 V 0.8 VI/O CLOCK DATA OUT tt(I/O) 0.8 V 2 V tr(bus), tf(bus) td(I/O-DATA) tv tt(I/O) 0.8 V I/O CLOCK Period Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms Last Clock 0.8 V 2.4 V 0.4 V tf(EOC) td(I/O-EOC) I/O CLOCK EOC Figure 7. I/O CLOCK and EOC Voltage Waveforms 0.4 V 2.4 V EOC td(EOC-DATA) Valid MSB DATA OUT 0.4 V 2.4 V tr(EOC) Figure 8. EOC and DATA OUT Voltage Waveforms TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079D – DECEMBER 1993 – REVISED MAY 1997 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Access Cycle B Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Sample Cycle B A/D Conversion Interval InitializeInitialize MSB LSB Previous Conversion Data MSB LSB B7 B6 B5 B4 C7 B11A11 A10 A9 A8 A7 A6 A5 A4 A1 A0 Hi-Z State 1 2 3 4 5 6 7 8 11 12 1I/O CLOC