TLC5615CP

TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 � 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package � 5-V Single Supply Operation � 3-Wire Serial Interface � High-Impedance Reference Inputs � Voltage Output Range . . . 2 Times the Reference Input Voltage � Internal Power-On Reset � Low Power Consumption . . . 1.75 mW Max � Update Rate of 1.21 MHz � Settling Time to 0.5 LSB . . . 12.5 m s Typ � Monotonic Over Temperature � Pin Compatible With the Maxim MAX515 applications � Battery-Powered Test Instruments � Digital Offset and Gain Adjustment � Battery Operated/Remote Industrial Controls � Machine and Motion Control Devices � Cellular Telephones description The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards. The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation from –40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE† (D) PLASTIC SMALL OUTLINE (DGK) PLASTIC DIP (P) 0°C to 70°C TLC5615CD TLC5615CDGK TLC5615CP –40°C to 85°C TLC5615ID TLC5615IDGK TLC5615IP † Available in tape and reel as the TLC5615CDR and the TLC5615IDR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2000, Texas Instruments Incorporated 1 2 3 4 8 7 6 5 DIN SCLK CS DOUT VDD OUT REFIN AGND D, P, OR DGK PACKAGE (TOP VIEW) SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram _ +DAC 10-Bit DAC Register Power-ON Reset Control Logic 16-Bit Shift Register 4 Dummy Bits 2 0s 10 Data Bits (LSB) (MSB) REFIN AGND CS SCLK DIN OUT (Voltage Output) _ + DOUT R R �2 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION DIN 1 I Serial data input SCLK 2 I Serial clock input CS 3 I Chip select, active low DOUT 4 O Serial data output for daisy chaining AGND 5 Analog ground REFIN 6 I Reference input OUT 7 O DAC analog voltage output VDD 8 Positive power supply absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage at OUT from external source VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current at any terminal ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: TLC5615C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC5615I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 4.5 5 5.5 V High-level digital input voltage, VIH 2.4 V Low-level digital input voltage, VIL 0.8 V Reference voltage, Vref to REFIN terminal 2 2.048 VDD–2 V Load resistance, RL 2 k W Operating free air temperature TA TLC5615C 0 70 °C Operating free-air temperature, TA TLC5615I –40 85 °C electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2.048 V (unless otherwise noted) static DAC specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 10 bits Integral nonlinearity, end point adjusted (INL) Vref = 2.048 V, See Note 1 ±1 LSB Differential nonlinearity (DNL) Vref = 2.048 V, See Note 2 ±0.1 ± 0.5 LSB EZS Zero-scale error (offset error at zero scale) Vref = 2.048 V, See Note 3 ±3 LSB Zero-scale-error temperature coefficient Vref = 2.048 V, See Note 4 3 ppm/°C EG Gain error Vref = 2.048 V, See Note 5 ±3 LSB Gain-error temperature coefficient Vref = 2.048 V, See Note 6 1 ppm/°C PSRR Power supply rejection ratio Zero scale See Notes 7 and 8 80 dBPSRR Power-supply rejection ratio Gain See Notes 7 and 8 80 dB Analog full scale output RL = 100 k W 2Vref(1023/1024) V NOTES: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). 2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text). 4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin). 5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kW excluding the effects of the zero-scale error. 6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). 7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero-scale change. voltage output (OUT) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Voltage output range RL = 10 k W 0 VDD–0.4 V Output load regulation accuracy VO(OUT) = 2 V, RL = 2 k W 0.5 LSB IOSC Output short circuit current OUT to VDD or AGND 20 mA VOL(low) Output voltage, low-level IO(OUT) ≤ 5 mA 0.25 V VOH(high) Output voltage, high-level IO(OUT) ≤ –5 mA 4.75 V TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2.048 V (unless otherwise noted) (continued) reference input (REFIN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage 0 VDD–2 V ri Input resistance 10 MW Ci Input capacitance 5 pF digital inputs (DIN, SCLK, CS) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level digital input voltage 2.4 V VIL Low-level digital input voltage 0.8 V IIH High-level digital input current VI = VDD ±1 m A IIL Low-level digital input current VI = 0 ±1 m A Ci Input capacitance 8 pF digital output (DOUT) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Output voltage, high-level IO = –2 mA VDD–1 V VOL Output voltage, low-level IO = 2 mA 0.4 V power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD Supply voltage 4.5 5 5.5 V IDD Power supply current VDD = 5.5 V, No load, All inputs = 0 V or VDD Vref = 0 150 250 m A IDD Power supply current VDD = 5.5 V, No load, All inputs = 0 V or VDD Vref = 2.048 V 230 350 m A analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Signal-to-noise + distortion, S/(N+D) Vref = 1 Vpp at 1 kHz + 2.048 Vdc, code = 11 1111 1111, See Note 9 60 dB NOTE 9: The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate. TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 digital input timing requirements (see Figure 1) PARAMETER MIN NOM MAX UNIT tsu(DS) Setup time, DIN before SCLK high 45 ns th(DH) Hold time, DIN valid after SCLK high 0 ns tsu(CSS) Setup time, CS low to SCLK high 1 ns tsu(CS1) Setup time, CS high to SCLK high 50 ns th(CSH0) Hold time, SCLK low to CS low 1 ns th(CSH1) Hold time, SCLK low to CS high 0 ns tw(CS) Pulse duration, minimum chip select pulse width high 20 ns tw(CL) Pulse duration, SCLK low 25 ns tw(CH) Pulse duration, SCLK high 25 ns output switching characteristic PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tpd(DOUT) Propagation delay time, DOUT CL = 50 pF 50 ns operating characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, Vref = 2.048 V (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Output slew rate CL = 100 pF,TA = 25°C RL = 10 k W , 0.3 0.5 V/m s ts Output settling time To 0.5 LSB, RL = 10 k W , CL = 100 pF, See Note 10 12.5 m s Glitch energy DIN = All 0s to all 1s 5 nV�s NOTE 10: Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex. reference input (REFIN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference feedthrough REFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see Note 11) –80 dB Reference input bandwidth (f–3dB) REFIN = 0.2 Vpp + 2.048 Vdc REFIN = 0.2 Vpp + 2.048 Vdc 30 kHz NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048 Vdc + 1 Vpp at 1 kHz. TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ th(CSH0) tsu(CSS) tw(CH) tw(CL) th(CSH1) tsu(CS1) tw(CS) tpd(DOUT) CS SCLK DIN DOUT tsu(DS) th(DH) NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough. See Note A See Note A See Note B MSB LSB B. Data input from preceeding conversion cycle. See Note C Previous LSB C. Sixteenth SCLK falling edge Figure 1. Timing Diagram TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS 8 6 2 0 0.1 0.2 0.4 0.6 – O ut pu t S in k Cu rr en t – m A 10 14 OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE 16 0.8 1 4 12 18 20 0.3 0.5 0.7 0.9 1.1 1.2 VDD = 5 V VREFIN = 2.048 V TA = 25°C I O VO – Output Pulldown Voltage – V Figure 2 15 10 5 0 20 25 OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE 30 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 VDD = 5 V VREFIN = 2.048 V TA = 25°C – O ut pu t S ou rc e Cu rr en t – m A I O VO – Output Pullup Voltage – V Figure 3 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS 80 – Su pp ly C ur re nt – 200 280 SUPPLY CURRENT vs TEMPERATURE 240 160 120 40 0 –60 –40 –20 0 20 40 60 80 100 120 140 A m t – Temperature – °C VDD = 5 V VREFIN = 2.048 V TA = 25°C I D D Figure 4 1 100 1 k 10 k 100 k G – R el at iv e G ai n – dB VREFIN TO V(OUT) RELATIVE GAIN vs INPUT FREQUENCY 4 2 0 –2 –4 –6 –8 –10 –12 –14 VDD = 5 V VREFIN = 0.2 VPP + 2.048 V dc TA = 25°C fI – Input Frequency – Hz Figure 5 40 50 1 k Si gn al -T o -N oi se + D is to rti on – d B 70 30 Frequency – Hz SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY AT REFIN 20 10 0 60 10 k 100 k 300 k VDD = 5 V TA = 25°C VREFIN = 4 VPP Figure 6 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS D iff er en tia l N on lin ea rit y – LS B –0.2 0.2 0.1 0 –0.05 0.15 0.05 –0.1 –0.15 Input Code 255 511 767 10230 Figure 7. Differential Nonlinearity With Input Code In te gr al N on lin ea rit y – LS B –0.6 Input Code 1 0 –0.2 255 511 767 10230 0.8 0.6 0.4 0.2 –0.4 –0.8 –1 Figure 8. Integral Nonlinearity With Input Code TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION general function The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1). An internal circuit resets the DAC register to all zeros on power up. _ +Resistor String DAC 5 V 0.1 m F AGND VDD OUT REFIN DIN SCLK CS DOUT R R _ + Figure 9. TLC5615 Typical Operating Circuit Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2 INPUT† OUTPUT 1111 1111 11(00) 2�VREFIN� 1023 1024 : : 1000 0000 01(00) 2�VREFIN� 513 1024 1000 0000 00(00) 2�VREFIN� 512 1024� VREFIN 0111 1111 11(00) 2�VREFIN� 511 1024 : : 0000 0000 01(00) 2�VREFIN� 1 1024 0000 0000 00(00) 0 V † A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide. TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION buffer amplifier The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kW load with a 100-pF load capacitance. Settling time is 12.5 m s typical to within 0.5 LSB of final value. external reference The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10 MW and the REFIN input capacitance is typically 5 pF independent of input code. The reference voltage determines the DAC full-scale output. logic interface The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels. serial clock and update rate Figure 1 shows the TLC5615 timing. The maximum serial clock rate is: f(SCLK)max � 1t w�CH� � tw�CL� or approximately 14 MHz. The digital update rate is limited by the chip-select period, which is: tp(CS) � 16��tw�CH� � tw�CL��� tw�CS� and is equal to 820 ns which is a 1.21 MHz update rate. However, the DAC settling time to 10 bits of 12.5 m s limits the update rate to 80 kHz for full-scale input step transitions. TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION serial interface When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The rising edge of the SLCK input shifts the data into the input register. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked into the input register. All CS transitions should occur when the SCLK input is low. If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data sequence with the MSB first can be used as shown in Figure 10: 10 Data Bits x x 12 Bits MSB LSB 2 Extra (Sub-LSB) Bits x = don’t care Figure 10. 12-Bit Input Data Sequence or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first. 10 Data Bits x x 16 Bits MSB LSB 2 Extra (Sub-LSB) Bits 4 Upper Dummy Bits x = don’t care Figure 11. 16-Bit Input Data Sequence The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal (see Figure 1). The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data converter transfers. The TLC5615 three-wire interface is compatible with the SPI, QSPI†, and Microwire serial standards. The hardware connections are shown in Figure 12 and Figure 13. The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC input register in one write cycle. † CPOL = 0, CPHA = 0, QSPI protocol designations TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION serial interface (continued) SCLK DIN CS DOUT TLC5615 SK SO I/O SI Microwire Port NOTE A: The DOUT-SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired. Figure 12. Microwire Connection SCLK DIN CS DOUT TLC5615 SCK MOSI I/O MISO SPI/QSPI Port NOTE A: The DOUT-MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer. CPOL = 0, CPHA = 0 Figure 13. SPI/QSPI Connection daisy-chaining devices DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain, providing that the setup time, tsu(CSS), (CS low to SCLK high) is greater than the sum of the setup time, tsu(DS), p