从mips迁移到arm（英文版）

Application Note 235 Copyright © 2010 ARM Limited. All rights reserved. 1 ARM DAI 0235C Application Note Migrating from MIPS to ARM Document number: ARM DAI 0235 Issued: March 2010 Copyright ARM Limited 2010 235 Introduction 2 Copyright © 2010 ARM Limited. All rights reserved. Application Note 235 ARM DAI 0235C Application Note 235 Migrating from MIPS to ARM Copyright © 2010 ARM Limited. All rights reserved. Release information The following changes have been made to this Application Note. Change history Date Issue Change May 2010 A First release June 2010 B Minor corrections July 2010 C Minor additions Proprietary notice Words and logos marked with ® or © are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Confidentiality status This document is Open Access. This document has no restriction on distribution. Feedback on this Application Note If you have any comments on this Application Note, please send email to errata@arm.com giving:  the document title  the document number  the page number(s) to which your comments refer  an explanation of your comments. General suggestions for additions and improvements are also welcome. ARM web address http://www.arm.com Introduction Application Note 235 Copyright © 2010 ARM Limited. All rights reserved. 3 ARM DAI 0235C Introduction 4 Copyright © 2010 ARM Limited. All rights reserved. Application Note 235 ARM DAI 0235C Table of Contents 1 Introduction ................................................................................................................5 1.1 The ARM architecture .........................................................................................5 1.2 ARM development tools ......................................................................................5 1.3 References and Further Reading........................................................................5 2 ARM architecture features.........................................................................................6 2.1 ARM architecture versions ..................................................................................6 2.2 Programmer’s model...........................................................................................6 2.3 Debug..................................................................................................................8 3 MIPS and ARM compared..........................................................................................9 3.1 Programmer’s model...........................................................................................9 3.2 System control and configuration registers .......................................................15 3.3 Exceptions and interrupts..................................................................................15 3.4 Memory .............................................................................................................17 3.5 Debug................................................................................................................19 3.6 Power management ..........................................................................................20 3.7 Security features ...............................................................................................21 4 Migrating a software application ............................................................................22 4.1 General considerations .....................................................................................22 4.2 Tools configuration............................................................................................24 4.3 Startup...............................................................................................................24 4.4 Handling interrupts and exceptions...................................................................25 4.5 Timing and delays .............................................................................................30 4.6 Power Management ..........................................................................................30 4.7 C Programming .................................................................................................31 Introduction Application Note 235 Copyright © 2010 ARM Limited. All rights reserved. 5 ARM DAI 0235C 1 Introduction The purpose of this document is to highlight areas of interest for those involved in migrating software applications from MIPS to ARM platforms. No attempt is made to promote one architecture over the other, merely to explain clearly the issues involved in a decision to migrate an existing software application from one to the other. Familiarity with the MIPS architecture is assumed and corresponding ARM features are explained. The ARM architecture is supported by a wide range of technology, tools and infrastructure available from a large number of partners in the ARM Connected Community. Pointers to these resources are given where appropriate, although ARM’s own supporting technology is highlighted. There is much related documentation available from ARM (see references below) which should be consulted where further detail is required. 1.1 The ARM architecture The ARM architecture represents the most popular 32-bit embedded processor range in current use. It is, in essence, a RISC architecture. However, its evolution over the last 24 years has introduced many features and extensions which do not necessarily sit comfortably with the RISC ideal. The current versions of the architecture are described in more detail below. 1.2 ARM development tools Tools for developing software for ARM platforms are available from a wide selection of vendors. ARM itself produces the RealView range of tools for high-performance application development. The Keil Microcontroller Develop Kit (MDK) is a lower-cost solution for development with microcontroller products. Many other toolsets are available from other vendors, including a free toolchain from GNU. 1.3 References and Further Reading ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition, ARM DDI 0406B ARMv7-M Architecture Reference Manual, ARM DDI 0403D Cortex-A9 Technical Reference Manual, ARM DDI 0388E Cortex-M3 Technical Reference Manual, ARM DDI 0337G RealView Compilations Tools Developer Guide, ARM DUE 0203I Keil Embedded Development Tools - Getting Started, ARM KUI 0049A (All ARM/Keil documentation referenced here may be downloaded directly from infocenter.arm.com) ARM architecture features 6 Copyright © 2010 ARM Limited. All rights reserved. Application Note 235 ARM DAI 0235C 2 ARM architecture features ARM is a 32-bit architecture. As such, it has 32-bit registers, ALU, data paths, address and data buses. Additionally, in the native ARM instruction set, all instructions are 32 bits wide. Individual ARM implementations may have internal 64-bit paths for performance reasons. 2.1 ARM architecture versions The ARM architecture has been through several revisions since its emergence in the mid 1980’s. The most recent version, ARMv7, is implemented in the Cortex range of processor cores. The architecture is defined in three “profiles”, the ‘A’ profile or Application-class processors, ‘R’ for Real-time and ‘M’ for microcontroller devices. ARMv7-A is currently implemented in the Cortex-A5, Cortex-A8 and Cortex-A9 processors and supports fully-featured application class devices capable of running platform Operating Systems such as Linux, WinCE etc. It provides full virtual memory support and optional media processing extensions. ARMv7-R is available in the Cortex-R4 and is targeted as applications which require hard, predictable real-time performance. Devices incorporating a Cortex-R4 processor core are used, for instance, in engine management systems, hard disk drive controllers and mobile baseband processors. ARMv7-M is used in microcontroller-type devices, principally those based around the Cortex-M3 core. This profile supports a subset of features in the v7-A and v7-R profiles aimed at enabling devices which maximize power efficiency and minimize cost. The architecture incorporates many features common in the microcontroller world e.g. bit- banding, hardware interrupt pre-emption etc. 2.2 Programmer’s model The description presented here is standard for the ARMv7-A and ARMv7-A architecture profiles. The ARMv7-M microcontroller profile has a different model for modes and exceptions. 2.2.1 Standard features 1. Register set The ARM register set consists of 37 general-purpose registers, 16 of which are usable at any one time. The subset which is usable is determined by the current operation mode (see below). In addition to the general purpose registers, the CPSR (Current Program Status Register) hold current status, operating mode, instruction set state, ALU status flags etc. 2. Operating modes The ARM core supports seven operating modes. All of these, with the exception of User mode, are privileged. Five modes (Supervisor, Undefined, Abort, FIQ and IRQ) are associated with handling particular types of exception events. Applications generally run either in User mode (unprivileged) or System mode (privileged) with the operating system, if one is used, running in Supervisor mode. 3. Instruction sets Current ARM cores may support several instruction sets:  The native ARM instruction set, in which all instructions are 32-bit. ARM architecture features Application Note 235 Copyright © 2010 ARM Limited. All rights reserved. 7 ARM DAI 0235C  The Thumb instruction set (introduced in ARMv4T), in which all instructions are 16-bit. This provides greatly improved code density.  Java bytecode – cores which include the Jazelle-DBX extension are capable of executing Java bytecode directly in hardware. The ARM and Thumb instruction sets have both been extended several times since their introduction. In particular, the Thumb-2 extension introduces 32-bit instructions into the 16-bit Thumb instruction set providing greatly increased performance without compromising the code density benefits of thumb. Of the ARM cores available on the market today, all support the ARM and Thumb instruction sets as a minimum, with the exception of ARMv7-M devices which support only the Thumb-2 instruction set. 4. Exceptions and interrupts ARM supports seven basic exception types. External interrupts are mapped to the FIQ and IRQ exceptions. Other exceptions are used for external errors (e.g. bus errors), internal errors (e.g. undefined instructions or memory address translation faults), or software interrupts (caused synchronously by executing an SVC instruction). 5. Memory architecture ARM cores have a 32-bit address bus providing a flat 4GB linear address space. Memory is addressed in bytes and may be accessed as 8-byte doublewords, 4-byte words, 2-byte halfwords or single bytes. Configuration options in the core determine the endianness and alignment behavior of the memory interface. More advanced ARM cores implement caches, Tightly Coupled Memory (TCM) regions, virtual memory and memory protection features. 2.2.2 Advanced features 1. Neon and floating point ARM provides a standard floating point coprocessor, VFP, which exists in several versions. It is capable of both scalar and vector operations in single and double precision IEEE 754 floating point. The Cortex-A cores, which implement the ARMv7-A architecture, may include the Neon media processing instruction set. If present, this is executed by a separate media processing engine integrated with the main integer pipeline. 2. Jazelle ARM provides two optional methods for acceleration of Java and other dynamically compiler languages. Jazelle-DBX (Direct Bytecode eXecution) which supports execution of a subset of Java bytecodes in hardware. Jazelle-RCT (Runtime Compilation Target) which provides some extended instructions to improve performance of Just-In-Time compilation techniques for languages like Java, Perl etc. 3. Memory protection Many ARM cores incorporate a Memory Protection Unit (MPU) which allows memory to be partitioned into a number of regions. Each region cab be assigned access permissions which are policed automatically by the MPU at run-time. 4. Virtual memory ARM architecture features 8 Copyright © 2010 ARM Limited. All rights reserved. Application Note 235 ARM DAI 0235C Application class cores (such as ARM1176JZ-S, Cortex-A9 etc) incorporate a Memory Management Unit (MMU). As well as providing the protection capabilities of an MPU, an MMU also provides full virtual-physical address translation allowing implementation of platform operating system such as Linux, Windows Mobile etc. 5. Generic interrupt controllers Almost all ARM-based devices include an interrupt controller of some kind. More recent ARM cores have standardized on a Generic Interrupt Controller (GIC). 6. Multicore support ARM11MPCore and Cortex-A9 MPCore are multi-core versions of the ARM11 and Cortex-A9 respectively. They are designed to be used in clusters of up to four cores which are connected via logic which controls interrupt distribution and manages cache coherency. 2.3 Debug ARM provides debug using the industry-standard JTAG port. As standard, this uses a 5- wire connection. A 2-wire version is also available for use in applications where pin-count is at a premium. ARM’s CoreSight on-chip debug infrastructure allows chip designers to specify and build complex multi-core debug systems which allow synchronous trace and debug of multiple cores within a single device. MIPS and ARM compared Application Note 235 Copyright © 2010 ARM Limited. All rights reserved. 9 ARM DAI 0235C 3 MIPS and ARM compared Both MIPS and ARM produce a wide range of processor cores, targeted at various price and performance points. As far as it is possible to make direct comparisons, the following table attempts to line up the product ranges. MIPS ARM MIPS4K ARM966E-S and Cortex-M3 MIPS4KEc ARM926EJ-S MIPS4KSd SC300 MIPS24K ARM1176JZ-S MIPS24Kc ARM1156T2(F)-S, Cortex-R4 MIPS24Kf ARM1176JZF-S MIPS34K Cortex-A5, ARM11 MPCore MIPS74K Cortex-A8, Cortex-A9 UP MIPS1004K Cortex-A5, ARM11 MPCore The MIPS64 architecture, supported by MIPS5K and MIPS20K processors incorporates 64-bit elements (64-bit data and address paths and a larger virtual memory space, for instance). ARM processors, since the ARM10 have supported 64-bit data buses between the core and the caches, greatly increasing throughput and efficiency. ARM’s flat 4GB address space has been available since the first versions of the architecture. In this document, where examples are required, we assume that the target ARM core is either an ARMv7-M device (e.g. Cortex-M3) or ARMv7-A (e.g. Cortex-A9). 3.1 Programmer’s model Both MIPS and ARM are “RISC” architectures. As such, they have limited instruction sets and large register sets. Both are load-store architectures (i.e. they cannot directly manipulate the contents of memory locations). The programmer’s models are therefore somewhat similar since both reflect the RISC approach. However there are some significant differences. 3.1.1 Register set Of the two, MIPS has a larger set of general purpose registers, having 32 in all. However, some of these have special purposes and this effectively reduces the set which is routinely available to the programmer. The MIPS registers are named $0, $1,…$31. $0 is a pseudo-register which always holds the value zero. Several other MIPS registers are reserved for special use in interrupt handlers and also by the assembler for “synthetic” instructions (see below). The ARM register set is much more straightforward in that all registers, with very few exceptions, are fully accessible and behave identically. In particular, the program counter (r15, commonly referred to as pc) is generally accessible in the same way as any other register. This allows many novel uses of instructions which modify or access the pc to control program flow in efficient ways. The larger register set offered by MIPS can reduce register pressure for compiled code but greatly increases the cost of context save/restore operations necessitated by task MIPS and ARM compared 10 Copyright © 2010 ARM Limited. All rights reserved. Application Note 235 ARM DAI 0235C switches or interrupts. The need to use larger fields in instructions to specify register operands also somewhat reduces the flexibility of MIPS instructions. ARM instructions, for instance, often support more flexible addressing modes as there are bits available to encode more options. Although the ARM register set is smaller, techniques like register renaming (in which architectural registers are dynamically mapped in the pipeline to a much larger set of physical registers) greatly increase the scope for code optimizations in ARM systems. The MIPs architecture supports the implementation of multiple “shadow” banks of registers. This allows more efficient context-switching operations but the fact that this feature is not commonly or consistently implemented on MIPS-based devices makes it of limited use. Consequently, few compilers or operating systems make use of it. In addition to the general purpose register set, MIPS provides two separate registers (Hi and Lo) to hold the results of a multiply operation. Special instructions are used to read these registers and copy the contents to general purpose registers. These registers must also be saved in the event of exceptions or task switches, increasing the cost of having them. In contrast, the ARM multiplication instructions use general purpose registers for input and output, removing the need to save and restore extra registers. Both architectures support coprocessors with separate banks of dedicated registers. ARM supports up to 15 coprocessors (with 11 available for user-definition), while MIPS supports up to 4. 3.1.2 Status registers In addition to the general purpose register set, both architectures provide status registers holding e.g. ALU status flags, interrupt status and current mode. The ARM CPSR (Current Program Status Register) is as follows in the v7-A and v7-R profiles. In general, only the ALU flags (NZCVQ) are modifiable when executing in user mode. Other fields, with the exception of T and J bits, may be modified directly when in privileged modes. T and J bits are only changed indirectly by execution of instructions like BX and BXJ. A P The v7-M CPSR can be referred to using the following names, which indicate various combinations of sub-fields. APSR – Application Program Status Register (ALU flags only) IPSR – Interrupt Program Status Register (ISE number) EPSR – Execution Program Status Register (IT, ICI and T fields) The name xPSR refers to a composite of all three and is the one automatically saved on the stack on entry to an exception. Only APSR is accessible to Thread mode programs. I