74HC374芯片资料

TL/F/5336 M M 5 4 H C 3 7 4 / M M 7 4 H C 3 7 4 T R I-S T A T E O c ta l D -T y p e F lip -F lo p January 1988 MM54HC374/MM74HC374 TRI-STATEÉ Octal D-Type Flip-Flop General Description These high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the TRI- STATE feature, these devices are ideally suited for interfac- ing with bus lines in a bus organized system. These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are pres- ent at the other inputs and the state of the storage ele- ments. The 54HC/74HC logic family is speed, function, and pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features Y Typical propagation delay: 20 ns Y Wide operating voltage range: 2–6V Y Low input current: 1 mA maximum Y Low quiescent current: 80 mA maximum Y Compatible with bus-oriented systems Y Output drive capability: 15 LS-TTL loads Connection Diagram Dual-In-Line Package TL/F/5336–1 Top View Order Number MM54HC374 or MM74HC374 Truth Table Output Clock Data Output Control L u H H L u L L L L X Q0 H X X Z H e high Level, L e Low Level X e don’t Care ue transition from low-to-high Z e high impedance state Q0e the level of the output before steady state input conditions were established TRI-STATEÉ is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) b0.5 to a7.0V DC Input Voltage (VIN) b1.5 to VCCa1.5V DC Output Voltage (VOUT) b0.5 to VCCa0.5V Clamp Diode Current (IIK, IOK) g20 mA DC Output Current, per pin (IOUT) g35 mA DC VCC or GND Current, per pin (ICC) g70 mA Storage Temperature Range (TSTG) b65§C to a150§C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§C Operating Conditions Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V (VIN, VOUT) Operating Temp. Range (TA) MM74HC b40 a85 §C MM54HC b55 a125 §C Input Rise or Fall Times VCCe2.0V(tr, tf) 1000 ns VCCe4.5V 500 ns VCCe6.0V 400 ns DC Electrical Characteristics TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits VIH Minimum High Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V Input Voltage** 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VOH Minimum High Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VINeVIH or VIL lIOUTls6.0 mA 4.5V 4.2 3.98 3.84 3.7 V lIOUTls7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum Low Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VINeVIH or VIL lIOUTls6.0 mA 4.5V 0.2 0.26 0.33 0.4 V lIOUTls7.8 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA Current IOZ Maximum TRI-STATE VINeVIH, OCeVIH 6.0V g0.5 g5 g10 mA Output Leakage VOUTeVCC or GND Current ICC Maximum Quiescent VINeVCC or GND 6.0V 8.0 80 160 mA Supply Current IOUTe0 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§C to 85§C; ceramic ‘‘J’’ package: b12 mW/§C from 100§C to 125§C. Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCCe5V, TAe25§C, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit fMAX Maximum Operating 50 35 MHz Frequency tPHL, tPLH Maximum Propagation CLe45 pF 20 32 ns Delay Clock to Q tPZH, tPZL Maximum Output Enable RLe kX Time CLe45 pF 19 28 ns tPHZ, tPLZ Maximum Output Disable RLe kX 17 25 ns Time CLe5 pF tS Minimum Setup Time 20 ns tH Minimum Hold Time 5 ns tW Minimum Pulse Width 9 16 ns AC Electrical Characteristics VCCe2.0–6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits fMAX Maximum Operating CLe50 pF 2.0V 6 5 4 MHz Frequency 4.5V 30 24 20 MHz 6.0V 35 28 23 MHz tPHL, tPLH Maximum Propagation CLe50 pF 2.0V 68 180 225 270 ns Delay, Clock to Q CLe150 pF 2.0V 110 230 288 345 ns CLe50 pF 4.5V 22 36 45 48 ns CLe150 pF 4.5V 30 46 57 69 ns CLe50 pF 6.0V 20 31 39 46 ns CLe150 pF 6.0V 28 40 50 60 ns tPZH, tPZL Maximum Output Enable RLe1 kX Time CLe50 pF 2.0V 50 150 189 225 ns CLe150 pF 2.0V 80 200 250 300 ns CLe50 pF 4.5V 21 30 37 45 ns CLe150 pF 4.5V 30 40 50 60 ns CLe50 pF 6.0V 19 26 31 39 ns CLe150 pF 6.0V 26 35 44 53 ns tPHZ, tPLZ Maximum Output Disable RLe1 kX 2.0V 50 150 189 225 ns Time CLe50 pF 4.5V 21 30 37 45 ns 6.0V 19 26 31 39 ns tS Minimum Setup Time 2.0V 50 60 75 ns 4.5V 9 13 15 ns 6.0V 9 11 13 ns tH Minimum Hold Time 2.0V 5 30 5 ns 4.5V 5 5 5 ns 6.0V 5 5 5 ns tW Minimum Pulse Width 2.0V 30 80 100 120 ns 4.5V 9 16 20 24 ns 6.0V 8 14 18 20 ns tTHL, tTLH Maximum Output Rise CLe50 pF 2.0V 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns tr, tf Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time, Clock 4.5V 500 500 500 ns 6.0V 400 400 400 ns CPD Power Dissipation (per flip-flop) Capacitance (Note 5) OCeVCC 30 pF OCeGND 50 pF CIN Maximum Input Capacitance 5 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. 3 M M 5 4 H C 3 7 4 / M M 7 4 H C 3 7 4 T R I- S T A T E O c ta l D -T y p e F li p -F lo p Physical Dimensions inches (millimeters) Order Number MM54HC374J or MM74HC374J NS Package J20A Order Number MM74HC374N NS Package N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. 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