74HC368芯片资料

TL/F/5209 M M 5 4 H C 3 6 5 / M M 5 4 H C 3 6 6 / M M 5 4 H C 3 6 7 / M M 5 4 H C 3 6 8 / M M 7 4 H C 3 6 5 / M M 7 4 H C 3 6 6 / M M 7 4 H C 3 6 7 / M M 7 4 H C 3 6 8 January 1988 MM54HC365/MM74HC365 Hex TRI-STATEÉ Buffer MM54HC366/MM74HC366 InvertingHexTRI-STATEBuffer MM54HC367/MM74HC367 Hex TRI-STATE Buffer MM54HC368/MM74HC368 InvertingHexTRI-STATEBuffer General Description These TRI-STATE buffers are general purpose high speed inverting and non-inverting buffers that utilize advanced sili- con-gate CMOS technology. They have high drive current outputs which enable high speed operation even when driv- ing large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds com- parable to low power Schottky TTL circuits. All 4 circuits are capable of driving up to 15 low power Schottky inputs. The MM54/74HC366 and the MM54/74HC368 are inverting buffers, where as the MM54/74HC365 and the MM54/ 74HC367 are non-inverting buffers. The MM54/74HC365 and the MM54/74HC366 have two TRI-STATE control in- puts (G1 and G2) which are NORed together to control all six gates. The MM54/74HC367 and the MM54/74HC368 also have two output enables, but one enable (G1) controls 4 gates and the other (G2) controls the remaining 2 gates. All inputs are protected from damage due to static dis- charge by diodes to VCC and ground. Features Y Typical propagation delay: 15 ns Y Wide operating voltage range: 2V–6V Y Low input current: 1 mA maximum Y Low quiescent current: 80 mA maximum (74 Series) Y Output drive capability: 15 LS-TTL loads Connection Diagrams Dual-In-Line Packages/Top Views TL/F/5209–1 Order Number MM54HC365 or MM74HC365 TL/F/5209–3 Order Number MM54HC367 or MM74HC367 TL/F/5209–2 Order Number MM54HC366 or MM74HC366 TL/F/5209–4 Order Number MM54HC368 or MM74HC368 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) b0.5 to a7.0V DC Input Voltage (VIN) b1.5 to VCCa1.5V DC Output Voltage (VOUT) b0.5 to VCCa0.5V Clamp Diode Current (IIK, IOK) g20 mA DC Output Current, per pin (IOUT) g35 mA DC VCC or GND Current, per pin (ICC) g70 mA Storage Temperature Range (TSTG) b65§C to a150§C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§C Operating Conditions Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V (VIN, VOUT) Operating Temp. Range (TA) MM74HC b40 a85 §C MM54HC b55 a125 §C Input Rise or Fall Times VCCe2.0V(tr, tf) 1000 ns VCCe4.5V 500 ns VCCe6.0V 400 ns DC Electrical Characteristics (Note 4) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits VIH Minimum High Level Input 2.0V 1.5 1.5 1.5 V Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum Low Level Input 2.0V 0.5 0.5 0.5 V Voltage** 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VOH Minimum High Level Output VINeVIH or VIL Voltage lIOUTls20 mA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VINeVIH or VIL lIOUTls6.0 mA 4.5V 4.2 3.98 3.84 3.7 V lIOUTls7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum Low Level Output VINeVIH or VIL Voltage lIOUTls20 mA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VINeVIH or VIL lIOUTls6.0 mA 4.5V 0.2 0.26 0.33 0.4 V lIOUTls7.8 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input Current VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA IOZ Maximum TRI-STATE Output VOUTeVCC or GND 6.0V g0.5 g5.0 g10 mA Leakage Current GeVIH ICC Maximum Quiescent Supply VINeVCC or GND 6.0V 8.0 80 160 mA Current IOUTe0 mA Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§C to 85§C; ceramic ‘‘J’’ package: b12 mW/§C from 100§C to 125§C. Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics MM54HC365/MM74HC365 VCCe5V, TAe25§C, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit tPHL, tPLH Maximum Propagation CLe45 pF 15 22 ns Delay tPZH, tPZL Maximum Output Enable RLe1 kX 29 40 ns Time CLe45 pF tPHZ, tPLZ Maximum Output Disable RLe1 kX 25 36 ns Time CLe5 pF AC Electrical Characteristics MM54HC365/MM74HC365 VCCe2.0–6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits tPHL, tPLH Maximum Propagation CLe50 pF 2.0V 35 105 130 150 ns Delay CLe150 pF 2.0V 45 135 168 205 ns CLe50 pF 4.5V 14 24 30 36 ns CLe150 pF 4.5V 17 29 36 45 ns CLe50 pF 6.0V 11 19 24 28 ns CLe150 pF 6.0V 15 24 30 36 ns tPZH, tPZL Maximum Output Enable RLe1 kX Time CLe50 pF 2.0V 90 230 287 345 ns CLe150 pF 2.0V 98 245 306 367 ns CLe50 pF 4.5V 31 44 55 66 ns CLe150 pF 4.5V 38 53 66 80 ns CLe50 pF 6.0V 25 35 43 52 ns CLe150 pF 6.0V 29 41 51 62 ns tPHZ, tPLZ Maximum Output Disable RLe1 kX 2.0V 58 175 218 260 ns Time CLe50 pF 4.5V 26 44 55 66 ns 6.0V 22 37 46 55 ns tTHL, tTLH Maximum Output Rise CLe50 pF 2.0V 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns CPD Power Dissipation Any Enabled 45 pF Capacitance (Note 5) A Input Any Disabled 8 pF A Input CIN Maximum Input 5 10 10 10 pF Capacitance COUT Maximum Output 10 20 20 20 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. Truth Table ’HC365 Inputs Output G1 G2 A Y H X X Z X H X Z L L H H L L L L 3 AC Electrical Characteristics (Continued) MM54HC366/MM74HC366 VCCe5V, TAe25§C, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit tPHL, tPLH Maximum Propagation CLe45 pF 12 18 ns Delay tPZL, tPZH Maximum Output Enable RLe1 kX 29 40 ns Time CLe45 pF tPHZ, tPLZ Maximum Output Disable RLe1 kX 25 36 ns Time CLe5 pF AC Electrical Characteristics MM54HC366/MM74HC366 VCCe2.0–6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits tPHL, tPLH Maximum Propagation CLe50 pF 2.0V 33 82 102 125 ns Delay CLe150 pF 2.0V 43 107 134 160 ns CLe50 pF 4.5V 12 19 24 30 ns CLe150 pF 4.5V 16 26 32 39 ns CLe50 pF 6.0V 10 16 20 24 ns CLe150 pF 6.0V 14 22 27 33 ns tPZH, tPZL Maximum Output Enable RLe1 kX ns Time CLe50 pF 2.0V 90 230 287 345 ns CLe150 pF 2.0V 98 245 306 367 ns CLe50 pF 4.5V 31 44 55 66 ns CLe150 pF 4.5V 38 53 66 80 ns CLe50 pF 6.0V 25 35 43 52 ns CLe150 pF 6.0V 29 41 51 62 ns tPHZ, tPLZ Maximum Output Disable RLe1 kX 2.0V 58 175 218 260 ns Time CLe50 pF 4.5V 26 44 55 66 ns 6.0V 22 37 46 55 ns tTHL, tTLH Maximum Output Rise CLe50 pF 2.0V 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns CPD Power Dissipation Any Enabled 45 pF Capacitance (Note 5) A Input Any Disabled 6 pF A Input CIN Maximum Input 5 10 10 10 pF Capacitance COUT Maximum Output 10 20 20 20 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. Truth Table ’HC366 Inputs Output G1 G2 A Y H X X Z X H X Z L L H L L L L H 4 AC Electrical Characteristics (Continued) MM54HC367/MM74HC367 VCCe5V, TAe25§C, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit tPHL, tPLH Maximum Propagation CLe45 pF 13 22 ns Delay tPZL, tPZH Maximum Output Enable RLe1 kX 23 37 ns Time CLe45 pF tPHZ, tPLZ Maximum Output Disable RLe1 kX 25 33 ns Time CLe5 pF AC Electrical Characteristics MM54HC367/MM74HC367 VCCe2.0–6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits tPHL, tPLH Maximum Propagation CLe50 pF 2.0V 35 105 130 150 ns Delay CLe150 pF 2.0V 45 135 168 205 ns CLe50 pF 4.5V 14 24 30 36 ns CLe150 pF 4.5V 17 29 36 45 ns CLe50 pF 6.0V 11 19 24 28 ns CLe150 pF 6.0V 15 24 30 36 ns tPZH, tPZL Maximum Output Enable RLe1 kX ns Time CLe50 pF 2.0V 69 172 216 250 ns CLe150 pF 2.0V 75 187 233 280 ns CLe50 pF 4.5V 24 38 47 57 ns CLe150 pF 4.5V 29 46 57 69 ns CLe50 pF 6.0V 22 35 43 52 ns CLe150 pF 6.0V 26 42 52 63 ns tPHZ, tPLZ Maximum Output Disable RLe1 kX 2.0V 47 117 146 220 ns Time CLe50 pF 4.5V 22 35 44 52 ns 6.0V 19 31 39 46 ns tTHL, tTLH Maximum Output Rise CLe50 pF 2.0V 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns CPD Power Dissipation Any Enabled 45 pF Capacitance (Note 5) A Input Any Disabled 8 pF A Input CIN Maximum Input 5 10 10 10 pF Capacitance COUT Maximum Output 10 20 20 20 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. Truth Table ’HC367 Inputs Output G A Y H X Z L H H L L L 5 AC Electrical Characteristics (Continued) MM54HC368/MM74HC368 VCCe5V, TAe25§C, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit tPHL, tPLH Maximum Propagation CLe45 pF 11 18 ns Delay tPZL, tPZH Maximum Output Enable RLe1 kX 23 37 ns Time CLe45 pF tPHZ, tPLZ Maximum Output Disable RLe1 kX 19 33 ns Time CLe5 pF AC Electrical Characteristics MM54HC368/MM74HC368 VCCe2.0–6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits tPHL, tPLH Maximum Propagation CLe50 pF 2.0V 33 82 102 125 ns Delay CLe150 pF 2.0V 43 107 134 160 ns CLe50 pF 4.5V 12 19 24 30 ns CLe150 pF 4.5V 16 26 32 39 ns CLe50 pF 6.0V 10 16 20 24 ns CLe150 pF 6.0V 14 22 27 33 ns tPZH, tPZL Maximum Output Enable RLe1 kX ns Time CLe50 pF 2.0V 69 172 216 250 ns CLe150 pF 2.0V 75 187 233 280 ns CLe50 pF 4.5V 24 38 47 57 ns CLe150 pF 4.5V 29 46 57 69 ns CLe50 pF 6.0V 22 35 43 52 ns CLe150 pF 6.0V 26 42 52 63 ns tPHZ, tPLZ Maximum Output Disable RLe1 kX 2.0V 47 117 146 220 ns Time CLe50 pF 4.5V 22 35 44 52 ns 6.0V 19 31 39 46 ns tTHL, tTLH Maximum Output Rise CLe50 pF 2.0V 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns CPD Power Dissipation Any Enabled 45 pF Capacitance (Note 5) A Input Any Disabled 6 pF A Input CIN Maximum Input 5 10 10 10 pF Capacitance COUT Maximum Input 10 20 20 20 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. Truth Table ’HC368 Inputs Output G A Y H X Z L H L L L H 6 Logic Diagrams MM54HC365/MM74HC365 TL/F/5209–5 MM54HC367/MM74HC367 TL/F/5209–7 MM54HC366/MM74HC366 TL/F/5209–6 MM54HC368/MM74HC368 TL/F/5209–8 7 M M 5 4 H C 3 6 5 / M M 5 4 H C 3 6 6 / M M 5 4 H C 3 6 7 / M M 5 4 H C 3 6 8 / M M 7 4 H C 3 6 5 / M M 7 4 H C 3 6 6 / M M 7 4 H C 3 6 7 / M M 7 4 H C 3 6 8 Physical Dimensions inches (millimeters) Order Number MM54HC365J, MM54HC366J, MM54HC367J, MM54HC368J, MM74HC365J, MM74HC366J, MM74HC367J, or MM74HC368J, NS Package J16A Order Number MM74HC365N, MM74HC366N, MM74HC367N, or MM74HC368N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. 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