SMT最热门技术----Flip Chip Technology

Chapter B: Flip-Chip Technology Chapter B: Flip-Chip Technology B1. Level 1. Introduction to Flip-Chip techniques Print this section in .pdf format by clicking the link Print Section B1. B1.1 Why flip-chip? In the development of packaging of electronics the aim is to lower cost, increase the packaging density, improve the performance while still maintaining or even improving the reliability of the circuits. The concept of flip-chip process where the semiconductor chip is assembled face down onto circuit board is ideal for size considerations, because there is no extra area needed for contacting on the sides of the component. The performance in high frequency applications is superior to other interconnection methods, because the length of the connection path is minimised. Also reliability is better than with packaged components due to decreased number of connections. In flip-chip joining there is only one level of connections between the chip and the circuit board. Potentially flip chip technology is cheaper than wire bonding because bonding of all connections takes place simultaneously whereas with wire bonding one bond is made at a time. In practise, however, this price benefit is not always achieved due to immature processes, e.g. the cost of die bumping with current processes can be significant, especially in low volumes. Flip-chip joining is not a new technology. The technology has been driven by IBM for mainframe computer applications. Many millions of flip chips have been processed by IBM on ceramic substrates since the end of 60`s. At the beginning of 70`s the automotive industry also began to use flip chips on ceramics. Today flip-chips are widely used for watches, mobile phones, portable communicators, disk drives, hearing aids, LCD displays, automotive engine controllers as well as the main frame computers. The number of flip chips assembled was over 500 million in year 1995 and close to 600 million flip chips were consumed 1997 [B1].   B1.2 General benefits/disadvantages Advantages: Smaller size: Smaller IC footprint (only about 5% of that of packaged IC e.g. quad flat pack), reduced height and weight. Increased functionality: The use of flip chips allow an increase in the number of I/O. I/O is not limited to the perimeter of the chip as in wire bonding. An area array pad layout enables more signal, power and ground connections in less space. A flip chip can easily handle more than 400 pads. Improved performance: Short interconnect delivers low inductance, resistance and capacitance, small electrical delays, good high frequency characteristics, thermal path from the back side of the die. Improved reliability: Epoxy underfill in large chips ensures high reliability. Flip-chips can reduce the number connections per pin from three to one. Improved thermal capabilities: Because flip chips are not encapsulated, the back side of the chip can be used for efficient cooling. Low cost: Batch bumping process, cost of bumping decreases, cost reductions in the underfill-process Figure B1. Comparison of the number of I/O vs. chip size between area array and perimeter array pad arrangement for pitches of 0.2 mm and 0.4 mm. Disadvantages: Difficult testing of bare dies. Limited availability of bumped chips. Challenge for PCB technology as pitches become very fine and bump counts are high. For inspection of hidden joints an X-ray equipment is needed. Weak process compatibility with SMT. Handling of bare chips is difficult. High assembly accuracy needed. With present day materials underfilling process with a considerable curing time is needed. Low reliability for some substrates. Repairing is difficult or impossible.   B1.3 Relative cost comparison The cost of flip chip technology can be divided into bumping cost and assembly process cost. Die bumping costs are dependent on wafer size, number of dies per wafer, wafer yield and volume. The assembly processes for the most common flip chip technology include pick and place together with flux application, reflow and cleaning as well as underfill process and its curing. The cost of the necessary equipment and floor space, the capacity of the equipment and its compatibility with other manufacturing processes are also important factors having influence on the economy of the technology for particular product. The substrate has also an important impact on the packaging costs. The cost of substrate depends e.g. on via sizes, layer count, line width and spaces, die pad pitch, flatness requirements, material type, panelization optimisation and the fabrication process. In the case of manufacturing of 300 - 400 I/O BGA packages in the volume of 1 million per month the capital cost of flip chip process is less than half of the corresponding cost for wire bonding technology and the floor space needed is also only about one half of that for wire bonding technology The cost of bumping with solder bumps using common batch processes is practically independent of the wafer size. The costs per die are therefore strongly dependent on the number of good dies obtained from one wafer. An order of magnitude for wafer bumping in high volume production is $85 per wafer. For the case of 10 mm die on 8 inch wafer and yield of 90% the bumping cost per die is $0.37. The cost of wire bonding process increases with increasing number of I/O磗 while the cost of flip chip process is practically independent of the I/O count. For very high I/O numbers the flip chip process is the only choice. Wire bonding, which is a mature technology, costs about $0.03 per pin, based on a 500 I/O device. The cost to bump a 200 mm with the evaporative process is around $200, sputtering and plating comes in at around $100, and electroless nickel bumping cost projections are below $50 [B1]. B1.4 Availability of components A precondition for using flip chip technique is availability of bumped chips or alternatively known good bare dies when bumping is done separately. The use of solder bumping is the most common process alternative. Many chip houses already deliver solder bumped dies http://www.imec.be/kgd/. Solder bumping which is a wafer level process, needs big and expensive facilities. Therefore it is not convenient to have inhouse processing facilities for solder bumping. There are also specialised companies making services of solder bumping. The situation with the availability of solder bumped and tested chips for flip chip bonding is still not satisfactory. Flip chip bonding knowledge is spreading slowly and as an additional production step in wafer manufacturing the known good die (KGD) issue is still causing a certain degree of uncertainty on the user side [B2].   B1.5 How mature is the technology?   Although flip chip technology has been used already for about 30 years, it is still in quite limited use. It has many technical variations which have very different levels of maturity and fairly restricted availability. The flip chip technology using solder joining is already in a fairly mature state. The limitations are at least partly related to the limited availability of bumped components and limited compatibility with available SMD processing equipment. B1.6 Short description of each flip chip process There are many different alternative processes used for flip-chip joining. A common feature of the joined structures is that the chip is lying face down to the substrate and the connections between the chip and the substrate are made using bumps of electrically conducting material. Cross sections of flip chip joints without and with underfill material are shown in Figure B2. Examples of the different types of flip chip joints are schematically shown in Figure B3.   Figure B2. Cross sections of flip chip joints without and with underfill material.   Figure B3. Examples of different types of flip chip joints.   B1.6.1 Flip chip process by solder joining. Also look at section B2.1 In flip chip soldering process solder bumped chips are soldered onto the circuit board. Solder is usually, but not always, deposited also on to the substrate pad areas. For fine pitch applications, solder can be deposited e.g. by electroplating, solder ink jet or solid solder deposition. Tacky flux is applied to the solder contact areas either by dipping the chip into a flux reservoir or by dispensing flux onto the substrate. For coarse pitch applications (>0.4 mm) solder paste is deposited on the substrate by stencil printing. The bumps of chips are placed into the tacky paste and they are reflowed in an oven. After the reflow process cleaning of the flux is preferred. The underfill material is applied by dispensing along one or two sides of the chip, from where the low viscosity epoxy is drawn by capillary forces into the space between the chip and substrate. Finally the underfill is cured by heat. Repairing of the flip chip joint is usually impossible after the underfill process. Therefore testing must be done after reflow and before the underfill application. The steps of flip chip soldering process are: die preparing (testing, bumping, dicing) substrate preparing (flux application or solder paste printing) pick, alignment and place reflow soldering cleaning of flux residues (optional) underfill dispensing underfill curing.   Figure B4. Flip chip soldering process.   Figure B5. The underfill application by dispensing.   B1.6.2 Flip chip joining by thermocompression. Also look at section B2.2 In the thermocompression bonding process, the bumps of the chip are bonded to the pads on the substrate by force and heat applied from an end effector. The process requires gold bumps on the chip or the substrate and a corrrespondingly bondable surface (e.g. gold, aluminium). The bonding temperature is usually high, e.g. 300      B1.6.3 Flip chip thermosonic joining. Also look at section B2.3 The thermocompression bonding process can be made more efficient by using ultrasonic power to speed up the welding process. Ultrasonic energy is transferred to the bonding area from the pick-up tool through the back surface of the chip. The thermosonic bonding introduces ultrasonic energy that softens the bonding material and makes it vulnerable to plastic deformation. The main benefit of the method compared to thermocompression is lower bonding temperature and shorter processing time. One potential problem associated with thermosonic bonding is silicon cratering. It is generally believed that such damage results from excessive ultrasonic vibration. B1.6.4 Flip chip joining using adhesives (isotropic, anisotropic, nonconductive). Also look at section B2.4 Conductive adhesives have become a viable alternative to tin-lead solders also in flip chip joining. Adhesively bonded flip chip combines the advantages of thin structures and cost efficiency. The advantages of conductive adhesives include ease of processing, low curing temperatures, and elimination of the need to clean after the bonding process. Anisotropically conductive adhesives have also the ability to connect fine pitch devices. Figure B7 shows a schematic drawing of flip chip bonding with isotropically and anisotropically conductive adhesives (ICAs and ACAs). Also nonconductive adhesives can be used for flip chip bonding, in this case the joint surfaces are forced into intimate contact by the adhesive between the component and substrate. Figure B7.Schematic drawings of flip chip joints made with conductive adhesives. Isotropically conductive adhesives are pastes of polymer resin that are filled with conducting particles to a content that assures conductivity in all directions. Generally, the polymer resin is epoxy and conducting particles are silver. Anisotropically conductive adhesives are pastes or films of thermoplastics or b-stage epoxies. They are filled with metal particles or metal coated polymer spheres to a content that assures electrical insulation in all directions before bonding. After bonding the adhesive becomes electrically conductive in z-direction The metal particles are typically nickel or gold and these metals are also used to coat polymer spheres.   B1.7 Reliability The different flip chip processes have different aspects concerning the reliability. However, one key factor which has drastically increased the reliability of flip chip structures against temperature variations is the use of underfiller between the chip and the circuit board which, when properly selected and applied, may increase the reliability by more than one decade. The underfill materials, usually filled epoxies, are stiff enough to take part of the forces developed by different thermal expansion coefficients of the chip and substrate. An underfill material also protects the face of the chip against moisture and impurities and makes the structure mechanically stronger.   B1.8 Testing. Also look at section B2.1.1 Testing The reason for testing is to assure the functionality of the components before and after the flip chip process. The flip chip joined structure should be tested before underfill process when the repairing is still possible   Chapter B: Flip-Chip Technology B2. Level 2. Guidelines Print this section in .pdf format by clicking the link Print Section B2. B2.1 Flip Chip bonding using soldering process B2.1.1 Design issues Bumping and UBM processes Various bumping processes suited for flip chip soldering have been reviewed e.g. by Patterson et al [B3]. The main wafer level bumping processes are evaporated solder bumping, electroplated solder bumping and printed solder paste bumping. Solder ball bumping using slightly modified ball bonder and wire of solder alloy material have also been used. The deposition of under bump metallurgy (UBM) on to the pad areas of the chip is a very important issue to allow bump formation and to stand the flip chip soldering process. The under bump metallurgy has various functions. It must allow good enough adhesion to the pad metallisation which usually is aluminium. It must act as a diffusion barrier during the soldering process, allow good wettability of the solder material and prevent oxidation of the surface. For different bumping processes different under bump metallurgies are used. Table B1 summarises the features of each solder deposition processes in terms of under bump metallurgy. Table B1. Under bump metallurgies used for different bumping processes [B3]. UBM Evaporated (typical of C4) Plating I Plating II Solder paste printing (typ FCT) Electroless nickel Adhesion layer Cr TiW CrCu Al Ni Solder diffusion layer Phased Cr-Cu Cu stud/mini bump CrCu Ni Ni Solder wettable layer Cu Cu Cu Cu Au Oxide prevention Au Au Au Cu Au Suitability for 63SnPb No Poor No Yes Yes Use with probed wafers No No No Yes Mixed In evaporated solder bumping process a metal mask (typically molybdenium) is used to make the deposition of UBM layers and the solder alloy onto a silicon wafer with normal passivation as well as polyimide passivation (see Figure B8). The process includes sequential evaporation of chromium, a phased chromium/copper layer, a copper layer and a gold layer to form the UBM. A high lead solder layer is then evaporated on top of the UBM to form a thick deposit of 97PbSn or 95PbSn. Figure B8. Evaporative solder bumping process [B3]. Electroplating is a popular alternative to the evaporation process because of its lower cost, facility and floor space requirements. One of the various process alternatives is schematically shown in Figure B9. The UBM materials used are typically TiW, Cu and Au sequentially sputtered or evaporated over the entire wafer. The UBM adheres to the wafer passivation as well as to the bond pads. Patterned photoresist is then applied to allow plating of copper minibump onto the UBM metallisation. A second mask allows then the formation of the plated solder bump, after which the photoresist is stripped. The UBM which is on the entire wafer is removed from the areas other than pad areas by wet etching. Finally the bumps are formed by reflow Figure B9. Solder bumping by electroplating process. The formation of the bump by stencil printing of solder paste is a practical process which is suited for many types of solder materials including 63SnPb. The UBM layers are deposited by sputtering. The first layer is sputtered aluminium followed by sputtered layers of Ni and Cu. A layer of photoresist is applied, patterned and developed. The Al, Ni and Cu-layers are then etched away except over the bond pad passivation openings. The photoresist is removed leaving the UBM over the pad areas. Solder paste is then printed onto pad areas and reflowed to form the spherical bumps. Figure B10. Sputtered UBM and solder paste bumping process. The company Flip Chip Technologies has design guide (http://www.flipchip.com), which gives advice for selecting between available bumping materials, explains the geometrical restrictions and die pad design standards, bump placement, resistance and shear test patterns, alignment key specification and placement as well as wafer passivation requirements. Various test die (peripheral or array type) and substrates available for evaluation and reliability testing. Compatibility of the solder material with the substrate material is very important. FR4-substrate, for example, can not stand the high temperature reflow temperature of Pb95/Sn5. If high temperature solder is used for bumps, low temperature solder alloy must be applied to the substrate to make possible a low temperature joining process. The minimum pitch obtained for perimeter pad layout is about 200  m whereas for the area array layout the minimum pitch is about 250  m. In almost all dies the pads are peripherally located because of the wire bonding applications. For flip chip bonding the number of I/O can be increased by applying area array pad layout. The redistribution of the pad layout from peripheral arrangement to area array arrangement is possible by doing extra redistribution circuitry onto the die prior to bumping process. Maximum current density for solder bumps is approximately 4200 A/cm2. Typical bump heights are 125 - 140  m depending of pitch and the bump height tolerance     