AD9284

8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9284 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. FEATURES Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold 1.2 V p-p analog input range for each channel Differential input with 500 MHz bandwidth LVDS-compliant digital output DNL: ±0.2 LSB Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Built-in selectable digital test pattern generation Pin-programmable power-down function Available in 48-lead LFCSP APPLICATIONS Communications Diversity radio systems I/Q demodulation systems Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber GENERAL DESCRIPTION The AD9284 is a dual 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports simultaneous operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance. The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible. The AD9284 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Integrated Dual 8-Bit, 250 MSPS ADC. 2. Single 1.8 V Supply Operation with LVDS Outputs. 3. Power-Down Option Controlled via a Pin-Programmable Setting. FUNCTIONAL BLOCK DIAGRAM AD9284 CLK+ CLK– VIN+A VIN–A VREF VCM ADC ADC SPI CLOCK MANAGEMENT VIN–B VIN+B SDIO/ PWDN OESCLKCSB LV D S O U TP U T B U FF ER LV D S O U TP U T B U FF ER ×1.5 1.0V VREF REF SELECT D7+ (MSB), D7– (MSB) D0+ (LSB), D0– (LSB) (CHANNEL A) D7+ (MSB), D7– (MSB) D0+ (LSB), D0– (LSB) (CHANNEL B) DCO GENERATION DCO+ DCO– RBIAS AGND AVDD DRVDD DRGND 09 08 5- 00 1 Figure 1. AD9284 Rev. 0 | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  DC Specifications ......................................................................... 3  AC Specifications.......................................................................... 4  Digital Specifications ................................................................... 5  Switching Specifications .............................................................. 6  SPI Timing Specifications ........................................................... 6  Absolute Maximum Ratings............................................................ 7  Thermal Resistance ...................................................................... 7  ESD Caution.................................................................................. 7  Pin Configuration and Function Descriptions............................. 8  Typical Performance Characteristics ........................................... 10  Equivalent Circuits ......................................................................... 12  Theory of Operation ...................................................................... 13  ADC Architecture ...................................................................... 13  Analog Input Considerations.................................................... 13  Voltage Reference ....................................................................... 13  RBIAS........................................................................................... 13  Clock Input Considerations...................................................... 14  Digital Outputs ........................................................................... 14  Built-In Self-Test (BIST) and Output Test .................................. 15  Built-In Self-Test (BIST)............................................................ 15  Output Test Modes..................................................................... 15  Serial Port Interface (SPI).............................................................. 16  Configuration Using the SPI..................................................... 16  Hardware Interface..................................................................... 17  Configuration Without the SPI ................................................ 17  SPI Accessible Features.............................................................. 17  Memory Map .................................................................................. 18  Reading the Memory Map Register Table............................... 18  Memory Map Register Table..................................................... 19  Memory Map Register Descriptions........................................ 21  Applications Information .............................................................. 22  Design Guidelines ...................................................................... 22  Outline Dimensions ....................................................................... 23  Ordering Guide .......................................................................... 23  REVISION HISTORY 1/11—Revision 0: Initial Version AD9284 Rev. 0 | Page 3 of 24 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted. Table 1. Parameter1 Temperature Min Typ Max Unit RESOLUTION Full 8 Bits DC ACCURACY Differential Nonlinearity Full ±0.2 ±0.4 LSB Integral Nonlinearity Full ±0.1 ±0.3 LSB No Missing Codes Full Guaranteed Offset Error Full 0 ±0.4 ±2.1 % FS Gain Error Full 0 ±2.5 ±2.8 % FS MATCHING CHARACTERISTICS Offset Error Full 0 ±0.5 ±2.6 % FS Gain Error Full 0 ±0.1 ±0.7 % FS TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±20 ppm/°C ANALOG INPUT Input Span Full 1.2 V p-p Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 16 kΩ Input Capacitance (Differential) Full 250 fF Full Power Bandwidth Full 700 MHz VOLTAGE REFERENCE Internal Reference Full 0.97 0.98 0.99 V Input Resistance Full 3 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current IAVDD Full 124 128 mA IDRVDD Full 51 54 mA POWER CONSUMPTION Sine Wave Input2 Full 314 330 mW Power-Down Power Full 0.3 1.7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. AD9284 Rev. 0 | Page 4 of 24 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, maximum sample rate, VIN = −1.0 dBFS differential input, unless otherwise noted. Table 2. Parameter Temperature Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz 25°C 49.3 dBFS fIN = 70 MHz 25°C 49.3 dBFS fIN = 96.6 MHz Full 48.7 49.3 dBFS fIN = 220 MHz 25°C 49.3 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 10.3 MHz 25°C 49.2 dBFS fIN = 70 MHz 25°C 49.2 dBFS fIN = 96.6 MHz Full 48.5 49.2 dBFS fIN = 220 MHz 25°C 49.2 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz 25°C 7.9 Bits fIN = 70 MHz 25°C 7.9 Bits fIN = 96.6 MHz Full 7.8 7.9 Bits fIN = 220 MHz 25°C 7.9 Bits WORST SECOND OR THIRD HARMONIC fIN = 10.3 MHz 25°C −70 dBc fIN = 70 MHz 25°C −70 dBc fIN = 96.6 MHz Full −70 −61 dBc fIN = 220 MHz 25°C −65 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10.3 MHz 25°C 70 dBc fIN = 70 MHz 25°C 70 dBc fIN = 96.6 MHz Full 61 69 dBc fIN = 220 MHz 25°C 65 dBc WORST OTHER HARMONIC OR SPUR fIN = 10.3 MHz 25°C −71 dBc fIN = 70 MHz 25°C −71 dBc fIN = 96.6 MHz Full −70 −64 dBc fIN = 220 MHz 25°C −67 dBc CROSSTALK Full −80 dBc AD9284 Rev. 0 | Page 5 of 24 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted. Table 3. Parameter1 Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/PECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage2 Full 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS CSB High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −5 −0.4 +5 μA Low Level Input Current Full −80 −63 −50 μA Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF SCLK, SDIO/PWDN, OE High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full 50 57 70 μA Low Level Input Current Full −5 −0.4 +5 μA Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS DRVDD = 1.8 V Differential Output Voltage (VOD) Full 290 345 400 mV Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V Output Coding (Default) Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 Specified for LVDS and LVPECL only. AD9284 Rev. 0 | Page 6 of 24 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 30 250 MHz CLK Period (tCLK) Full 7.4 ns CLK Pulse Width High (tCH) Full 3.7 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 3.7 ns DCO Propagation Delay (tDCO) Full 3.7 ns DCO to Data Skew (tSKEW) Full −280 −60 +100 ps Pipeline Delay (Latency) Full 10.5 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time1 Full 500 μs OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Wake-up time is dependent on the value of the decoupling capacitors. SPI TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns Timing Diagram M – 1 M + 1 M + 2 M + 5 M + 4 M + 3 M N – 1 N + 1 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 N – 7 N + 2 N + 5 N + 4 N + 3 N tA tCH tCLK tDCO tSKEW tPD VIN±A VIN±B CLK+ CLK– DCO+, DCO– CH A, CH B DATA CH A, CH B 09 08 5- 00 2 Figure 2. Output Data Timing AD9284 Rev. 0 | Page 7 of 24 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Electrical AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D7+/D7− to DRGND −0.3 V to DRVDD + 0.3 V DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.3 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V VIN±A, VIN±B to AGND −0.3 V to AVDD + 0.2 V SDIO/PWDN to DRGND −0.3 V to DRVDD + 0.3 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK to AGND −0.3 V to DRVDD + 0.3 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type θJA θJC Unit 48-Lead LFCSP (CP-48-12) 30.4 2.9 °C/W ESD CAUTION AD9284 Rev. 0 | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 13 14 15 16 17 18 19 20 21 22 23 24 D 2– D 2+ D 3– D 3+ D C O – D C O + D 4– D 4+ D 5– D 5+ D 6– D 6+ 48 47 46 45 44 43 42 41 40 39 38 37 A VD D VI N –B VI N +B A VD D A VD D VR EF A VD D VC M A VD D VI N +A VI N –A A VD D 1 2 3 4 5 6 7 8 9 10 11 12 AVDD AVDD DNC DNC RBIAS DNC DRGND DRVDD D0– (LSB) D0+ (LSB) D1– D1+ AVDD CLK+ CLK– CSB SDIO/PWDN SCLK OE DRGND DRVDD D7+ (MSB) D7– (MSB) 35 AVDD36 34 33 32 31 30 29 28 27 26 25 AD9284 TOP VIEW (Not to Scale) PIN 1 INDICATOR NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 09 08 5- 00 3 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description ADC Power Pins 1, 2, 35, 36, 37, 40, 42, 44, 45, 48 AVDD Supply Analog Power Supply (1.8 V Nominal). 8, 27 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 7, 28 DRGND Ground Digital Output Ground. 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. ADC Analog Pins 39 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 46 VIN+B Input Differential Analog Input Pin (+) for Channel B. 47 VIN−B Input Differential Analog Input Pin (−) for Channel B. 43 VREF Input/output Voltage Reference Input/Output. 5 RBIAS Input/output External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND. 41 VCM Output Common-Mode Level Bias Output for Analog Inputs. 34 CLK+ Input ADC Clock Input—True. 33 CLK− Input ADC Clock Input—Complement. Digital Input 29 OE Input Digital Enable (Active Low) to Tristate Output Data Pins. Digital Outputs 26 D7+ (MSB) Output Channel A/Channel B LVDS Output Data 7—True. 25 D7− (MSB) Output Channel A/Channel B LVDS Output Data 7—Complement. 24 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 23 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 22 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 21 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 20 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 19 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. AD9284 Rev. 0 | Page 9 of 24 Pin No. Mnemonic Type Description 16 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 14 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 12 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 10 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 9 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 18 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 17 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control Pins 30 SCLK Input SPI Serial Clock. 31 SDIO/PWDN Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). 32 CSB Input SPI Chip Select (Active Low). Do Not Connect 3, 4, 6 DNC N/A Do Not Connect. Do not connect to this pin. AD9284 Rev. 0 | Page 10 of 24 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, unless otherwise noted. 0 –20 –40 –60 –80 –100 –120 0 25 50 75 100 125 A M PL IT U D E (d B FS ) FREQUENCY (MHz) 250MSPS 4.3MHz @ –1dBFS SNR = 48.3dB (49.3dBFS) ENOB = 7.7 SFDR = 70.3dBc SECOND HARMONIC THIRD HARMONIC 09 08 5- 10 7 Figure 4. Single-Tone FFT with fIN = 4.3 MHz 0 –20 –40 –60 –80 –100 –120 0 25 50 75 100 125 A M PL IT U D E (d B FS ) FREQUENCY (MHz) 250MSPS 330.3MHz @ –1dBFS SNR = 48.2dB (49.2dBFS) ENOB = 7.6 SFDR = 60.9dBc SECOND HARMONICTHIRD HARMONIC 09 08 5- 10 8 Figure 5. Single-Tone FFT with fIN = 220.3 MHz 80 60 70 50 40 30 20 10 0 –45 0–5–10–15–20–25–30–35–40 SF D R /S N R (d B ) AIN POWER (dBFS) SFDR (dBFS) SNR (dBFS) SFDR (dBc) SNR (dBc) REFERENCE LINE 09 08 5- 10 9 Figure 6. SFDR/SNR vs. Input Amplitude (AIN) with fIN = 2.2 MHz 0 –20 –40 –60 –80 –100 –120 0 25 50 75 100 125 A M PL IT U D E (d B FS ) FREQUENCY (MHz) 250MSPS 96.6MHz @ –1dBFS SNR = 48.3dB (49.3dBFS) ENOB = 7.7 SFDR = 70.0dBc SECOND HARMONIC THIRD HARMONIC 09 08 5- 11 0 Figure 7. Single-Tone FFT with fIN = 96.6 MHz 0 –20 –40 –60 –80 –100 –120 0 25 50 75 100 125 A M PL IT U D E (d B FS ) FREQUENCY (MHz) 250MSPS 29.2MHz @ –7dBFS 32.2MHz @ –7dBFS SFDR = 69.6dBc (76.6dBFS) 09 08 5- 11 1 Figure 8. Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz 80 60 70 50 40 30 20 10 0 –45 0–5–10–15–20–25–30–35–40 SF D R /IM D 3 (d B ) AIN POWER (dBFS) IMD3 (dBFS) SFDR (dBFS) IMD3 (dBc) SFDR (dBc) 09 08 5- 11 2 Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz AD9284 Rev. 0 | Page 11 of 24 75 70 65 60 55 50 50.0 49.8 49.6 49.4 49.2 49.0 50 25022520017515012510075 SF D R (d B c) SN R