TND313-D

1 TND313/D Rev. 0, Aug-05 High-Efficiency, 80 PLUS Compliant 250 W ATX Reference Design Documentation Package © 2005 ON Semiconductor. 2 Disclaimer: ON Semiconductor is providing this reference design documentation package “AS IS” and the recipient assumes all risk associated with the use and/or commercialization of this design package. No licenses to ON Semiconductor’s or any third party’s Intellectual Property is conveyed by the transfer of this documentation. This reference design documentation package is provided only to assist the customers in evaluation and feasibility assessment of the reference design. The design intent is to demonstrate that an ATX efficiency of 80% plus is possible utilizing ON Semiconductor power control ICs and other standard, inexpensive components. It is expected that users may make further refinements to meet specific performance goals. 3 Overview............................................................................................................................. 4 1. Specifications............................................................................................................. 5 2. Architecture Overview............................................................................................... 5 3. Performance Results .................................................................................................. 6 4. Evaluation Guidelines.............................................................................................. 11 5. Comparison to Traditional ATX Solutions.............................................................. 13 6. Schematics ............................................................................................................... 15 7. Gerber Files.............................................................................................................. 18 8. Parts List .................................................................................................................. 21 9. Critical Component Information.............................................................................. 24 10. Required/Suggested Changes................................................................................... 25 11. Resources/Contact Information ............................................................................... 27 12. Appendix…………………………………………………………………………...28 4 Overview This reference document describes a built-and-tested, GreenPointTM solution for an ATX power supply, which exceeds the efficiency requirements of the new 80 PLUS program for desktop computers. At the time of publication, this is the first documented open reference design for 80 PLUS requirements. Use of advanced new components from ON Semiconductor enabled the development of this efficient, integrated and cost effective power architecture. The reference design circuit consists of two double-sided 144 mm x 109 mm printed circuit boards designed to fit into the ATX enclosure with a fan. The Input Board incorporates the input filter, rectifier, active power factor correction (PFC) circuit, standby regulation circuit and supervisory/monitoring circuit. The Output Board consists of the isolated step-down converter and rectification circuitry for desired output voltages (including post-regulation control for 3.3 V). An overview of the entire circuit is provided by Figure 1. As shown in that figure, ON Semiconductor devices are available for every functional block of the ATX power supply; and by judicious choice of design tradeoffs, optimum performance is achieved at minimum cost. Figure 1. ON Semiconductor’s proposed ATX architecture block diagram 5 1. Specifications The design closely follows the ATX12V power supply guidelines and specifications available from www.formfactors.org. Key specifications are outlined below: Input Voltage: 90-264 Vac, 47-63 Hz Output 1: 12 V +/- 5%, 1 A - 20 A (max ripple/noise: 120 mV pp) Output 2: 5 V +/- 5%, 0.3 A - 18 A (max ripple/noise: 50 mV pp) Output 3: 3.3 V +/- 5%, 0.5 A - 17 A (max ripple/noise: 50 mV pp) Output 4: -12 V +/- 10%, 0 A – 0.3 A (max ripple/noise: 120 mV pp) Output 5: 5 VSB +/- 5%, 0 A - 2 A (max ripple/noise: 50 mV pp) Combined maximum output power of Output 2 and Output 3 is 115 W. Total maximum output of the power supply is 250 W. The power supply shall meet the IEC1000-3-2 requirements over the input line range and under full load conditions. The power supply shall meet minimum 80% efficiency requirements for 20%, 50% and 100% load conditions as defined by the 80 PLUS requirements. Also, per the 80 PLUS requirement, it shall have a power factor of 0.9 or greater at 100 % load. Hold-up time: 20 ms minimum. OVP, UVP and OCP per ATX12V specifications. Physical size: Must fit within the ATX enclosure (150 mm x 140 mm x 86 mm). 2. Architecture Overview In order to meet the 80 PLUS requirements, a different overall power architecture was selected for the power supply. First, the use of active power factor correction in the front-end allows system optimization because the PFC output voltage is well regulated. The implementation of the active PFC front end is made simpler by using the NCP1653, an 8-pin continuous conduction mode (CCM) PFC controller. By choosing the CCM approach for PFC, the peak and rms currents are kept low and better efficiency is achieved in the PFC stage. The output of the PFC stage is set at 385 V. The SMPS stage uses an active clamp forward topology. This topology offers a number of advantages as demonstrated in the schematics and the results. It improves efficiency, eliminates snubbers and provides better switch utilization. The NCP1280 controller and 6 MC33152 driver are used to implement the most effective control scheme of the active clamp topology. The turns ratio used is 18:1 for 5 V output and 11.2:1 for 12 V output. The 5 V and 12 V outputs use synchronous rectification to improve efficiency. The use of optimized turns ratio allows use of lowest voltage MOSFETs for each output. In addition, the 12 V, -12 V and 5 V output inductors are coupled on a single core to achieve better cross-regulation and ripple reduction. The feedback signal is summed from both 5 V and 12 V to achieve additional regulation tracking. The -12 V output does not use synchronous rectification. In order to achieve better ripple performance and a smaller output filter, the switching frequency is selected at 200 kHz. In order to achieve the desired regulation on the 3.3 V output, post-regulation is needed. In place of the traditional mag-amp circuit, a switching post-regulator is used. This circuit uses synchronous MOSFETs and an NCP4330 as the controller/driver for the MOSFETs. As a result of this approach, an efficiency gain of 1-2% is achieved. For the standby output circuit, a higher integration level is made feasible by using the NCP1014, a PWM regulator that also incorporates an appropriate switch to provide all functionality in one package. The use of the true current mode control technique in NCP1014 allows better regulation of the standby power supply. The output voltage monitoring and system interface is eased by using the NCP112, a supervisory IC that can monitor the main outputs and provide appropriate flags and OV/UV shutdown. In summary, the architecture selected for this reference design allows design optimization so that the desired performance is achieved without increasing the component costs and circuit complexity too much. The performance results section demonstrates the performance, and the indication of cost differential is given in Section 5. 3. Performance Results The evaluation of the reference design encompasses several areas including efficiency, power dissipation, active clamp stage and output voltage ripple. Please be aware that this evaluation is provided to demonstrate the effectiveness of the architecture. It is the users’ responsibility to ensure the system meets all their requirements. The converter efficiency is measured at the 80 PLUS program recommended operating conditions as detailed in Table 1. The converter efficiency is measured at the worst condition, 115 Vac. The converter achieves over 80% efficiency over all load conditions as shown in Figure 2. Please note that the output voltages used for the efficiency calculations are measured at the end of the power cables. If the voltage is measured at the output of the board, efficiency will improve at higher loads. Eight GND 18-gauge wires and four 20-gauge wires are provided for each of the +3.3 V, +5 V and +12 V connections. 7 Table 1. 80 PLUS Program Test Conditions Output Current (A) Load 12 V 5 V 3.3 V -12 V 5 V Stby 20 % 2.7 2.0 1.9 0.0 0.3 50 % 6.7 4.9 4.7 0.1 0.7 100 % 13.4 9.9 9.3 0.2 1.4 70 80 90 0 20 40 60 80 100 Percentage Load (%) Ef fic ie nc y (% ) Figure 2. Efficiency vs. percentage load The thermal efficiency of the converter is evaluated using an infrared camera. Measurements are done at room temperature without a fan. Figures 3 and 4 show thermal measurements of the system boards at 20% and 100% load at low line. Figures 5 and 6 show the system boards at 20% and 100% load at high line. A maximum temperature of 125 °C is observed on the PFC switch at full load at the minimum input voltage. It is apparent that external cooling and/or additional heatsink are needed. The system exhibits thermal stability when operated in an enclosed plastic case with a fan connected from the 5 V output. Figure 3. Thermal performance at 115 Vac at 20% load 8 Figure 4. Thermal performance at 115 Vac at 100% load Figure 5. Thermal performance at 230 Vac at 20% load Figure 6. Thermal performance at 230 Vac at 100% load 9 The drain voltage of the power switch (X1) at 20% and 100% load is shown in Figure 7. The power switch is rated at a maximum voltage 800 V. The peak or ripple voltage observed on the drain waveform is determined by the active clamp capacitor. The active clamp capacitor in this design is selected such that the drain voltage is limited to 680 V, or 15% of the rated voltage of X1. A lower ripple voltage is achieved with a lower capacitor. However, the active clamp capacitor should not be made arbitrarily large because it will move the RHP zero introduced by the active clamp to a lower frequency, making frequency compensation difficult. The power switch turns on when the drain voltage is a little less than 300 V, for an input voltage of 385 V. Therefore, reduced switching losses are obtained. A lower drain voltage at the switching point can be achieved by adding an external inductor in series with the transformer. However, this will require a larger operating duty cycle. The small glitch observed at 100% load can be reduced by adjusting the non-overlap time delay. Figure 7. Power switch drain waveforms 10 The output voltage ripple at 20% load for the 3.3 V, 5 V and 12 V outputs is shown in Figure 8-10. The target output voltage ripple is 120 mV for the 12 V output and 50 mV for the remaining outputs. A coupled choke is used for the 5 V and 12 V outputs, resulting in very low ripple. The ripple of the 3.3 V output is within spec, but it can be further reduced by adding more capacitance on the output or adding a small LC filter. A place holder for an LC filter was added on the Output Board if the user decides to add the filter. Figure 8. 3.3 V output voltage ripple Figure 9. 5 V output voltage ripple 11 Figure 10. 12 V output voltage ripple 4. Evaluation Guidelines Evaluation of the reference design should be attempted only by persons who are intimately familiar with power conversion circuitry. Lethal mains referenced voltages and high dc voltages are present within the primary section of the ATX circuitry. All testing should be done using a mains high-isolation transformer to power the demonstration unit so that appropriate test equipment probing will not affect or potentially damage the test equipment or the ATX circuitry. The evaluation engineer should also avoid connecting the ground terminal of oscilloscope probes or other test probes to floating or switching nodes (e.g. the source of the active clamp MOSFET X8). High impedance, low capacitance test probes should be used where appropriate for minimal interaction with the circuits under investigation. Particular care should be taken when probing the high impedance input pins of the NCP1653 power factor controller and especially the NCP1280 active clamp controller. As with all sensitive switchmode circuitry, the power supply under test should be switched off from the ac mains whenever the test probes are connected and/or disconnected. A minimum load of 1 A should always be present on each of the 5 V and 12 V outputs. The 3.3 V output does not have a minimum load requirement and a preload resistor is included in the -12 V output. All the outputs with the exception of the 3.3 V and 5 V standby are rated at a maximum current of 15 A. The Input Board containing the power factor corrector and standby supply circuitry can be evaluated separately by disconnecting the wiring from the two printed circuit boards. The NCP1014 standby flyback converter will be operational as long as there is ac mains voltage applied to the Input Board. This auxiliary converter can be evaluated by merely applying the mains voltage to the board. The NCP112 enable input and monitoring circuitry will have to be disabled, however, to evaluate the power factor corrector 12 circuitry separately. The NCP112 circuitry will normally cause a shutdown of the PFC (and the main converter) if the 3.3 V, the 5 V and the 12 V outputs are not sensed at their nominal voltage (see ON Semiconductor data sheet for the NCP112). The disabling of the enable input and monitor/shutdown can be accomplished by soldering a jumper wire across pins 3 and 4 of optocoupler U3 on this board. This will allow immediate operation of the PFC circuit when the unit is powered up from the mains. The 3.3 V output and the associated NCP4330 controller can be disabled by removing the jumper wire that connects the controller’s Vdd bias rail to the +12 V output. Although the primary current sense circuitry of the NCP1280 in conjunction with the NCP112 monitor chip will protect the power supply from accidental short circuits, it is not recommended that abrupt “crowbar” type shorts be applied to the ATX outputs. Such abrupt short circuits can potentially damage the output capacitors and synchronous rectifier MOSFETs if applied excessively due to unpredictable transients and/or voltage reversals caused by resonant action of the output LC circuits. It should be noted that individual current limit circuitry does not exist on the demonstration unit’s outputs and the supply relies on the peak inverter current detector (transformer TX3) to protect the supply from overloads. The evaluating engineer should also be aware of the idiosyncrasies of constant current type electronic loads when powering up the ATX demonstration unit. If the loads are adjusted to be close to the ATX’s maximum rated output power, the unit could shut down at turn on due to the instantaneous overloading effect of the constant current loads. As a consequence, electronic loads should be set to constant resistance mode or rheostats should be used for loads. The other alternative is to start the supply at light to medium load and then increase the constant current electronic loads to the desired level. The boards are mechanically designed to fit in a traditional ATX enclosure by stacking on top of each other as shown in Figure 11. However, they can also stand side by side to facilitate evaluation in a lab environment as shown in Figure 12. 13 Figure 11. ATX solution boards in ATX enclosure Figure 12. ATX solutions boards side by side for evaluation 5. Comparison to Traditional ATX Solutions The new architecture used in this reference design compares very favorably to the traditional ATX designs. A detailed comparison was made to the traditional ATX design which incorporates a passive PFC and a 1-switch forward converter. The efficiency results of the traditional solution are plotted in Figure 13. 14 70 80 90 0 20 40 60 80 100 Percentage Load (%) Ef fic ie nc y (% ) Figure 13. Traditional ATX power supply efficiency The traditional solution has the advantages of well understood operation and minimum cost structure due to volume utilization. However, if a detailed comparison of the total costs is made, the differential in cost between the traditional solution and this reference design is estimated to be about 10% (~$1.25). As the reference design is adapted for mass production, it is expected that experienced power supply designers will be able to achieve further cost optimization. ON Semiconductor is also working on further device developments to provide higher levels of integration and performance in order to optimize the costs for this approach. Following are a few of the factors that facilitate competitive cost structure for the reference design: • Use of active PFC reduces the stresses on the second stage components and allows universal ac input without switches. • Use of active PFC reduces the high voltage capacitance requirements to meet holdup requirements. • Use of NCP1653 in active PFC minimizes the control circuit costs. • Use of NCP112 for enable/monitor functions eliminates use of multiple discrete components and saves printed circuit board space. • Use of NCP1280 and active clamp topology minimizes the primary FET requirements compared to 1-switch forward converter. • Use of active clamp topology minimizes the voltage stresses on secondary rectifiers and allows the use of lower cost components. • Use of active clamp topology eliminates most of the snubbers and reduces heat sink size and costs. • Use of switching post regulator reduces the discrete circuitry required for generating the 3.3 V output. 15 • Higher level of integration offered by NCP1653, NCP1280, NCP4330, NCP112 and NCP1014 reduces the total BOM cost and manufacturing costs. 6. Schematics This design is implemented using two dedicated boards. The Input Board includes the PFC, supervisory and 5 V standby circuits, and the Output Board includes the 3.3 V, 5 V, 12 V and -12 V converters. The circuit schematics for the Input and Output Boards are shown in Figure 14 and Figure 15, respectively. Multiple connections are required between the boards. The connections are indicated with this symbol “ ”. Also, a few changes were required after the initial prototype boards were built. The changes are highlighted in red in the schematic. 16 Figure 14. Input Board circuit schematic R 21 22 5V _S TB 1 S TB Y _R TN 1 R 16 1K R 24 33 K R 12 47 0K R 3 0. 1 2 W + C 6 20 0/ 45 0V C 21 10 nF R 27 7. 5k L4 10 69 4- L4 3- 3V 1 (1 5V ) D 4 M B R D 35 0 C 2 4. 7n f " Y " N C P 10 14 U 4 1 23 4 1 23 4 R 2 4. 7M 1 /2 W R 20 12 0K 1 W C 26 2. 2n f 40 0V R 25 10 0K R 5 10 K C 23 10 nf Q 2 2N 29 07 3 2 1 + C 24 10 0u f 10 V D 1 M S R 86 0 U 5 H 11 A 81 7A 1 2 4 3 R 9 56 0K C 13 1n F N 1 C 1 1uf 250VAC C 14 10 0n F D 2 1N 54 06 C 20 10 nF U 3 H 11 A 81 7A 1 2 4 3 C O M 1 R 19 47 0 R 18 4. 7K 12 V 1 R 22 22 k C 31 0. 1 C 19 10 nF R 23 10 0K + C 30 10 uf 1 6V R 26 10 K C 5 0. 1u