74HC161

TL/F/5008 7 4 H C 1 6 0 / M M 5 4 / 7 4 H C 1 6 1 / M M 5 4 / 7 4 H C 1 6 2 / M M 5 4 / 7 4 H C 1 6 3 January 1992 MM74HC160 Synchronous Decade Counter with Asynchronous Clear MM54HC161/MM74HC161 Synchronous Binary Counter with Asynchronous Clear MM54HC162/MM74HC162 Synchronous Decade Counter with Synchronous Clear MM54HC163/MM74HC163 Synchronous Binary Counter with Synchronous Clear General Description The MM54HC160/MM74HC160 , MM54HC161/ MM74HC161 , MM54HC162 /MM74HC162 , a n d MM54HC163/MM74HC163 synchronous presettable count- ers utilize advanced silicon-gate CMOS technology and in- ternal look-ahead carry logic for use in high speed counting applications. They offer the high noise immunity and low power consumption inherent to CMOS with speeds similar to low power Schottky TTL. The ’HC160 and the ’HC162 are 4 bit decade counters, and the ’HC161 and the ’HC163 are 4 bit binary counters. All flip-flops are clocked simultaneous- ly on the low to high transition (positive edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Pre- setting of all four flip-flops is synchronous to the rising edge of CLOCK. When LOAD is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken high before the positive edge of CLOCK the count operation will be unaffected. All of these counters may be cleared by utilizing the CLEAR input. The clear function on the MM54HC162/MM74HC162 and MM54HC163/MM74HC163 counters are synchronous to the clock. That is, the counters are cleared on the posi- tive edge of CLOCK while the clear input is held low. The MM54HC160/MM74HC160 and MM54HC161/ MM74HC161 counters are cleared asynchronously. When the CLEAR is taken low the counter is cleared immediately regardless of the CLOCK. Two active high enable inputs (ENP and ENT) and a RIP- PLE CARRY (RC) output are provided to enable easy cas- cading of counters. Both ENABLE inputs must be high to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implemen- tation of N-bit counters. All inputs are protected from damage due to static dis- charge by diodes to VCC and ground. Features Y Typical operating frequency: 40 MHz Y Typical propagation delay; clock to Q: 18 ns Y Low quiescent current: 80 mA maximum (74HC Series) Y Low input current: 1 mA maximum Y Wide power supply range: 2–6V Connection Diagram TL/F/5008–1 Order Number MM54HC161/162/163 or MM74HC160/161/162/163 Truth Tables ’HC160/HC161 CLK CLR ENP ENT Load Function X L X X X Clear X H H L H Count & RC disabled X H L H H Count disabled X H L L H Count & RC disabled u H X X L Load u H H H H Increment Counter H e high level, L e low level X e don’t care, u e low to high transition ’HC162/HC163 CLK CLR ENP ENT Load Function u L X X X Clear X H H L H Count & RC disabled X H L H H Count disabled X H L L H Count & RC disabled u H X X L Load u H H H H Increment Counter C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A. Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) b0.5 to a7.0V DC Input Voltage (VIN) b1.5 to VCCa1.5V DC Output Voltage (VOUT) b0.5 to VCCa0.5V Clamp Diode Current (IIK, IOK) g20 mA DC Output Current, per pin (IOUT) g25 mA DC VCC or GND Current, per pin (ICC) g50 mA Storage Temperature Range (TSTG) b65§C to a150§C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§C Operating Conditions Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V (VIN, VOUT) Operating Temp. Range (TA) MM74HC b40 a85 §C MM54HC b55 a125 §C Input Rise or Fall Times VCCe2.0V(tr, tf) 1000 ns VCCe4.5V 500 ns VCCe6.0V 400 ns DC Electrical Characteristics (Note 4) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits VIH Minimum High Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V Input Voltage** 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VOH Minimum High Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VINeVIH or VIL lIOUTls4.0 mA 4.5V 4.2 3.98 3.84 3.7 V lIOUTls5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum Low Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VINeVIH or VIL lIOUTls4.0 mA 4.5V 0.2 0.26 0.33 0.4 V lIOUTls5.2 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA Current ICC Maximum Quiescent VINeVCC or GND 6.0V 8.0 80 160 mA Supply Current IOUTe0 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§C to 85§C; ceramic ‘‘J’’ package: b12 mW/§C from 100§C to 125§C. Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCCe5V, TAe25§C, CLe15 pF, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units fMAX Maximum Operating Frequency 43 30 MHz tPHL, tPLH Maximum Propagation Delay, Clock to RC 30 35 ns tPHL, tPLH Maximum Propagation Delay, Clock to Q 29 34 ns tPHL, tPLH Maximum Propagation Delay, ENT to RC 18 32 ns tPHL Maximum Propagation Delay, Clear to Q or RC 27 38 ns tREM Minimum Removal Time, Clear to Clock 10 20 ns tS Minimum Set Up Time Clear, Load, 30 ns Enable or Data to Clock tH Minimum Hold Time, Data from Clock 5 ns tW Minimum Pulse Width Clock, 16 ns Clear, or Load AC Electrical Characteristics CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits fMAX Maximum Operating 2.0V 10 5 4 4 MHz Frequency 4.5V 40 27 21 18 MHz 6.0V 45 32 25 21 MHz tPHL Maximum Propagation 2.0V 100 215 271 320 ns Delay, Clock to RC 4.5V 32 43 54 64 ns 6.0V 28 37 46 54 ns tPLH Maximum Propagation 2.0V 88 175 220 260 ns Delay, Clock to RC 4.5V 18 35 44 52 ns 6.0V 15 30 37 44 ns tPHL Maximum Propagation 2.0V 95 205 258 305 ns Delay, Clock to Q 4.5V 30 41 52 61 ns 6.0V 26 35 44 52 ns tPLH Maximum Propagation 2.0V 85 170 214 253 ns Delay, Clock to Q 4.5V 17 34 43 51 ns 6.0V 14 29 36 43 ns tPHL Maximum Propagation 2.0V 90 195 246 291 ns Delay, ENT to RC 4.5V 28 39 49 58 ns 6.0V 24 33 42 49 ns tPLH Maximum Propagation 2.0V 80 160 202 238 ns Delay, ENT to RC 4.5V 16 32 40 48 ns 6.0V 14 27 34 41 ns tPHL Maximum Propagation 2.0V 100 220 275 325 ns Delay, Clear to RC 4.5V 32 44 55 66 ns 6.0V 28 37 47 55 ns tPHL Maximum Propagation 2.0V 100 210 260 315 ns Delay, Clear to Q 4.5V 32 42 52 63 ns 6.0V 28 36 45 54 ns tREM Minimum Removal Time 2.0V 125 158 186 ns Clear to Clock 4.5V 25 32 37 ns 6.0V 21 27 32 ns tS Minimum Setup 2.0V 150 190 225 ns Time Clear or Data 4.5V 30 38 45 ns to Clock 6.0V 26 32 38 ns tS Minimum Setup 2.0V 135 170 200 ns Time Load 4.5V 27 34 41 ns to Clock 6.0V 23 29 35 ns tS Minimum Setup 2.0V 175 220 260 ns Time Enable 4.5V 35 44 52 ns to Clock 6.0V 30 37 44 ns tH Minimum Hold Time 2.0V 50 63 75 ns Data from Clock 4.5V 10 13 15 ns 6.0V 9 11 13 ns 3 AC Electrical Characteristics (Continued) CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits tH Minimum Hold Time 2.0V 0 0 0 ns Enable, Load or Clear 4.5V 0 0 0 ns to Clock 6.0V 0 0 0 ns tW Minimum Pulse Width 2.0V 80 100 120 ns Clock, Clear, or 4.5V 16 20 24 ns Load 6.0V 14 17 20 ns tTLH, tTHL Maximum 2.0V 40 75 95 110 ns Output Rise and 4.5V 8 15 19 22 ns Fall Time 6.0V 7 13 16 19 ns tr, tf Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time 4.5V 500 500 500 ns 6.0V 400 400 400 ns CPD Power Dissipation (per package) 90 pF Capacitance (Note 5) CIN Maximum Input Capacitance 5 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. Logic Diagrams MM54HC160/MM74HC160 or MM54HC162/MM74HC162 TL/F/5008–2 MM54HC161/MM74HC161 or MM54HC163/MM74HC163 TL/F/5008–3 4 Logic Waveforms 160, 162 Synchronous Decade Counters Typical Clear, Preset, Count and Inhibit Sequences Sequence: TL/F/5008–4 (1) Clear outputs to zero (2) Preset to BCD seven (3) Count to eight, nine, zero, one, two, and three (4) Inhibit 161, 163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences Sequence: TL/F/5008–5 (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit 5 7 4 H C 1 6 0 / M M 5 4 / 7 4 H C 1 6 1 / M M 5 4 / 7 4 H C 1 6 2 / M M 5 4 / 7 4 H C 1 6 3 Physical Dimensions inches (millimeters) Order Number MM54HC160J, MM54HC161J, MM54HC162J, MM54HC163J, MM74HC160J, MM74HC161J, MM74HC162J, MM74HC163J NS Package J16A Order Number MM74HC160N, MM74HC161N, MM74HC162N, MM74HC163N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. 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