OB2269_icpdf

©On-Bright Electronics Confidential - 1 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling GENERAL DESCRIPTION OB2269C is a highly integrated current mode PWM control IC optimized for high performance, low standby power and cost effective offline flyback converter applications. PWM switching frequency at normal operation is externally programmable and trimmed to tight range. At no load or light load condition, the IC operates in extended ‘burst mode’ to minimize switching loss. Lower standby power and higher conversion efficiency is thus achieved. VDD low startup current and low operating current contribute to a reliable power on startup design with OB2269C. A large value resistor could thus be used in the startup circuit to minimize the standby power. The internal slope compensation improves system large signal stability and reduces the possible sub- harmonic oscillation at high PWM duty cycle output. Leading-edge blanking on current sense input removes the signal glitch due to snubber circuit diode reverse recovery. This greatly helps to reduce the external component count and system cost in application. OB2269C offers complete protection coverage with automatic self-recovery feature including Cycle-by- Cycle current limiting (OCP), over load protection (OLP), over temperature protection (OTP), VDD over voltage protection (OVP) and under voltage lockout (UVLO). The Gate-drive output is clamped at 18V to protect the power MOSFET. In OB2269C, OCP threshold slope is internally optimized to reach constant output power limit over universal AC input range. Excellent EMI performance is achieved with On- Bright proprietary frequency shuffling technique together with soft switching control at the totem pole gate drive output. The tone energy at below 20KHZ is minimized in operation. Consequently, audio noise performance is greatly improved. OB2269C is offered in both SOP-8 and DIP-8 packages. FEATURES ■ On-Bright Proprietary Frequency Shuffling Technology for Improved EMI Performance ■ Extended Burst Mode Control For Improved Efficiency and Minimum Standby Power Design ■ Audio Noise Free Operation ■ External Programmable PWM Switching Frequency ■ Internal Synchronized Slope Compensation ■ Low VIN/VDD Startup Current(6.5uA) and Low Operating Current (2.3mA) ■ Leading Edge Blanking on Current Sense Input ■ Complete Protection Coverage With Auto Self- Recovery o External Programmable Over Temperature Protection (OTP) o With or Without On-chip VDD OVP for System OVP o Under Voltage Lockout with Hysteresis (UVLO) o Gate Output Maximum Voltage Clamp (18V) o Line Compensated Cycle-by-Cycle Over- current Threshold Setting For Constant Output Current Limiting Over Universal Input Voltage Range (OCP) o Over Load Protection. (OLP) APPLICATIONS Offline AC/DC flyback converter for ■ Laptop Power Adaptor ■ PC/TV/Set-Top Box Power Supplies ■ Open-frame SMPS ■ Battery Charger TYPICAL APPLICATION On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 2 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling GENERAL INFORMATION Pin Configuration The OB2269C is offered in DIP and SOP packages shown as below. Ordering Information Part Number Description OB2269CAP With Frequency Shuffling, DIP8, Pb-free OB2269CAPV With Frequency Shuffling, DIP8, Pb-free, no OVP OB2269CCP With Frequency Shuffling, SOP8, Pb-free OB2269CCPV With Frequency Shuffling, SOP8, Pb-free, no OVP Package Dissipation Rating Package RθJA (°C/W) DIP8 90 SOP8 150 Absolute Maximum Ratings Parameter Value VDD/VIN DC Supply Voltage 30 V VDD Zener Clamp VoltageNote VDD_Clamp+0.1V VDD Clamp Continuous Current 10 mA VFB Input Voltage -0.3 to 7V VSENSE Input Voltage to Sense Pin -0.3 to 7V VRT Input Voltage to RT Pin -0.3 to 7V VRI Input Voltage to RI Pin -0.3 to 7V Min/Max Operating Junction Temperature TJ -20 to 150 oC Min/Max Storage Temperature Tstg -55 to 150 oC Lead Temperature (Soldering, 10secs) 260 oC Note: VDD_Clamp has a nominal value of 35V. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 3 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling Marking Information TERMINAL ASSIGNMENTS Pin Num Pin Name I/O Description 1 GND P Ground 2 FB I Feedback input pin. PWM duty cycle is determined by voltage level into this pin and current-sense signal level at Pin 6. 3 VIN I Connected through a large value resistor to rectified line input for Startup IC supply and line voltage sensing. 4 RI I Internal Oscillator frequency setting pin. A resistor connected between RI and GND sets the PWM frequency. 5 RT I Temperature sensing input pin. Connected through a NTC resistor to GND. 6 SENSE I Current sense input pin. Connected to MOSFET current sensing resistor node. 7 VDD P DC power supply pin. 8 GATE O Totem-pole gate drive output for power MOSFET. On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 4 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling BLOCK DIAGRAM RECOMMENDED OPERATING CONDITION Symbol Parameter Min Max Unit VDD VDD Supply Voltage 12 23 V RI RI Resistor Value 24 31 Kohm TA Operating Ambient Temperature -20 85 oC On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 5 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling ESD INFORMATION Symbol Parameter Test Conditions Min Typ Max Unit HBMNote Human Body Model on All Pins Except VIN and VDD MIL-STD 3 KV MM Machine Model on All Pins JEDEC-STD 250 V Note: HBM all pins pass 3KV except High Voltage Input pin. The details are VIN passes 1kV, VDD passes 1.5KV, all other I/Os pass 3KV. In system application, High Voltage Input pin is either a high impedance input or connected to a cap. The lower rating has minimum impacts on system ESD performance. ELECTRICAL CHARACTERISTICS (TA = 25OC, VDD=16V, RI=24Kohm if not otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit Supply Voltage (VDD) I_VDD_Startup VDD Start up Current VDD =15V, Measure current into VDD 6.5 20 uA I_VDD_Operation Operation Current VFB=3V 2.3 mA UVLO(Enter) VDD Under Voltage Lockout Enter 9.5 10.5 11.5 V UVLO(Exit) VDD Under Voltage Lockout Exit (Startup) 15.5 16.5 17.5 V OVP(ON)*Optional VDD Over Voltage Protection Enter 23.5 25 26.5 V OVP(OFF)*Optional VDD Over Voltage Protection Exit (Recovery) 21.5 23 24.5 V OVP_Hys*Optional OVP Hysteresis OVP(ON)-OVP(OFF) 2 V TD_OVP VDD OVP Debounce time 80 uSec VDD_Clamp VDD Zener Clamp Voltage I(VDD ) = 5mA 35 V Feedback Input Section(FB Pin) AVCS PWM Input Gain ΔVFB /ΔVcs 2.8 V/V VFB_Open VFB Open Voltage 5.9 V IFB_Short FB pin short circuit current Short FB pin to GND, measure current 0.80 mA VTH_0D Zero Duty Cycle FB Threshold Voltage 0.95 V VTH_BM Burst Mode FB Threshold Voltage 1.7 V VTH_PL Power Limiting FB Threshold Voltage 4.4 V TD_PL Power limiting Debounce Time 80 mSec ZFB_IN Input Impedance 7.2 Kohm Current Sense Input(Sense Pin) T_blanking Sense Input Leading Edge Blanking Time 250 nS ZSENSE_IN Sense Input 30 Kohm On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 6 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling Impedance TD_OC Over Current Detection and Control Delay CL=1nf at GATE, 120 nSec VTH_OC_0 Current Limiting Threshold at No Compensation I(VIN) = 0uA 0.85 0.90 0.95 V VTH_OC_1 Current Limiting Threshold at Compensation I(VIN) = 150uA 0.81 V Oscillator FOSC Normal Oscillation Frequency 60 65 70 KHZ ∆f_Temp Frequency Temperature Stability -20oC to 100oC 2 % ∆f_VDD Frequency Voltage Stability VDD = 12-25V 2 % RI_range Operating RI Range 12 24 60 Kohm V_RI_open RI open voltage 2.0 V F_BM Burst Mode Base Frequency 22 KHZ DC_max Maxmum Duty Cycle 75 80 85 % DC_min Minimum Duty Cycle - - 0 % Gate Drive Output VOL Output Low Level Io = -20 mA 0.3 V VOH Output High Level Io = +20 mA 11 V VG_Clamp Output Clamp Voltage Level VDD=20V 18 V T_r Output Rising Time CL = 1nf 120 nSec T_f Output Falling Time CL = 1nf 50 nSec Over Temperature Protection I_RT Output Current of RT pin 70 uA VTH_OTP OTP Threshold Voltage 1.015 1.065 1.115 V VTH_OTP_off OTP Recovery Threshold Voltage 1.165 V TD_OTP OTP De-bounce Time 100 uSec V_RT_Open RT Pin Open Voltage 3.5 V Frequency Shuffling ∆f_OSC Frequency Modulation range /Base frequency -3 3 % Freq_Shuffling Shuffling Frequency RI = 24Kohm 32 HZ On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 7 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling CHARACTERIZATION PLOTS VDD Start-up Current vs. Voltage 0 1 2 3 4 5 6 7 8 9 10 11 0 2 4 6 8 10 12 14 16 VDD VOLTAGE (V) S ta rt- up C ur re nt (u A ) VDD Startup Current vs Temperature 0 2 4 6 8 -25 5 35 65 95 125 Temperature(C) Is ta rtu p( uA ) VDD UVLO and Operation Current 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 14 16 18 20 22 24 VDD Voltage (V) VD D Cu rr en t (m A) VDD Operation Current vs. Load 1 2 3 4 5 6 0 500 1000 1500 2000 Gatedrive Loading (pf) I( VD D) ( mA ) Fosc 50Khz Fosc 65Khz Fosc 100Khz VDD UVLO(enter) vs. Temperature 10.3 10.35 10.4 10.45 10.5 10.55 10.6 -10 10 30 50 70 90 110 Temperature(C) U V LO (e nt er ) ( V ) VDD UVLO(exit) vs. Temperature 16.4 16.5 16.6 16.7 16.8 16.9 -10 10 30 50 70 90 110 Temperature(C) U V LO (e xi t) (V ) On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 8 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling Fosc(KHz) vs RI(Kohm) 20 50 80 110 140 12 24 36 48 60 RI(Kohm) Fo sc (K H z) Fosc(KHz) vs. Temperature 63.5 64.0 64.5 65.0 65.5 66.0 -20 5 30 55 80 105 130 Temp(C) Fo sc (K H z) Vth_OC vs. I(vin) 0.6 0.7 0.8 0.9 1.0 0 50 100 150 200 250 300 I(vin) (uA) V th _O C (V ) Vth_OC(50KHz) Vth_OC(65KHz) I_RT vs. Temperature 70.6 70.8 71 71.2 71.4 -20 0 20 40 60 80 100 120 Temperature(C) I_ R T( uA ) On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 9 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling OPERATION DESCRIPTION The OB2269C is a highly integrated PWM controller IC optimized for offline flyback converter applications. The extended burst mode control greatly reduces the standby power consumption and helps the design easily meet the international power conservation requirements. • Startup Current and Start up Control Startup current of OB2269C is designed to be very low so that VDD could be charged up above UVLO(exit) threshold level and device starts up quickly. A large value startup resistor can therefore be used to minimize the power loss yet reliable startup in application. For a typical AC/DC adaptor with universal input range design, a 2 MΩ, 1/8 W startup resistor could be used together with a VDD capacitor to provide a fast startup and yet low power dissipation design solution. z Operating Current The Operating current of OB2269C is low at 2.3mA. Good efficiency is achieved with OB2269C low operating current together with extended burst mode control schemes. z Frequency shuffling for EMI improvement The frequency Shuffling/jittering (switching frequency modulation) is implemented in OB2269C. The oscillation frequency is modulated with a internally generated random source so that the tone energy is evenly spread out. The spread spectrum minimizes the conduction band EMI and therefore eases the system design in meeting stringent EMI requirement. z Burst Mode Operation At zero load or light load condition, most of the power dissipation in a switching mode power supply is from switching loss on the MOSFET transistor, the core loss of the transformer and the loss on the snubber circuit. The magnitude of power loss is in proportion to the number of switching events within a fixed period of time. Reducing switching events leads to the reduction on the power loss and thus conserves the energy. OB2269C self adjusts the switching mode according to the loading condition. At from no load to light/medium load condition, the FB input drops below burst mode threshold level (1.8V). Device enters Burst Mode control. The Gate drive output switches only when VDD voltage drops below a preset level and FB input is active to output an on state. Otherwise the gate drive remains at off state to minimize the switching loss thus reduce the standby power consumption to the greatest extend. The nature of high frequency switching also reduces the audio noise at any loading conditions. z Oscillator Operation A resistor connected between RI and GND sets the constant current source to charge/discharge the internal cap and thus the PWM oscillator frequency is determined. The relationship between RI and switching frequency follows the below equation within the specified RI in Kohm range at nominal loading operational condition. )( )( 1560 Khz KohmRI FOSC = z Current Sensing and Leading Edge Blanking Cycle-by-Cycle current limiting is offered in OB2269C current mode PWM control. The switch current is detected by a sense resistor into the sense pin. An internal leading edge blanking circuit chops off the sense voltage spike at initial MOSFET on state due to snubber diode reverse recovery so that the external RC filtering on sense input is no longer required. The current limit comparator is disabled and thus cannot turn off the external MOSFET during the blanking period. PWM duty cycle is determined by the current sense input voltage and the FB input voltage. z Internal Synchronized Slope Compensation Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation. This greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus reduces the output ripple voltage. z Over Temperature Protection A NTC resistor in series with a regular resistor should connect between RT and GND for temperature sensing and protection. NTC resistor value becomes lower when the ambient temperature rises. With the fixed internal current IRT flowing through the resistors, the voltage at RT pin becomes lower at high temperature. The internal OTP circuit is triggered and shutdown the MOSFET when the sensed input voltage is lower than VTH_OTP. z Gate Drive On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 ) ©On-Bright Electronics Confidential - 10 - OB_DOC_DS_69CC1 OB2269C Current Mode PWM ControllerFrequency Shuffling OB2269C Gate is connected to the Gate of an external MOSFET for power switch control. Too weak the gate drive strength results in higher conduction and switch loss of MOSFET while too strong gate drive output compromises the EMI. Good tradeoff is achieved through the built-in totem pole gate drive design with right output strength and dead time control. The low idle loss and good EMI system design is easier to achieve with this dedicated control scheme. An internal 18V clamp is added for MOSFET gate protection at higher than expected VDD input. z Protection Controls Good system reliability is achieved with OB2269C’s rich protection features including Cycle-by-Cycle current limiting (OCP), Over Load Protection (OLP), over temperature protection (OTP), on-chip VDD over voltage protection (OVP, optional) and under voltage lockout (UVLO). The OCP threshold value is self adjusted lower at higher current into VIN pin. This OCP threshold slope adjustment helps to compensate the increased output power limit at higher AC voltage caused by inherent Over-Current sensing and control delay. A constant output power limit is achieved with recommended OCP compensation scheme on OB2269C. At output overload condition, FB voltage is biased higher. When FB input exceeds power limit threshold value for more than 80mS, control circuit reacts to turnoff the power MOSFET. Similarly, control circuit shutdowns the power MOSFET when an Over Temperature condition is detected. OB2269C resumes the operation when temperature drops below the hysteresis value. VDD is supplied with transformer auxiliary winding output. It is clamped when VDD is higher than 35V. MOSFET is shut down when VDD drops below UVLO(enter) limit and device enters power on startup sequence thereafter. On -B ri gh t Co nf id en ti al t o Ly co n (志 恒 通 电 子 )