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1 ® ISL6520 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. FN9009.4 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller The ISL6520 makes simple work out of implementing a complete control and protection scheme for a DC/DC stepdown converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, the ISL6520 integrates the control, output adjustment, monitoring and protection functions into a single 8-pin package. The ISL6520 provides simple, single feedback loop, voltage- mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of ±1.5% over temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 15MHz gain-bandwidth product and 8V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Protection from over-current conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. Features • Operates from +5V Input • 0.8V to VIN Output Range - 0.8V Internal Reference - ±1.5% Over Line Voltage and Temperature • Drives N-Channel MOSFETs • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle • Lossless, Programmable Over-Current Protection - Uses Upper MOSFET’s rDS(on) • Small Converter Size - 300kHz Fixed Frequency Oscillator - Internal Soft Start - 8 Ld SOIC or 16Ld 4x4mm QFN • QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Power Supplies for Microprocessors - PCs - Embedded Controllers • Subsystem Power Supplies - PCI/AGP/GTL+ Buses - ACPI Power Control • Cable Modems, Set Top Boxes, and DSL Modems • DSP and Core Communications Processor Supplies • Memory Supplies • Personal Computer Peripherals • Industrial Power Supplies • 5V-Input DC/DC Regulators • Low-Voltage Distributed Power Supplies Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6520CB 6520CB 0 to 70 8 Ld SOIC M8.15 ISL6520CBZ (Note) 6520CBZ 0 to 70 8 Ld SOIC (Pb-free) M8.15 ISL6520IB 6520IB -40 to 85 8 Ld SOIC M8.15 ISL6520IBZ (Note) 6520IBZ -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL6520CR ISL6520CR 0 to 70 16 Ld 4x4mm QFN L16.4x4 ISL6520IR ISL6520IR -40 to 85 16 Ld 4x4mm QFN L16.4x4 ISL6520EVAL1 Evaluation Board * Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet October 4, 2005 ISL6520 Block Diagram Typical Application Pinouts SOIC TOP VIEW QFN TOP VIEW 5 6 8 7 4 3 2 1 UGATE GND PHASE FB VCC COMP/SD BOOT LGATE 12 11 10 9 1 2 3 4 16 15 14 13 5 6 7 8 NC COMP/OCSET NC FB GND BOOT UGATE GND NC N C N C PH A SE N C LG AT E N C VC C N C + - +- + - OSCILLATOR IN H IB IT PWM COMPARATOR ERROR AMP VCC PWM GND FB COMP/OCSET 0.8V OC COMPARATOR GATE CONTROL LOGIC BOOT UGATE PHASE 20µA FIXED 300kHz + - LGATE VCC SOFTSTART POR AND SAMPLE AND HOLD VCC +VO FB COMP/OCSET UGATE PHASE BOOT VCC GND LGATE 5 7 6 3 2 1 8 4 ISL6520 RS ROFFSET CI CF RF ROCSET LOUT DBOOT CBOOT CBULKCDCPL CHF COUT 2 FN9009.4 October 4, 2005 ISL6520 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Recommended Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10% Ambient Temperature Range - ISL6520C . . . . . . . . . . . 0oC to 70oC Ambient Temperature Range - ISL6520I . . . . . . . . . . -40oC to 85oC Junction Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 125oC Thermal Resistance θJA (oC/W) θJC (oC/W) SOIC Package (Note 1) . . . . . . . . . . . . . . 95 . . N/A QFN Package (Note 2, 3). . . . . . . . . . . . . . 45 . . 7 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal Supply IVCC UGATE and LGATE Open 2.6 3.2 3.8 mA POWER-ON RESET Rising VCC POR Threshold POR 4.19 4.30 4.5 V VCC POR Threshold Hysteresis - 0.25 - V OSCILLATOR Frequency fOSC ISL6520C, VCC = 5V 250 300 340 kHz ISL6520I, VCC = 5V 230 300 340 kHz Ramp Amplitude ∆VOSC - 1.5 - VP-P REFERENCE Reference Voltage Tolerance ISL6520C -1.5 - +1.5 % ISL6520I -2.5 +2.5 % Nominal Reference Voltage VREF - 0.800 - V ERROR AMPLIFIER DC Gain Guaranteed By Design - 88 - dB Gain-Bandwidth Product GBWP - 15 - MHz Slew Rate SR - 8 - V/µs GATE DRIVERS Upper Gate Source Current IUGATE-SRC - -1 - A Upper Gate Sink Current IUGATE-SNK - 1 - A Lower Gate Source Current ILGATE-SRC - -1 - A Lower Gate Sink Current ILGATE-SNK - 2 - A PROTECTION / DISABLE OCSET Current Source IOCSET ISL6520C 17 20 22 µA ISL6520I 14 20 24 µA Disable Threshold VDISABLE - 0.8 - V 3 FN9009.4 October 4, 2005 ISL6520 Functional Pin Description VCC This is the main bias supply for the ISL6520, as well as the lower MOSFET’s gate. Connect a well-decoupled 5V supply to this pin. FB This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP/OCSET pin, to compensate the voltage-control feedback loop of the converter. GND This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. PHASE Connect this pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the upper MOSFET for over-current protection. This pin is also monitored by the continuously adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. UGATE Connect this pin to the upper MOSFET’s gate. This pin provides the PWM-controlled gate drive for the upper MOSFET. This pin is also monitored by the adaptive shoot- through protection circuitry to determine when the upper MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the upper MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. BOOT This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-channel MOSFET. COMP/OCSET This is a multiplexed pin. During a short period of time following power-on reset (POR), this pin is used to determine the over- current threshold of the converter. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET (VCC). ROCSET, an internal 20µA current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter over- current (OC) trip point according to the following equation: Internal circuitry of the ISL6520 will not recognize a voltage drop across ROCSET larger than 0.5V. Any voltage drop across ROCSET that is greater than 0.5V will set the overcurrent trip point to: An over-current trip cycles the soft-start function. During soft-start, and all the time during normal converter operation, this pin represents the output of the error amplifier. Use this pin, in combination with the FB pin, to compensate the voltage-control feedback loop of the converter. Pulling OCSET to a level below 0.8V will disable the controller. Disabling the ISL6520 causes the oscillator to stop, the LGATE and UGATE outputs to be held low, and the softstart circuitry to re-arm. LGATE Connect this pin to the lower MOSFET’s gate. This pin provides the PWM-controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the lower MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. Functional Description Initialization The ISL6520 automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin. The POR function initiates the Over-Current Protection (OCP) sampling and hold operation after the supply voltage exceeds its POR threshold. Upon completion of the OCP sampling and hold operation, the POR function initiates the Soft Start operation. Over Current Protection The over-current function protects the converter from a shorted output by using the upper MOSFET’s on-resistance, rDS(ON), to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level (see Typical Application diagram). Immediately following POR, the ISL6520 initiates the Over- Current Protection sampling and hold operation. First, the internal error amplifier is disabled. This allows an internal 20µA current sink to develop a voltage across ROCSET. The ISL6520 then samples this voltage at the COMP pin. This sampled voltage, which is referenced to the VCC pin, is held internally as the Over-Current Set Point. When the voltage across the upper MOSFET, which is also referenced to the VCC pin, exceeds the Over-Current Set Point, the over-current function initiates a soft-start sequence. Figure 1 shows the inductor current after a fault is introduced while running at 15A. The continuous fault causes the ISL6520 to go into a hiccup mode with a typical period of 25ms. The inductor current increases to 18A during the Soft IPEAK IOCSETxROCSET rDS ON( ) -------------------------------------------------= IPEAK 0.5V rDS ON( ) ----------------------= 4 FN9009.4 October 4, 2005 ISL6520 Start interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 1 is only 1.5W. The over-current function will trip at a peak inductor current (IPEAK) determined by: where IOCSET is the internal OCSET current source (20µA typical). The OC trip point varies mainly due to the MOSFET’s rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for , where ∆I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. Soft Start The POR function initiates the soft start sequence after the overcurrent set point has been sampled. Soft start clamps the error amplifier output (COMP pin) and reference input (non- inverting terminal of the error amp) to the internally generated Soft Start voltage. Figure 2 shows a typical start up interval where the COMP/OCSET pin has been released from a grounded (system shutdown) state. Initially, the COMP/OCSET is used to sample the oversurrent setpoint by disabling the error amplifier and drawing 20µA through ROCSET. Once the over- current level has been sampled, the soft start function is initiated. The clamp on the error amplifier (COMP/OCSET pin) initially controls the converter’s output voltage during soft start. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). When the internally generated Soft Start voltage exceeds the feedback (FB pin) voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically take about 11ms. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 3 should be located as close together as possible. FIGURE 1. OVERCURRENT OPERATION TIME (5ms/DIV.) OUTPUT INDUCTOR 5A/DIV. CURRENT IPEAK IOCSET x ROCSET rDS ON( ) -----------------------------------------------------= IPEAK IOUT MAX( ) ∆I( ) 2 ----------+> FIGURE 2. START UP SEQUENCE VOUT 500mV/DIV. COMP/OCSET 1V/DIV. TIME (2ms/DIV.) LO COLGATE UGATE PHASE Q1 Q2 VIN VOUT RETURN ISL6520 CIN LO A D FIGURE 3. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS 5 FN9009.4 October 4, 2005 ISL6520 Please note that the capacitors CIN and CO may each represent numerous physical capacitors. Locate the ISL6520 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6520 must be sized to handle up to 1A peak current. Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/OCSET pin and locate the resistor, ROSCET close to the COMP/OCSET pin because the internal current source is only 20µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC a practical. Feedback Compensation Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse- width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL6520) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC). 3. Place 2ND Zero at Filter’s Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier’s Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary. The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. Compensation Break Frequency Equations Figure 6 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +5V ISL6520 COMP/OCSET GND VCC BOOT D1 LO CO VOUT LO A D Q1 Q2 PHASE +VIN CBOOT CVCC R O C SE T +5V FLC 1 2π x LO x CO -------------------------------------------= FESR 1 2π x ESR x CO --------------------------------------------= FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT REFERENCE LO CO ESR VIN ∆VOSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - REFERENCE R1 R3R2 C3 C2 C1 COMP VOUT FB ZFB ISL6520 ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN OSC FZ1 1 2π x R2 x C1 ------------------------------------= FZ2 1 2π x R1 R3+( ) x C3 -------------------------------------------------------= FP1 1 2π x R2 x C1 x C2 C1 C2+ ----------------------     ---------------------------------------------------------= FP2 1 2π x R3 x C3 ------------------------------------= 6 FN9009.4 October 4, 2005 ISL6520 Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying th