cs4335

Preliminary Product Information This document conCirrus Logic reserv Copyrig (P.O. Box 17847, Austin, Texas 78760(512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CS4334/5/6/7/8/9 tains information for a new product. es the right to modify this product without notice. ht ª Cirrus Logic, Inc. 1999 All Rights Reserved) SEP ‘99 DS248PP3 8-Pin, 24-Bit, 96 kHz Stereo D/A Converter Features lComplete Stereo DAC System: Interpolation, D/A, Output Analog Filtering l24-Bit Conversion l96 dB Dynamic Range l -88 dB THD+N lLow Clock Jitter Sensitivity lSingle +5 V Power Supply lFiltered Line Level Outputs lOn-Chip Digital De-emphasis lPopgaurd® Technology lFunctionally Compatible with CS4330/31/33 Description The CS4334 family members are complete, stereo digi- tal-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8-pin package. The CS4334/5/6/7/8/9 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference volt- age input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital de-empha- sis, operates from a single +5V power supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers. ORDERING INFORMATION See page 23 I LRCK 3 SDATA 1 DEM/SCLK 2 MCLK 4 VA AOUTL 8 AOUTR 5 Serial Input Interface Interpolator Interpolator De-emphasis Modulator D S Modulator DAC DAC Voltage Reference Analog Low-Pass Filter Analog Low-Pass Filter 7 AGND 6 D S 1 CS4334/5/6/7/8/9 TABLE OF CONTENTS 1. CHARACTERISTICS/SPECIFICATIONS ...................................................... 4 ANALOG CHARACTERISTICS................................................................... 4 POWER AND THERMAL CHARACTERISTICS ......................................... 6 DIGITAL CHARACTERISTICS.................................................................... 7 ABSOLUTE MAXIMUM RATINGS .............................................................. 7 RECOMMENDED OPERATING CONDITIONS.......................................... 7 SWITCHING CHARACTERISTICS ............................................................. 8 2. TYPICAL CONNECTION DIAGRAM ........................................................... 10 3. GENERAL DESCRIPTION .......................................................................... 11 3.1 Digital Interpolation Filter ................................................................... 11 3.2 Delta-Sigma Modulator ...................................................................... 11 3.3 Switched-Capacitor DAC ................................................................... 11 3.4 Analog Low-Pass Filter ...................................................................... 11 4. SYSTEM DESIGN ........................................................................................ 12 4.1 Master Clock ...................................................................................... 12 4.2 Serial Clock ........................................................................................ 12 4.2.1 External Serial Clock Mode ...................................................... 12 4.2.2 Internal Serial Clock Mode ....................................................... 12 4.3 De-Emphasis ..................................................................................... 12 4.4 Initialization and Power-Down ........................................................... 12 4.5 Output Transient Control ................................................................... 13 4.6 Grounding and Power Supply Decoupling ......................................... 13 4.7 Analog Output and Filtering ............................................................... 13 4.8 Overall Base-Rate Frequency Response .......................................... 17 4.9 Overall High-Rate Frequency Response ........................................... 18 4.10 Base Rate Mode Performance Plots ............................................... 19 4.11 High Rate Mode Performance Plots ................................................ 20 5. PIN DESCRIPTIONS ................................................................................... 21 6. PARAMETER DEFINITIONS ....................................................................... 22 7. REFERENCES ............................................................................................. 22 8. ORDERING INFORMATION: ...................................................................... 23 9. FUNCTIONAL COMPATIBILITY ................................................................. 23 10. PACKAGE DIMENSIONS .......................................................................... 24 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 DS248PP3 CS4334/5/6/7/8/9 LIST OF FIGURES Figure 1.Output Test Load .................................................................................... 6 Figure 2.Maximum Loading................................................................................... 6 Figure 3.Power vs. Sample Rate .......................................................................... 6 Figure 4.External Serial Mode Input Timing.......................................................... 9 Figure 5.Internal Serial Mode Input Timing........................................................... 9 Figure 6. Internal Serial Clock Generation ............................................................ 9 Figure 7.Recommended Connection Diagram.................................................... 10 Figure 8.System Block Diagram.......................................................................... 11 Figure 9.De-Emphasis Curve (Fs = 44.1kHz) ..................................................... 13 Figure 10.CS4334 Data Format (I2S).................................................................. 14 Figure 11.CS4335 Data Format .......................................................................... 14 Figure 12.CS4336 Data Format .......................................................................... 14 Figure 13.CS4337 Data Format .......................................................................... 15 Figure 14.CS4338 Data Format .......................................................................... 15 Figure 15.CS4339 Data Format .......................................................................... 15 Figure 16.CS4334/5/6/7/8/9 Initialization and Power-Down Sequence .............. 16 Figure 17.Stopband Rejection............................................................................. 17 Figure 18.Transition Band................................................................................... 17 Figure 19.Transition Band................................................................................... 17 Figure 20.Passband Ripple................................................................................. 17 Figure 21.Stopband Rejection............................................................................. 18 Figure 22.Transition Band................................................................................... 18 Figure 23.Transition Band................................................................................... 18 Figure 24.Passband Ripple................................................................................. 18 Figure 25.0 dBFS FFT (BRM) ............................................................................. 19 Figure 26. -60 dBFS FFT (BRM)......................................................................... 19 Figure 27.Idle Channel Noise FFT (BRM)........................................................... 19 Figure 28.Twin Tone IMD FFT (BRM)................................................................. 19 Figure 29.THD+N vs. Amplitude (BRM).............................................................. 19 Figure 30.THD+N vs. Frequency (BRM)............................................................. 19 Figure 31.0 dBFS FFT (HRM)............................................................................. 20 Figure 32. -60 dBFS FFT (HRM)......................................................................... 20 Figure 33.Idle Channel Noise FFT (HRM) .......................................................... 20 Figure 34.Twin Tone IMD FFT (HRM) ................................................................ 20 Figure 35.THD+N vs. Amplitude (HRM).............................................................. 20 Figure 36. THD+N vs. Frequency (HRM)............................................................ 20 DS248PP3 3 CS4334/5/6/7/8/9 1. CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25 °C; Logic "1" = VA = 5 V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load RL = 10 kW , CL = 10 pF (see Figure 1)) Notes: 1. One-half LSB of triangular PDF dither added to data. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Dynamic Performance for CS4334/5/6/7/8/9-KS Specified Temperature Range TA -10 - 70 -10 - 70 °C Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 88 91 86 89 93 96 91 94 - - - - - 91 - 89 90 96 88 94 - - - - dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N - - - - - - -88 -73 -33 -86 -71 -31 -83 -68 -28 -81 -66 -26 - - - - - - -88 -70 -30 -86 -68 -28 -83 -65 -25 -81 -63 -23 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 94 - - 95 - dB Dynamic Performance for CS4334/5/6/7/8/9-BS Specified Temperature Range TA -40 - 85 -40 - 85 °C Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 85 88 83 86 93 96 91 94 - - - - - 88 - 86 90 96 88 94 - - - - dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N - - - - - - -88 -73 -33 -86 -71 -31 -82 -65 -25 -70 -63 -23 - - - - - - -88 -70 -30 -86 -68 -28 -82 -62 -22 -80 -60 -20 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 94 - - 95 - dB 4 DS248PP3 CS4334/5/6/7/8/9 ANALOG CHARACTERISTICS (Continued) Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 17-24) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is not available in High-Rate Mode. 6. Refer to Figure 2. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 2) Passband (Note 3) to -0.05 dB corner to -0.1 dB corner to -3 dB corner 0 - 0 - - - .4780 - .4996 - 0 0 - - - - .4650 .4982 Fs Fs Fs Frequency Response 10 Hz to 20 kHz -.01 - +.08 -.05 - +.2 dB Passband Ripple - - ±.08 - - ±.2 dB StopBand .5465 - - .5770 - - Fs StopBand Attenuation (Note 4) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz - ±0.36/Fs - - - ±1.39/Fs ±0.23/Fs - - s s De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz - - - - - - +1.5/+0 +.05/-.25 -.2/-.4 (Note 5) dB dB dB Parameters Symbol Min Typ Max Units dc Accuracy Interchannel Gain Mismatch - 0.1 0.4 dB Gain Error - ±5 - % Gain Drift - 100 - ppm/°C Analog Output Full Scale Output Voltage 3.25 3.5 3.75 Vpp Quiescent Voltage VQ - 2.2 - VDC Max AC-Load Resistance (Note 6) RL - 3 - k W Max Load Capacitance (Note 6) CL - 100 - pF DS248PP3 5 CS4334/5/6/7/8/9 POWER AND THERMAL CHARACTERISTICS Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V. Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current normal operation power-down state IA IA - - 15 40 19 - mA m A Power Dissipation (Note 7) normal operation power-down - - 75 0.2 104 - mW mW Package Thermal Resistance q JA - 110 - °C/Watt Power Supply Rejection Ratio (1 kHz) PSRR - 79 - dB AOUTx AGND 10 µF V out R L C L Figure 1. Output Test Load 100 50 75 25 2.5 5 10 15 Safe Operating Region Ca pa ci tiv e Lo a d - - C (pF ) L Resistive Load -- R (k W )L 125 3 20 Figure 2. Maximum Loading 75 50 30 Po w er (m W ) Sample Rate (kHz) BR M HR M 70 65 60 55 40 50 60 70 80 90 100 Figure 3. Power vs. Sample Rate 6 DS248PP3 CS4334/5/6/7/8/9 DIGITAL CHARACTERISTICS (TA = 25°C; VA = 4.75V - 5.5V) Notes: 8. Iin for CS433X LRCK is ±20 m A max. ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) Parameters Symbol Min Typ Max Units High-Level Input Voltage VIH 2.0 - - V Low-Level Input Voltage VIL - - 0.8 V Input Leakage Current (Note 8) Iin - - ±10 m A Input Capacitance - 8 - pF Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current, Any Pin Except Supplies Iin - ±10 mA Digital Input Voltage VIND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) TA -55 125 °C Storage Temperature Tstg -65 150 °C Parameters Symbol Min Typ Max Units DC Power Supply VA 4.75 5.0 5.5 V DS248PP3 7 CS4334/5/6/7/8/9 SWITCHING CHARACTERISTICS (TA = -40 to 85°C; VA = 4.75V - 5.5V; Inputs: Logic 0 = 0V, Logic 1 = VA, CL = 20pF) Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/- 1/2 MCLK Period. 10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures 10-15) Parameters Symbol Min Typ Max Units Input Sample Rate Fs 2 - 100 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns SCLK Period MCLK / LRCK = 512, 256 or 384 tsclkw - - ns SCLK Period MCLK / LRCK = 128 or 192 tsclkw - - ns SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 9) - 50 - % SCLK Period (Note 10) tsclkw - - ns SCLK rising to LRCK edge tsclkr - - m s SDATA valid to SCLK rising setup time tsdlrs - - ns SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 tsdh - - ns SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 tsdh - - ns 1 128( )Fs---------------------- 1 64( )Fs------------------- 1 SCLK----------------- tsclkw 2------------------ 1 512( )Fs---------------------- 10+ 1 512( )Fs---------------------- 15+ 1 384( )Fs---------------------- 15+ 8 DS248PP3 CS4334/5/6/7/8/9 sclkhtslrst slrdt sdlrst sdh t sclklt SDATA SCLK LRCK Figure 4. External Serial Mode Input Timing SDATA *INTERNAL SCLK LRCK sclkwt sdlrst sdht sclkrt Figure 5. Internal Serial Mode Input Timing * The SCLK pulses shown are internal to the CS4334/5/6/7/8/9. SDATA LRCK MCLK *INTERNAL SCLK 1 N 2 N Figure 6. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4334/5/6/7/8/9. N equals MCLK divided by SCLK DS248PP3 9 CS4334/5/6/7/8/9 2. TYPICAL CONNECTION DIAGRAM DEM/SCLK 6 Audio Data Processor External Clock MCLK AGND AOUTR CS4334 CS4335 CS4336 CS4337 CS4338 CS4339 SDATA LRCK VA AOUTL 3 1 2 4 7 0.1 µF + 1 µF 8 Left Audio Output 5 Right Audio Output +5V 3.3 µF 10 k W C 560 W + R + 560 C = 4 p Fs(R 560) 267 k R L 3.3 µF 10 k W C 560 W + 267 k R L L L Figure 7. Recommended Connection Diagram 10 DS248PP3 CS4334/5/6/7/8/9 3. GENERAL DESCRIPTION The CS4334 family of devices offers a complete stereo digital-to-analog system including digital in- terpolation, fourth-order delta-sigma digital-to-an- alog conversion, digital de-emphasis and analog filtering, as shown in Figure 8. This architecture provides a high tolerance to clock jitter. The primary purpose of using delta-sigma modula- tion techniques is to avoid the limitations of resis- tive laser trimmed digital-to-analog converter architectures by using an inherently linear 1-bit digital-to-analog converter. The advantages of a 1- bit digital-to-analog converter include: ideal differ- ential linearity, no distortion mechanisms due to re- sistor matching errors and no linearity drift over time and temperature due to variations in resistor values. The CS4334 family of devices supports two modes of operation. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. High Rate Mode al- lows input sample rates up to 100 k