Virtex-5器件一览

DS100 (v5.0) February 6, 2009 www.xilinx.com Product Specification 1 © 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. General Description The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally- controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability. Summary of Virtex-5 FPGA Features • Five platforms LX, LXT, SXT, TXT, and FXT − Virtex-5 LX: High-performance general logic applications − Virtex-5 LXT: High-performance logic with advanced serial connectivity − Virtex-5 SXT: High-performance signal processing applications with advanced serial connectivity − Virtex-5 TXT: High-performance systems with double density advanced serial connectivity − Virtex-5 FXT: High-performance embedded systems with advanced serial connectivity • Cross-platform compatibility − LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators • Most advanced, high-performance, optimal-utilization, FPGA fabric − Real 6-input look-up table (LUT) technology − Dual 5-LUT option − Improved reduced-hop routing − 64-bit distributed RAM option − SRL32/Dual SRL16 option • Powerful clock management tile (CMT) clocking − Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting − PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division • 36-Kbit block RAM/FIFOs − True dual-port RAM blocks − Enhanced optional programmable FIFO logic − Programmable - True dual-port widths up to x36 - Simple dual-port widths up to x72 − Built-in optional error-correction circuitry − Optionally program each block as two independent 18-Kbit blocks • High-performance parallel SelectIO technology − 1.2 to 3.3V I/O Operation − Source-synchronous interfacing using ChipSync™ technology − Digitally-controlled impedance (DCI) active termination − Flexible fine-grained I/O banking − High-speed memory interface support • Advanced DSP48E slices − 25 x 18, two’s complement, multiplication− Optional adder, subtracter, and accumulator − Optional pipelining − Optional bitwise logical functionality − Dedicated cascade connections • Flexible configuration options − SPI and Parallel FLASH interface − Multi-bitstream support with dedicated fallback reconfiguration logic − Auto bus width detection capability • System Monitoring capability on all devices − On-chip/Off-chip thermal monitoring − On-chip/Off-chip power supply monitoring − JTAG access to all monitored quantities • Integrated Endpoint blocks for PCI Express Designs − LXT, SXT, TXT, and FXT Platforms− Compliant with the PCI Express Base Specification 1.1− x1, x4, or x8 lane support per block− Works in conjunction with RocketIO™ transceivers • Tri-mode 10/100/1000 Mb/s Ethernet MACs − LXT, SXT, TXT, and FXT Platforms− RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) options • RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s − LXT and SXT Platforms • RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s − TXT and FXT Platforms • PowerPC 440 Microprocessors − FXT Platform only− RISC architecture− 7-stage pipeline− 32-Kbyte instruction and data caches included− Optimized processor interface structure (crossbar) • 65-nm copper CMOS process technology • 1.0V core voltage • High signal-integrity flip-chip packaging available in standard or Pb-free package options 0 Virtex-5 Family Overview DS100 (v5.0) February 6, 2009 0 0 Product Specification R Virtex-5 Family Overview 2 www.xilinx.com DS100 (v5.0) February 6, 2009 Product Specification R Table 1: Virtex-5 FPGA Family Members Device Configurable Logic Blocks (CLBs) DSP48E Slices(2) Block RAM Blocks CMTs(4) PowerPC Processor Blocks Endpoint Blocks for PCI Express Ethernet MACs(5) Max RocketIO Transceivers(6) Total I/O Banks(8) Max User I/O(7)Array(Row x Col) Virtex-5 Slices(1) Max Distributed RAM (Kb) 18 Kb(3) 36 Kb Max(Kb) GTP GTX XC5VLX30 80 x 30 4,800 320 32 64 32 1,152 2 N/A N/A N/A N/A N/A 13 400 XC5VLX50 120 x 30 7,200 480 48 96 48 1,728 6 N/A N/A N/A N/A N/A 17 560 XC5VLX85 120 x 54 12,960 840 48 192 96 3,456 6 N/A N/A N/A N/A N/A 17 560 XC5VLX110 160 x 54 17,280 1,120 64 256 128 4,608 6 N/A N/A N/A N/A N/A 23 800 XC5VLX155 160 x 76 24,320 1,640 128 384 192 6,912 6 N/A N/A N/A N/A N/A 23 800 XC5VLX220 160 x 108 34,560 2,280 128 384 192 6,912 6 N/A N/A N/A N/A N/A 23 800 XC5VLX330 240 x 108 51,840 3,420 192 576 288 10,368 6 N/A N/A N/A N/A N/A 33 1,200 XC5VLX20T 60 x 26 3,120 210 24 52 26 936 1 N/A 1 2 4 N/A 7 172 XC5VLX30T 80 x 30 4,800 320 32 72 36 1,296 2 N/A 1 4 8 N/A 12 360 XC5VLX50T 120 x 30 7,200 480 48 120 60 2,160 6 N/A 1 4 12 N/A 15 480 XC5VLX85T 120 x 54 12,960 840 48 216 108 3,888 6 N/A 1 4 12 N/A 15 480 XC5VLX110T 160 x 54 17,280 1,120 64 296 148 5,328 6 N/A 1 4 16 N/A 20 680 XC5VLX155T 160 x 76 24,320 1,640 128 424 212 7,632 6 N/A 1 4 16 N/A 20 680 XC5VLX220T 160 x 108 34,560 2,280 128 424 212 7,632 6 N/A 1 4 16 N/A 20 680 XC5VLX330T 240 x 108 51,840 3,420 192 648 324 11,664 6 N/A 1 4 24 N/A 27 960 XC5VSX35T 80 x 34 5,440 520 192 168 84 3,024 2 N/A 1 4 8 N/A 12 360 XC5VSX50T 120 x 34 8,160 780 288 264 132 4,752 6 N/A 1 4 12 N/A 15 480 XC5VSX95T 160 x 46 14,720 1,520 640 488 244 8,784 6 N/A 1 4 16 N/A 19 640 XC5VSX240T 240 x 78 37,440 4,200 1,056 1,032 516 18,576 6 N/A 1 4 24 N/A 27 960 XC5VTX150T 200 x 58 23,200 1,500 80 456 228 8,208 6 N/A 1 4 N/A 40 20 680 XC5VTX240T 240 x 78 37,440 2,400 96 648 324 11,664 6 N/A 1 4 N/A 48 20 680 XC5VFX30T 80 x 38 5,120 380 64 136 68 2,448 2 1 1 4 N/A 8 12 360 XC5VFX70T 160 x 38 11,200 820 128 296 148 5,328 6 1 3 4 N/A 16 19 640 XC5VFX100T 160 x 56 16,000 1,240 256 456 228 8,208 6 2 3 4 N/A 16 20 680 XC5VFX130T 200 x 56 20,480 1,580 320 596 298 10,728 6 2 3 6 N/A 20 24 840 XC5VFX200T 240 x 68 30,720 2,280 384 912 456 16,416 6 2 4 8 N/A 24 27 960 Notes: 1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously it was two LUTs and two flip-flops.) 2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks. 4. Each Clock Management Tile (CMT) contains two DCMs and one PLL. 5. This table lists separate Ethernet MACs per device. 6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150 Mb/s to 6.5 Gb/s. 7. This number does not include RocketIO transceivers. 8. Includes configuration Bank 0. Virtex-5 Family Overview DS100 (v5.0) February 6, 2009 www.xilinx.com Product Specification 3 R Virtex-5 FPGA Logic • On average, one to two speed grade improvement over Virtex-4 devices • Cascadable 32-bit variable shift registers or 64-bit distributed memory capability • Superior routing architecture with enhanced diagonal routing supports block-to-block connectivity with minimal hops • Up to 330,000 logic cells including: − Up to 207,360 internal fabric flip-flops with clock enable (XC5VLX330) − Up to 207,360 real 6-input look-up tables (LUTs) with greater than 13 million total LUT bits − Two outputs for dual 5-LUT mode gives enhanced utilization − Logic expanding multiplexers and I/O registers 550 MHz Clock Technology • Up to six Clock Management Tiles (CMTs) − Each CMT contains two DCMs and one PLL—up to eighteen total clock generators − Flexible DCM-to-PLL or PLL-to-DCM cascade − Precision clock deskew and phase shift − Flexible frequency synthesis − Multiple operating modes to ease performance trade-off decisions − Improved maximum input/output frequency − Fine-grained phase shifting resolution − Input jitter filtering − Low-power operation − Wide phase shift range • Differential clock tree structure for optimized low-jitter clocking and precise duty cycle • 32 global clock networks • Regional, I/O, and local clocks in addition to global clocks SelectIO Technology • Up to 1,200 user I/Os • Wide selection of I/O standards from 1.2V to 3.3V • Extremely high-performance − Up to 800 Mb/s HSTL and SSTL (on all single-ended I/Os) − Up to 1.25 Gb/s LVDS (on all differential I/O pairs) • True differential termination on-chip • Same edge capture at input and output I/Os • Extensive memory interface support 550 MHz Integrated Block Memory • Up to 16.4 Mbits of integrated block memory • 36-Kbit blocks with optional dual 18-Kbit mode • True dual-port RAM cells • Independent port width selection (x1 to x72) − Up to x36 total per port for true dual port operation − Up to x72 total per port for simple dual port operation (one Read port and one Write port) − Memory bits plus parity/sideband memory support for x9, x18, x36, and x72 widths − Configurations from 32K x 1 to 512 x 72 (8K x 4 to 512 x 72 for FIFO operation) • Multirate FIFO support logic − Full and Empty flag with fully programmable Almost Full and Almost Empty flags • Synchronous FIFO support without Flag uncertainty • Optional pipeline stages for higher performance • Byte-write capability • Dedicated cascade routing to form 64K x 1 memory without using FPGA routing • Integrated optional ECC for high-reliability memory requirements • Special reduced-power design for 18 Kbit (and below) operation 550 MHz DSP48E Slices • 25 x 18 two’s complement multiplication • Optional pipeline stages for enhanced performance • Optional 48-bit accumulator for multiply accumulate (MACC) operation with optional accumulator cascade to 96-bits • Integrated adder for complex-multiply or multiply-add operation • Optional bitwise logical operation modes • Independent C registers per slice • Fully cascadable in a DSP column without external routing resources ChipSync Source-Synchronous Interfacing Logic • Works in conjunction with SelectIO technology to simplify source-synchronous interfaces • Per-bit deskew capability built into all I/O blocks (variable delay line on all inputs and outputs) • Dedicated I/O and regional clocking resources (pins and trees) • Built-in data serializer/deserializer logic with corresponding clock divider support in all I/O • Networking/telecommunication interfaces up to 1.25 Gb/s per I/O Virtex-5 Family Overview 4 www.xilinx.com DS100 (v5.0) February 6, 2009 Product Specification R Digitally Controlled Impedance (DCI) Active I/O Termination • Optional series or parallel termination • Temperature and voltage compensation • Makes board layout much easier − Reduces resistors − Places termination in the ideal location, at the signal source or destination Configuration • Support for platform Flash, standard SPI Flash, or standard parallel NOR Flash configuration • Bitstream support with dedicated fallback reconfiguration logic • 256-bit AES bitstream decryption provides intellectual property security and prevents design copying • Improved bitstream error detection/correction capability • Auto bus width detection capability • Partial Reconfiguration via ICAP port Advanced Flip-Chip Packaging • Pre-engineered packaging technology for proven superior signal integrity − Minimized inductive loops from signal to return − Optimal signal-to-PWR/GND ratios • Reduces SSO induced noise by up to 7x • Pb-Free and standard packages System Monitor • On-Chip temperature measurement (±4°C) • On-Chip power supply measurement (±1%) • Easy to use, self-contained − No design required for basic operation − Autonomous monitoring of all on-chip sensors − User programmable alarm thresholds for on-chip sensors • User accessible 10-bit 200kSPS ADC − Automatic calibration of offset and gain error − DNL = ±0.9 LSBs maximum • Up to 17 external analog input channels supported − 0V to 1V input range − Monitor external sensors e.g., voltage, temperature − General purpose analog inputs • Full access from fabric or JTAG TAP to System Monitor • Fully operational prior to FPGA configuration and during device power down (access via JTAG TAP only) 65-nm Copper CMOS Process • 1.0V Core Voltage • 12-layer metal provides maximum routing capability and accommodates hard-IP immersion • Triple-oxide technology for proven reduced static power consumption System Blocks Specific to the LXT, SXT, TXT, and FXT Devices Integrated Endpoint Block for PCI Express Compliance • Works in conjunction with RocketIO GTP transceivers (LXT and SXT) and GTX transceivers (TXT and FXT) to deliver full PCI Express Endpoint functionality with minimal FPGA logic utilization. • Compliant with the PCI Express Base Specification 1.1 • PCI Express Endpoint block or Legacy PCI Express Endpoint block • x8, x4, or x1 lane width • Power management support • Block RAMs used for buffering • Fully buffered transmit and receive • Management interface to access PCI Express configuration space and internal configuration • Supports the full range of maximum payload sizes • Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of 32 bit and 64 bit) Tri-Mode Ethernet Media Access Controller • Designed to the IEEE 802.3-2002 specification • Operates at 10, 100, and 1,000 Mb/s • Supports tri-mode auto-negotiation • Receive address filter (5 address entries) • Fully monolithic 1000Base-X solution with RocketIO GTP transceivers • Supports multiple external PHY connections (RGMII, GMII, etc.) interfaces through soft logic and SelectIO resources • Supports connection to external PHY device through SGMII using soft logic and RocketIO GTP transceivers • Receive and transmit statistics available through separate interface • Separate host and client interfaces • Support for jumbo frames • Support for VLAN • Flexible, user-configurable host interface • Supports IEEE 802.3ah-2004 unidirectional mode Virtex-5 Family Overview DS100 (v5.0) February 6, 2009 www.xilinx.com Product Specification 5 R RocketIO GTP Transceivers (LXT/SXT only) • Full-duplex serial transceiver capable of 100 Mb/s to 3.75 Gb/s baud rates • 8B/10B, user-defined FPGA logic, or no encoding options • Channel bonding support • CRC generation and checking • Programmable pre-emphasis or pre-equalization for the transmitter • Programmable termination and voltage swing • Programmable equalization for the receiver • Receiver signal detect and loss of signal indicator • User dynamic reconfiguration using secondary configuration bus • Out of Band (OOB) support for Serial ATA (SATA) • Electrical idle, beaconing, receiver detection, and PCI Express and SATA spread-spectrum clocking support • Less than 100 mW typical power consumption • Built-in PRBS Generators and Checkers RocketIO GTX Transceivers (TXT/FXT only) • Full-duplex serial transceiver capable of 150 Mb/s to 6.5 Gb/s baud rates • 8B/10B encoding and programmable gearbox to support 64B/66B and 64B/67B encoding, user-defined FPGA logic, or no encoding options • Channel bonding support • CRC generation and checking • Programmable pre-emphasis or pre-equalization for the transmitter • Programmable termination and voltage swing • Programmable continuous time equalization for the receiver • Programmable decision feedback equalization for the receiver • Receiver signal detect and loss of signal indicator • User dynamic reconfiguration using secondary configuration bus • OOB support (SATA) • Electrical idle, beaconing, receiver detection, and PCI Express spread-spectrum clocking support • Low-power operation at all line rates PowerPC 440 RISC Cores (FXT only) • Embedded PowerPC 440 (PPC440) cores − Up to 550 MHz operation − Greater than 1000 DMIPS per core − Seven-stage pipeline − Multiple instructions per cycle − Out-of-order execution − 32 Kbyte, 64-way set associative level 1 instruction cache − 32 Kbyte, 64-way set associative level 1 data cache − Book E compliant • Integrated crossbar for enhanced system performance − 128-bit Processor Local Buses (PLBs) − Integrated scatter/gather DMA controllers − Dedicated interface for connection to DDR2 memory controller − Auto-synchronization for non-integer PLB-to-CPU clock ratios • Auxiliary Processor Unit (APU) Interface and Controller − Direct connection from PPC440 embedded block to FPGA fabric-based coprocessors − 128-bit wide pipelined APU Load/Store − Support of autonomous instructions: no pipeline stalls − Programmable decode for custom instructions Virtex-5 Family Overview 6 www.xilinx.com DS100 (v5.0) February 6, 2009 Product Specification R Architectural Description Virtex-5 FPGA Array Overview Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-5 devices implement the following functionality: • I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by programmable I/O blocks (IOBs). The IOBs can be connected to very flexible ChipSync logic for enhanced source-synchronous interfacing. Source-synchronous optimizations include per-bit deskew (on both input and output signals), data serializers/deserializers, clock dividers, and dedicated I/O and local clocking resources. • Configurable Logic Blocks (CLBs), the basic logic elements for Xilinx® FPGAs, provide combinatorial and synchronous logic as well as distributed memory and SRL32 shift register capability. Virtex-5 FPGA CLBs are based on real 6-input look-up table technology and provide superior capabilities and performance compared to previous generations of programmable logic. • Block RAM modules provide flexible 36 Kbit true dual-