74HC138

TL/F/5120 M M 5 4 H C 1 3 8 / M M 7 4 H C 1 3 8 3 -to -8 L in e D e c o d e r January 1988 MM54HC138/MM74HC138 3-to-8 Line Decoder General Description This decoder utilizes advanced silicon-gate CMOS technol- ogy, and is well suited to memory address decoding or data routing applications. The circuit features high noise immuni- ty and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM54HC138/MM74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs deter- mine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 54LS138/74LS138. All inputs are protected from dam- age due to static discharge by diodes to VCC and ground. Features Y Typical propagation delay: 20 ns Y Wide power supply range: 2V–6V Y Low quiescent current: 80 mA maximum (74HC Series) Y Low input current: 1 mA maximum Y Fanout of 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package TL/F/5120–1 Order Number MM54HC138 or MM74HC138 Truth Table Inputs Outputs Enable Select G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L L H H L H H H H H H H L L H L H H L H H H H H H L L H H H H H L H H H H H L H L L H H H H L H H H H L H L H H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L *G2eG2AaG2B Hehigh level, Lelow level, Xedon’t care TL/F/5120–2 C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) b0.5 to a7.0V DC Input Voltage (VIN) b1.5 to VCCa1.5V DC Output Voltage (VOUT) b0.5 to VCCa0.5V Clamp Diode Current (IIK, IOK) g20 mA DC Output Current, per pin (IOUT) g25 mA DC VCC or GND Current, per pin (ICC) g50 mA Storage Temperature Range (TSTG) b65§C to a150§C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§C Operating Conditions Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V (VIN, VOUT) Operating Temp. Range (TA) MM74HC b40 a85 §C MM54HC b55 a125 §C Input Rise or Fall Times VCCe2.0V(tr, tf) 1000 ns VCCe4.5V 500 ns VCCe6.0V 400 ns DC Electrical Characteristics (Note 4) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits VIH Minimum High Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V Input Voltage** 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VOH Minimum High Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VINeVIH or VIL lIOUTls4.0 mA 4.5V 4.2 3.98 3.84 3.7 V lIOUTls5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum Low Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VINeVIH or VIL lIOUTls4.0 mA 4.5V 0.2 0.26 0.33 0.4 V lIOUTls5.2 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA Current ICC Maximum Quiescent VINeVCC or GND 6.0V 8.0 80 160 mA Supply Current IOUTe0 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§C to 85§C; ceramic ‘‘J’’ package: b12 mW/§C from 100§C to 125§C. Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCCe5V, TAe25§C, CLe15 pF, tretfe6 ns Symbol Parameter Conditions Typ Guaranteed Units Limit tPLH Maximum Propagation 18 25 ns Delay, Binary Select to any Output tPHL Maximum Propagation 28 35 ns Delay, Binary Select to any Output tPHL, tPLH Maximum Propagation 18 25 ns Delay, G1 to any Output tPHL Maximum Propagation 23 30 ns Delay G2A or G2B to Output tPLH Maximum Propagation 18 25 ns Delay G2A or G2B to Output AC Electrical Characteristics CLe50 pF, tretfe6 ns (unless otherwise specified) TAe25§C 74HC 54HC Symbol Parameter Conditions VCC TA eb40 to 85§C TAeb55 to 125§C Units Typ Guaranteed Limits tPLH Maximum Propagation 2.0V 75 150 189 224 ns Delay Binary Select to 4.5V 15 30 38 45 ns any Output Low to High 6.0V 13 26 32 38 ns tPHL Maximum Propagation 2.0V 100 200 252 298 ns Delay Binary Select to any 4.5V 20 40 50 60 ns Output High to Low 6.0V 17 34 43 51 ns tPHL, tPLH Maximum Propagation 2.0V 75 150 189 224 ns Delay G1 to any 4.5V 15 30 38 45 ns Output 6.0V 13 26 32 38 ns tPHL Maximum Propagation 2.0V 82 175 221 261 ns Delay G2A or G2B to 4.5V 28 35 44 52 ns Output 6.0V 22 30 37 44 ns tPLH Maximum Propagation 2.0V 75 150 189 224 ns Delay G2A or G2B to 4.5V 15 30 38 45 ns Output 6.0V 13 26 32 38 ns tTLH, tTHL Output Rise and 2.0V 30 75 95 110 ns Fall Time 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns CIN Maximum Input 3 10 10 10 pF Capacitance CPD Power Dissipation (Note 5) 75 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC. 3 M M 5 4 H C 1 3 8 / M M 7 4 H C 1 3 8 3 -t o -8 L in e D e c o d e r Physical Dimensions inches (millimeters) Order Number MM54HC138J or MM74HC138J NS Package Number J16A Order Number MM74HC138N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.