PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
Version : 1.3
TECHNICAL SPECIFICATION
MODEL NO.: PD104SL3
Customer’s Confirmation
Customer Name
Date
By
PVI’s Confirmation
Confirmed By
Prepared By
PRIME VIEW INTERNATIONAL CO.,LTD.
3,LI SHIN RD. 1,SCIENCE-BASED INDUSTRIAL
PARK,HSINCHU,TAIWAN,R.O.C.
http://www.pvi.com.tw
Date: Mar.10, 2003
This technical specification is subject to change without notice.
Please contact with PVI for more detail information about this specification sheet.
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:1
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
TECHNICAL SPECIFICATION
CONTENTS
NO. ITEM PAGE
- Cover 1
- Contents 2
1 Application 3
2 Features 3
3 Mechanical Specifications 3
4 Mechanical Drawing of TFT-LCD module 4
5 Input / Output Terminals 5
6 Absolute Maximum Ratings 7
7 Electrical Characteristics 7
8 Power On Sequence 13
9 Optical Characteristics 14
10 Handling Cautions 17
11 Reliability Test 18
12 Block Diagram 19
13 Packing 20
- Revision History 21
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:2
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
1.Application
This data sheet applies to a color TFT LCD module, PD104SL3.
PD104SL3 module applies to notebook PC, sub-note-book PC and other OA product, which
require high quality flat panel display. This module is not designed for aerospace, avionics,
medical, F/A, transportation, car or any other products, which require extreme level of
reliability.
Prime View assume no responsibility for any damage resulting from the use of the device
which dose not comply with the instructions and the precautions in these specification sheet.
2. Features
. Amorphous silicon TFT LCD panel with back-light unit
. Pixel in stripe configuration
. Slim and compact, designed for O/A application
. Display Colors:262,144 colors
. Optimum Viewing Direction:6 o’clock
. 3.3V LVDS interface standard: DS90CF364 as receiver
. +3.3V DC supply voltage for TFT LCD panel driving
. Backlight driving DC/AC inverter not included in this module
.Long Life Lamp
3.Mechanical Specifications
Parameter Specifications Unit
Screen Size 26.4(diagonal) cm
10.4 (diagonal) inch
Display Format 800×(R, G, B)×600 dot
Display Colors 262,144
Active Area 211.2(H)×158.4 (V) mm
Pixel Pitch 0.264 (H)×0.264 (V) mm
Pixel Configuration Stripe
Outline Dimension 238.6 (w)×171.0(H)×6.0(typ.) (D) mm
Weight 310(typ.),320(max.) g
Back-light Single CCFL, side-light type
Surface treatment Anti-glare and hard-coating
Display mode Normally white
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:3
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
4. Mechanical Drawing of TFT-LCD Module
Unit: mm
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:4
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
5. Input Terminals
5-1) TFT-LCD Panel Driving
Connector type: Molex 55177-1491
Pin No. Symbol Function Remark
1 VDD Power supply : +3.3V
2 VDD Power supply : +3.3V
3 GND
4 GND
5 IN0- Pixel data Transmission pair 0 (negative -)
6 IN0+ Pixel data Transmission pair 0 (positive +)
7 IN1- Pixel data Transmission pair 1 (negative -)
8 IN1+ Pixel data Transmission pair 1 (positive +)
9 IN2- Pixel data Transmission pair 2 (negative -)
10 IN2+ Pixel data Transmission pair 2 (positive +)
11 CLK- Sampling Clock (negative -)
12 CLK+ Sampling Clock (positive +)
13 GND
14 GND
Recommended Transmitter (DS90C*363 of National Semiconductor) to PD104SL3 interface
Assignment:
Input
of DS
terminal
90C*363
Graphic controller output signal Output signal
symbol
To PD104SL3
interface
terminal(Symbol)
Symbol No. Symbol Function
TIN0 44 R0 Red pixel data (LSB)
TIN1 45 R1 Red pixel data
TIN2 47 R2 Red pixel data Tout0- No.5 : IN0-
TIN3 48 R3 Red pixel data
TIN4 1 R4 Red pixel data Tout0+ No.6 : IN0+
TIN5 3 R5 Red pixel data(MSB)
TIN6 4 G0 Green pixel data (LSB)
TIN7 6 G1 Green pixel data
TIN8 7 G2 Green pixel data
TIN9 9 G3 Green pixel data Tout1- No.7 : IN1-
TIN10 10 G4 Green pixel data
TIN11 12 G5 Green pixel data(MSB) Tout1+ No.8 : IN1+
TIN12 13 B0 Blue pixel data(LSB)
TIN13 15 B1 Blue pixel data
TIN14 16 B2 Blue pixel data
TIN15 18 B3 Blue pixel data
TIN16 19 B4 Blue pixel data Tout2- No.9 : IN2-
TIN17 20 B5 Blue pixel data(MSB)
TIN18 22 NC No connection Tout2+ N0.10 : IN2+
TIN19 23 NC No connection
TIN20 25 ENAB Compound Synchronization signal
CLK in 26 NCLK Data sampling clock TCLK out-
TCLK out+
No.11 : CLK IN-
No.12 : CLK IN+
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:5
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
Data stream of IN0-/+, IN1-/+ and IN2-/+ for PD104SL3
RxOUT0RxOUT1 RxOUT2RxOUT3 RxOUT4 RxOUT5RxOUT6 IN0
R1 R0 R4 R3 R2 R5 G0
RxOUT7 RxOUT8RxOUT9RxOUT10 RxOUT11 RxOUT13 RxOUT12IN1
G2 G1 G5 G4 G3 B0 B1
RxOUT7 RxOUT8RxOUT9 RxOUT10RxOUT11RxOUT12 RxOUT13 IN2
B3 B2 NC B5 B4NC ENAB
LVDS Interface Block Diagram
G
raphic C
ontroller C
ircuit
TIN0~TIN5
TIN6~TIN11
TIN12~TIN17
TIN18
TIN19
TIN20
TCLK IN
R0~R5
G0~G5
B0~B5
NC
NC
ENAB
CLK IN
TTL parallel to LV
D
S
PLL
DS90C*363
LV
D
S to TTL parallel
PLL
DS90CF364
IN0-
IN0+
RxOUT0~RxOUT5
RxOUT6~RxOUT11
RxOUT12~RxOUT17
RxOUT18
RxOUT19
RxOUT20
CLK OUT
LC
D
Internal C
ircuit
IN1-
IN1+
IN2-
IN2+
CLK-
CLK+
PD104SL3 module sideCustomer system side
5-2) Backlight driving
Connector type : “BHR-02VS-1” of Japan Solderless Terminal MFG Co. LTD
PIN NO. Symbol Description Remark
1 VL1 Input Voltage(High)
2 VL2 Input Voltage(Low)
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:6
PD104SL3
6. Absolute Maximum Ratings:
GND=0V, Ta=25℃
Parameters Symbol MIN. MAX. Unit Remark
Supply Voltage VDD -0.3 +4.0 V
Input Signals Voltage VIN -0.3 VDD+0.3 V Note 6-1
Backlight Driving Voltage VL - 2000 V
Backlight Driving Frequency FL 0 100 KHz
Storage Temperature TST -20 +70 ℃ Note 6-2
Operating Temperature TOP 0 +60 ℃
Note 6-1: LVDS signal
Note 6-2: Humidity : 90% RH Max. at Ta ≤ 40℃.
Maximum wet-bulb temperature is at 39℃or less at Ta > 40℃and no
condensation.
7. Electrical Characteristics
7-1) Recommended Operating Conditions: GND = 0V,Ta = 25℃
Item Symbol Min. Typ. Max. Unit Remark
Supply Voltage VDD 3.0 3.3 3.6 V
Current Dissipation IDD - 350 450 mA Note 7-1
LVDS Differential input high threshold VTH - - 100 mV Note 7-2
LVDS Differential input low threshold VTL -100 - -
Lamp Current IFL 3.0 5.0 6.0 mA 5mA : 160 cd/m2
Note 7-3
Note 7-5
Lamp Voltage VL 500 550 600 Vrms IFL=5mA
Note 7-3
Lamp Initial Voltage VSFL - 1200 - Vrms at Ta=25°C
1000 at Ta=0°C
Lamp Driving Frequency FL - 45 - KHz
Total power consumption (at IFL=5mA) -- 3.91 - W Note 7-4
Note 7-1 : To test the current dissipation of VDD, using the “color bars” testing pattern shown
as below
1 2 3 4 5 6 7 8
1. White
2. Yellow
3. Cyan
4. Green
5. Magenta
6. Red
7. Blue
8. Black
Idd current dissipation testing pattern
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
Ltd. Page:7
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
Note 7-2 : Please refers to DS90CF364 specification by National Semiconductor Corporation.
This LCD module conforms to LVDS standard.
Note 7-3 : The back-light driving waveform should be as closed to sine-wave as possible.
In order to satisfy the quality of B/L , no matter use what kind of inverter , the output lamp
current must between Min. and Max. to avoid the abnormal display image caused by B/L.
Note 7-4 : Not including the efficiency of backlight DC/AC inverter
Note 7-5 : Lamp current is measured with current meter for high frequency as shown below
InverterTFT-LCD
Module
~
A
1
2
* Pin 2 is Vlow
** Current meter :
Yokogawa 2016-01
Lamp current dissipation testing configuration
7-2) Input / Output signal timing chart
(A) Vertical Timing
X,1 X,2 X,3 X,4
X,598 X,599 X,600
X,Y
t1
t2
t3 t3
CLK
ENAB
R5~R0
G5~G0
B5~B0
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Ltd. Page:8
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
(B) Horizontal Timing
t3
t4
tc
CLK
ENAB
R5~R0
G5~G0
B5~B0
1,Y 2,Y 3,Y 4,Y 5,Y 6,Y 7,Y X,Y
798,Y 800,Y
797,Y 799,Y
CLK
t 6 t 7
t 5
VIH(Min):0.8Vcc
VIL(Max):0.2Vcc
ENAB
R5-R0
G5-G0
B5-B0
VALID
DATA
Input Signal
CenterLevel:
0.5Vcc
VIH(Min):0.8Vcc
VIL(Max):0.2Vcc
CLK
a b
0.5Vcc
Duty ( a ,b ) : 50 ± 10%
t 8 t 9
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Ltd. Page:9
PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
D) Timing Specifications
Item Symbol Min. Typ. Max. Unit Remark
Frame Cycling t1 604 X t3 628X t3 800 X t3 -
- 16.58 ms
Vertical Display Period t2 600 X t3 600 X t3 600 X t3 -
Horizontal Scanning Time t3 920 X t5 1056 X t5 1064 X t5 -
26.4 - μs
Horizontal Display Period t4 - 800 X t5 - -
Clock Cycle t5 25.0 - ns
Clock High Level Time t6 9.0 - - ns
Clock Low Level Time t7 9.0 - - ns
Hold time t8 4.0 - - ns
Set-up time t9 5.0 - - ns
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
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PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
7-3) Display Color and Gray Scale Reference
Input Color Data
Color Red Green Blue
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (63) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Green (63) 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0
Basic Blue (63) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red (00) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (01) 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Red (02) 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Darker
Red ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Brighter
Red (61) 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Red (62) 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (63) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Green (00) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green (01) 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Green (02) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Darker
Green ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Brighter
Green (61) 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0
Green (62) 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0
Green (63) 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0
Blue (00) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue (01) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Blue (02) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Darker
Blue ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Brighter
Blue (61) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
Blue (62) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
Blue (63) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co.,
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PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
7-4) Pixel Arrangement
The LCD module pixel arrangement is the stripe.
R G B R G B R G B R G B
R G B R G B
R G B
R G B R G B R G B R G B
R G B R G B
R G B
3 rd Line
2 nd Line
1 st Line
600 th Line
599 th Line
598 th Line
R G B
R G B
R G B
R G B
1 st Pixel 800 th Pixel
1 Pixel = R G B
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PD104SL3
The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be
8.)Power On Sequence
3.0 V 3.0 V0 s< t <35 ms 0 s< t <35 ms
2t1 0
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