USING IGBT MODULES

Sep.1998 4.0 Using IGBT Modules Mitsubishi IGBT modules are designed to be rugged, low loss and easy to use. Use of advanced processing technologies gives low on-state saturation voltages while maintaining the high switching speed needed for 20kHz operation. The information presented in this section is intended to help users of Mitsubishi IGBT modules apply the devices effectively and reliably. 4.1 Structure and Operation of IGBT Module The IGBT, Insulated Gate Bipolar Transistor, is a switching transistor that is controlled by voltage applied to the gate terminal. Device operation and structure are similar to those of an Insulated Gate Field Effect Transistor, more commonly known as a MOSFET. The principal difference between the two device types is that the IGBT uses conductivity modulation to reduce on-state conduction losses. A brief comparison between the structures of the IGBT, MOSFET and npn Bipolar Junction Transistor (BJT) is depicted in Figure 4.1. The npn BJT is a three junction device that requires a continuous current flowing into the base region to supply enough charges to allow the junctions to conduct current. Because the MOSFET and the IGBT are voltage controlled devices, they only require voltage on the gate to maintain conduction through the device. The IGBT has one junction more than the MOSFET, and this Figure 4.1 Three Major Device Technologies MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES B E n+ p n– n+ C SG p n– n+ D n+ SiO2 EG p n– n+ C n+ SiO2 p+ npn POWER BIPOLAR n-CHANNEL POWER MOSFET n-CHANNEL POWER IGBT E C B S D G E C G Low on-state drop conductivity modulation Current control device, large drive power Medium fast switching High on-state drop for majority carrier condition Voltage control drive, small drive power Very fast switching Medium on-state drop for conductivity modulation Voltage control drive, small drive power Fast switching Advantage Disadvantage Sep.1998 junction allows higher blocking voltage and conductivity modulation, as described below, during conduction. This additional junction in the IGBT does limit switching frequency however. 4.1.1 Silicon Structure The IGBT silicon structure is as shown in Figure 4.2. A positive volt- age on the gate attracts electrons from the “p” gate region towards the silicon surface under the gate. These electrons invert the “p” directly under the gate to form an “n” region, thus creating a path for charge flow between the “n” collector region and the “n” emitter region. A zero or negative voltage (depends on the device) on the gate maintains the off-bias. 4.1.2 Device Operation When the device is on, the collector is at a higher voltage than the emitter, and therefore minority carriers are injected from the collector p+ region into the collector bulk region (n+ buffer layer and collector “n” region). The charges reduce the collector bulk region resistance and thus collector to emitter voltage drop is reduced (relative to VDS(on) of MOSFET). When a positive gate voltage is first applied, a gate current flows until the gate capacitance is charged and the gate voltage rises to the “on” level. When the gate voltage is removed, the charges injected into the collector bulk region must be removed before high voltage can be blocked. The IGBT surface emitter pattern is striped geometrically, in contrast to the FET cell-based geometry. The IGBT uses the same small feature size advantages of the MOSFET, but the striped geometry offers more ruggedness and immunity from latch-up of the parasitic thyris- tor shown in Figure 4.3A. A circuit model of a typical IGBT is illustrated in Figure 4.3A. H-Series IGBTs use optimized buffer layer, p± well doping and alignments, gate structure, and surface pattern designs. Minority carrier lifetime control techniques are used to reduce the gain of the “pnp” bi- polar element and minimize lateral RBE values, thus precluding latch- up. Therefore, the equivalent circuit model of a H-Series IGBT is reduced to the schematic in Fig- ure 4.3B. 4.1.3 Wafer Processing IGBT wafer processing is similar to FET processing. The silicon material is a dual epitaxial structure, and gate and emitter regions are diffused and/or ion implanted into the emitter side. Selective doping, electronic irradiation, and other processing techniques are used during emitter-side processing. Many of the same processing techniques used to fabricate FET devices are employed in IGBT manufacture. The high di/dt and dv/dt capabilities of the FETs result from the control of minority carriers near the gate “p” region and collector “n” region interface. The same techniques plus addi- tional steps to control carrier life- time near the collector N+ buffer region help to generate immunity from latch-up and to enhance the Figure 4.2 IGBT Cross Section and Silicon Structure Figure 4.3 IGBT Internal Parasitics MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES n+ p+ E p+p+ n+ n+p p e G LG n– C HOLES Rb e e ELECTRONS RMOD C C E G RBE RMOD C C E G RBE A. MODEL OF CONVENTIONAL TYPE B. MODEL OF Mitsubishi RUGGED IGBT VCE(sat) = VBE + IMOS • RMOD + IMOS • rDS(ON) Sep.1998 switching ruggedness of H-Series IGBTs. Ultra clean facilities and in-line wafer testing promote consistent processing, thus ensuring chips of the highest quality and reliability. 4.1.4 Module Packaging Construction and Layout IGBT modules consist of multiple IGBT chips mounted on an isolated substrate, which is itself mounted on a heatsinking copper base plate (Figure 4.4A). Mitsubishi IGBT modules use an isolating ceramic substrate with copper patterns metallurgicly bonded to the top and bottom surfaces. (Figure 4.4B). This mounting method allows highly automated module assembly while minimizing thermal impedance. Mitsubishi IGBT modules use materials with similar thermal coefficients of expansion so that thermal stress is limited. Thus these IGBT modules can be expected to provide improved thermal cycle life over existing power transistor modules. Free-wheeling diodes are also mounted in the module for ease of system assembly and to allow minimum lead inductance, both inside and outside the module. Interconnection inside the modules is accomplished with rigid bussing to ease assembly. Rigid bussing also offers symmetric layout of internal components so the parasitic inductance is reduced and module ruggedness is enhanced. 4.1.5 Features of U-Series IGBT Packages A new IGBT module package called “U-Series” was developed by Mitsubishi Electric in 1996. The new package technology achieves a significant reduction in internal in- ductance and improved reliability over older designs. The time re- quired to assemble the new mod- ule was substantially reduced by using a special case that has the power electrodes molded into its sides rather than inserted after the case is molded. Figure 4.5 is a cross section drawing of the new IGBT module package. The main electrodes are connected directly to the power chips using large di- ameter aluminum bonding wires. In order to help simplify power circuit and snubber designs or possibly eliminate the need for snubbers al- together an effort was made to minimize the inductance of the new U-Series package. A variety of techniques were used to reduce each component of the package in- ductance. One of the most signifi- cant improvements was made pos- sible by the new insert molded case design. Wide electrodes are molded into the side of the case to form parallel plate structures that have considerably less inductance Figure 4.5 Cross Section of U-Series Module Package MAIN TERMINAL ELECTRODE SILICONE GEL COVER INSERT MOLDED CASE AIN SUBSTRATEPOWER CHIPSCU BASE PLATEAL BOND WIRES CASE (EPOXY RESIN) COMMON (C2E1) EMITTER (E2) COLLECTOR (C1) GATE AND EMITTER (G1, E1, G2, E2) EPOXY RESIN SILICONE GEL ALUMINUM WIRE SILICON CHIP NEW INSULATING BASE (ALN ISOLATOR) BASEPLATE BASE IGBT, FWD CHIP NEW INSULATING PLATE INSULATION MATERIAL COPPER BASE COLLECTOR PLATE INSULATION PLATE COPPER TERMINAL SEMICONDUCTOR CHIP (A) (B) H-SERIES IGBT MODULE CONVENTIONAL POWER MODULE Figure 4.4 Structure of Mitsubishi IGBT Module and Module Base Plate Construction MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES Sep.1998 than conventional electrodes. In addition, the strain relieving “S” bends that were needed in the electrodes of conventional modules are not needed in the U-Series package because the aluminum bond wires perform the strain re- lieving function. Elimination of these “S” bends helped to further reduce the electrode inductance. Overall, as a result of these induc- tance reducing features the U-Se- ries modules typically have about one third the inductance of conven- tional modules. A further reduction in assembly time was achieved by reducing the number of soldering steps during manufacturing. With the conventional module the chip to substrate and substrate to base plate soldering is done first with high temperature solder. Then the case is attached to the base plate and a second low temperature sol- dering step is used to connect the power electrodes. In the new mod- ule the second step is not needed because the connections to the power electrodes are made using the aluminum bond wires. The soldering temperature of the chip and substrate attachment can be reduced. The lower soldering temperature minimizes the effects of the mismatched coefficients of expansion between the base plate and the AlN DBC substrate. The re- sult is a reduction in thermal stress during manufacturing and improved power cycle reliability. 4.2.1 Absolute Maximum Ratings Symbol Parameter Definition VCES Collector-Emitter Blocking Voltage Maximum Off-state collector-emitter voltage with gate-emitter shorted VGES Gate-Emitter Voltage Maximum gate-emitter voltage with collector-emitter shorted IC Continuous Collector Current Maximum collector current – DC ICM Peak Collector Current Repetitive Peak collector current, Tj ≤ 150°C IE Continuous Diode Current Maximum diode current – DC IEM Peak Diode Current Repetitive Diode peak current, Tj ≤ 150°C PC Power Dissipation Maximum power dissipation, per device, TC = 25°C Tj Junction Temperature Allowable range of IGBT junction temperature during operation Viso Isolation Voltage Minimum RMS isolation voltage capability applied electric terminal to base plate, 1 minute duration Mounting Torque Allowable tightening torque for terminal and mounting screws 4.2.2 Electrical Characteristics Symbol Parameter Definition Static ICES Collector-Emitter Leakage Current IC at VCE = VCES, VGE = 0, gate-emitter shorted, Tj = 25°C IGES Gate-Emitter Leakage Current IG at VGE = VGES, VCE = 0, collector-emitter shorted, Tj = 25°C VGE(th) Gate-Emitter Threshold Voltage VGE at IC = specified mA, VCE = 10V VCE(sat) Collector-Emitter Saturation Voltage VCE at IC = rated IC and VGE = 15V QG Total Gate Charge Charge on gate at VCC - 0.5~0.6VCES, rated, IC = rated IC, VGE = 15V VEC Emitter-collector voltage Diode voltage at IE = -rated IC, VGE = 0V Dynamic Cies Input Capacitance Gate-emitter capacitance with VCE = 10V Coes Output Capacitance Collector-emitter capacitance with the gate shorted to the emitter Cres Reverse Transfer Capacitance Gate-collector capacitance with the emitter connected to the guard terminal of the impedance analyzer 4.2 IGBT Module Ratings and Characteristics The ratings as shown in Section 4.2 are most important for IGBT's operation and environment. A maximum rating is a value which establishes either a limiting capability or limiting condition (either maximum or minimum). It is determined for a specified value of environment and operation. Therefore, you cannot use the IGBT module beyond its maximum or minimum rating's value. MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES Sep.1998 4.2.4 Test Circuits and Conditions The following test circuits are used to evaluate IGBT characteristics. 1. VCE(sat) and VEC To ensure specified junction temperature, Tj, measurements of VCE (sat) VCC CURRENT MONITOR VGE L D.U.T. Irr t IC t IE IE Irr trr IE 0.5 Irr Qrr = 1/2 Irr trr +VGE1 -VGE2 E C V ICVGE RG E C V IC +VGE1 -VGE2 RG lC RLOAD VCC Figure 4.6 Reverse Recovery Measurement Circuit and Waveform Figure 4.7 VCE (sat) Test Figure 4.8 VCE Test Figure 4.9 Resistive Load Switching Test Circuit 4.2.2 Electrical Characteristics (Continued) Symbol Parameter Definition Dynamic (Continued) td(on) Turn-on Delay Time Time from VGE = 0V to IC = 10% of final value tr Rise Time Time from IC = 10% of final value to IC = 90% of final value td(off) Turn-off Delay Time Time from VGE = 90% of initial value to IC = 90% of initial value tf Fall Time Time from IC = 90% of initial value to IC = 10% of initial value trr Diode Reverse Recovery Time Time from IC = 0A to projection of zero IC from Irr and 0.5 Irr points with IE = -rated IC and at specified di/dt (Refer to Figure 4.6) Qrr Diode Reverse Recovery Charge Area under Irr curve from IC = 0A to projection of zero IC from Irr and 0.5x Irr points with IE = rated IC and at specified di/dt (Refer to Figure 4.6) 4.2.3 Thermal Characteristics Symbol Parameter Definition Rth(j-c) Thermal Resistance, Junction to Case (Tj - TC)/(IC-X VCE), IC conducting to establish thermal equilibrium Rth(c-f) Thermal Resistance, Case to fin (TC - Tf)/(IC X VCE), IC conducting to establish thermal equilibrium lubricated and VEC must be performed as low duty factor pulsed tests. (See Figures 4.7 and 4.8) 2. Resistive Load Switching Test Circuit. (See Figure 4.9) 3. Half-Bridge Switching Test Circuit (See Figure 4.10) MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES Sep.1998 4.3 Safe Operation Area Protecting IGBTs against disturbance caused by over currents or over voltage is an important design topic in most switching applications. In the case of all hard switching applications, such as inverter or chopper circuits for motor controls and transformer loads, the turn-off switching SOA and short circuit capability are the two most important ratings of IGBTs today. 4.3.1 The Turn-off Switching SOA of IGBT The turn-off switching SOA is simi- lar to RB SOA (Reverse Bias SOA) of Darlington transistors. The switching operation for a typical inverter bridge circuit (Figure 4.11) will generate the current and voltage waveform illustrated in Figure 4.12. In turning off an inductive load current, the voltage rise precedes the current fall. As the gate voltage reduces below its threshold value, the intrastructural MOSFET channel window gets blocked and injection of electrons cease. Removal of the stored minority carriers (holes) in the “n” base region starts, and during this interval, the parasitic wide base pnp transistor operated by vir- tue of its current gain characteristics causing the collector current to continue flowing. Thus, the later part of the IGBT turn-off fall current, is mainly due to the hole current. Some of the holes in the “n” base region continues to cross through the C-B junction of the parasitic npn transistor and travel horizontally below the “n” emitter layer. (Figure 4.13) This flow of holes causes a potential drop across the “p” body resistance, RD, and tends to activate the npn transistor. A turn on of the npn transistor, while the pnp transistor is still active, can lead to pnp thyristor latch-up, which means loss of gate control and, eventually, destruction of the device. This problem has been eliminated in the Mitsubishi IGBTs by careful optimization of the device geometry. The Switching SOA curve is the locus of points defining the maximum allowable simultaneous occurrence of collector current and collector to emitter voltage during turn-off. Figure 4.14 shows that H-Series IGBTs offer square switching SOA for 600V and 1200V devices at 2X rated current. The curves show that independent of VCE, the device current must be kept below 200% rated current. This limit is due to the designed current density of the chips and internal connections in the module. VGE 0 lC 0 90% 90% 10% t t td(on) tr td(off) tf Figure 4.10 Switching Time Waveform +VGE1 -VGE2 RG VCClE lC SHORT Figure 4.11 Half-Bridge Switching Test Circuit MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES Sep.1998 4.3.2 Short Circuit SOA Most power conversion applications require that the applied switch should survive a short circuit on the system output without any damage. When considering short circuit withstand capability of IGBT modules, two distinguishing cases are generally reviewed: Case-1 – Switching on of an IGBT into a short circuit, Case-2 – Load or groundfault short-circuit across a switched on IGBT. Figure 4.15 shows the circuitry and waveforms for each case. In Case-1, as the IGBT turns on, initial rate of rise of IC is determined by the wiring inductance, L. Also, the voltage, VCE, drops to some value below VCC as the L discharges. Soon after this, VCE switches back to almost full VCC level. The dv/dt at this switch back is coupled to the gate through the reverse transfer capacitance thus causing a momentary rise of gate voltage.This extra gate voltage mobilizes more electron and hole plasma within the IGBT module structure. The effect of this translates to a higher peak collector current within a couple of microseconds. The circuit design (e.g. layout, bias condition, selection of RG, maximum supply voltage, etc.) is important to limit the short circuit current magnitude in this high injection state. Due to high current density Figure 4.12 Switching Waveforms (Half-Bridge Mode) TURN-ON 50A/div 100V/div 50ns/div TVCE IC VCEICO RG=3.9 ohm T T T TURN-OFF 50A/div 100V/div 50ns/div EMITTER GATE COLLECTOR RB HOLE N° N° P° P e N° Figure 4.14 Turn-off Switching SOA COLLECTOR-EMITTER VOLTAGE (VOLTS) 0 200 400 600 800 1000 C O LL EC TO R CU RR EN T, I C , (N OR MA LIZ ED TO M OD UL E RA TIN G) 1X 0 1400 LIMIT FOR 600V CLASS (-12H) LIMIT FOR 250V CLASS (-5F) CONDITIONS: Tj = 25∼125°C VGE = ±15V RG = VCC ≤ 2X 1200 LIMIT FOR 1200V CLASS (-24H) LIMIT FOR 1700V CLASS (-34H) SEE TABLE 4.2 RECOMMENDED RANGE 150V (5F) 400V (12H) 800V (24H) 1000V(28H) 1100V (34H) 1600 LIMIT FOR 1400V CLASS (-28H) Figure 4.13 High Injection On-state Electron and Hole Currents within an IGBT Structure MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING IGBT MODULES Sep.1998 within the silicon, the internal temperature rises and it causes the high short circuit peak current to re- duce to a lower value which corre- sponds to what is called a satura- tion current. To protect the device from destruction, the current has to be cut off within a specified period, which is normally specified by the input gate pulse width, tw. At turn off, a sharp fall of collector current in the presence of the wiring inductance, L1, causes VCE to shoot up by an amount equivalent to: ∆VCE ≈ L1 X diC/dt. The instantaneous value of collector-emitter voltage, VCE, including this surge peak value must not be allowed to go beyond the specified voltage limit given by SCSOA. (See Figures 4.16, 4.17, 4.18, 4.19, and 4.20) In Case-2 short circuit an external short circuit occurs while the IGBT is already in the on state. (See Figure 4.15B) The increasing short circuit forces the IGBT chip to desaturate causing the collector- emitter voltage to rise from VCE(sat) to almost full VCC. The dv/dt during IGBT desaturation may be higher compared to Case-1 and is coupled back through the reverse transfer capacitance, which is now higher at the low on-state voltage, and may result in a higher momentary rise of gate voltage. As a result the magni- tude of the short cir