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IC Mask Design.pdf

IC Mask Design.pdf

上传者: wanglongfei_2002
7次下载 0人收藏 暂无简介 简介 2011-06-21 举报

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ChapterPreviewHere’swhatyou’regoingtoseeinthischapter:CloselookatautomatedlayoutsoftwareWhyautomatedlayoutonlyworkswithcertaincellsKnowingthecircuitreallydoeswhatitshouldHowtoknowinadvanceifyourfloorplanchoiceisgoodAutomatedprogramsgettingstuckTroubleshootingtipsWhichnetstowirefirstWhichnetstowirebyhandTechniquestoguaranteerule-perfectlayoutFlowchartofdigitallayoutproceduresLotsoffeedbackloopsHowtokeepthepowermovingthroughbigcellsChickenoreggwiringandtimingcircleDidyoureallybuildwhatyoudesigned?HowtobuildquickiechipsfortestingOpeningThoughtsonDigitalLayoutThemajorityofintegratedcircuitsbuilttodayarelarge.ImeanreallyhugeCMOSdigitalchips.Onechipmighthaveliterallymillionsoftransistorsinit.It’sbeyondanysinglemaskdesigner’scapabilitiestolayoutachiplikethatbyhand—inanyreasonabletimeframe,atleast.Consequently,themajorityoflargedigitalchipsarelaidoutwiththeassistanceofcomputer-aidedtools.1CHAPTER1DigitalLayoutSource:ICMaskDesignEssentialLayoutTechniquesDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Understandinghowtheseautomateddigitallayouttoolsoperateallowsyoutodevelopskillfuldailyhabitsinyourwork—eveninyouranalogwork.Ifyouunderstandhowthesoftwareoperates,youcanlayoutbettercircuitsfaster,compensateforsoftwareinadequacies,andsteerclearofroadblocksbeforetheyhappen.DesignProcessLet’sbuildadigitalchip.Inthischapter,wewillfollowadesignteamastheyprogressfromconcept,throughcircuittesting,andfinallytotheactualgateplacementandwiringofadigitalchip,usingasuiteofsoftwaretools.Let’sstart.It’sthecircuitdesigner’smovefirst.VerifyingtheCircuitryLogicCircuitdesignerstypicallyuselanguagescalledVHDLorVerilogtodesigntheirenormousdigitalcircuits.VHDLstandsforVHSIC(VeryHighSpeedIntegratedCircuits)HardwareDescriptionLanguage,anIEEEstandardsince1987.Verilogisanotherproprietarylogicdescriptionlanguage.WewilluseVHDLinourexamples.CircuitdesignersusetheVHDLlanguagetocreateachipthatexistsfirstasonlyadatabaseofnumbers.Thecircuitdesigner’sVHDLfilesareveryC-like.1Thefilesessentiallysay,forexample,“Iwantacircuitfunctionthataddstwo16-bitnumberstogether.”Inthisway,theVHDLfilesdescribeourmicro-processor,ourdigitalfunctions,orwhateverfunctionsweneed.TheseVHDLdatafilesarethensubmittedtoacomputersimulator,whichteststhechipcircuitrywhileitisstillinsoftwareform.ThelogicfunctionsoftheVHDLcoderunveryquickly,muchfasterthanatraditionaltransistorlevelSPICEsimulation(butnotasfastastherealsilicon.)TheVHDLsimulatorneedstohaveprocess-specificsoftwaredescriptionsofeachlogicfunctionitwantstouse,suchasrisetime,falltime,gatepropaga-tiondelays.Thisinformation,aswellasotherdeviceparameters,isstoredasaseriesoffilesthattheVHDLsimulatorcanaccess.Alongwiththeseelectri-caldescriptions,therearealsophysicalrepresentationsofeachofthegatesthatthesimulatorandlogicsynthesizercanuse.Allofthesefilesarecollec-tivelyknownasastandardcelllibraryorlogiclibrary.2|CHAPTER11Thecomputerlanguage,C.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.BylookingattheresultsoftheseVHDLsimulations,wecanmakeadjust-mentstothecircuitrybeforewecommitthechiptoactualsilicon.Thisisagreatsaving.CompilingaNetlistOncethecircuitdesignerhasfinishedverifyinghislogicdesign,hewillputhisVHDLcodethroughasiliconcompilerorlogicsynthesizer.ThecompilertranslatesthehighlevelC-likecodeintoafilethatcontainsalltherequiredlogicfunctions,aswellashowtheyaretobeconnectedtoeachother.Thefilebasicallysays,“Inordertoaddtwo16-bitnumberstogether,Ineed25gatesandhere’showtheyshouldbeconnected.”Inthisway,allourlogicfunc-tionsarecreatedandcross-referenced.DigitalLayout|3VHDLCodeSegmentarchitectureSTRUCTUREofTESTiscomponentand2xport(A,B,C,D:instd_ulogic:=‘1’;Y:outstd_ulogic);endcomponent;constantVCC:std_ulogic:=‘1’;signalT,Q:std_ulogic_vector(4downto0);beginT(0)<=VCC;A1:and2xportmap(A=>Q(0),B=>Q(1),Y=>T(2));A2:and2xportmap(A=>Q(0),B=>Q(1),C=>Q(2),D=>Q(3),Y=>T(4));Count<=Q;Thecompanythatissupplyingyoursiliconusuallyprovidesastandardcelllibrary.Theoretically,youaregivenalibrary,whichisperfect,andwillstayperfect.However,updatestothelibrarycanoccurquitefre-quently.Changestothelibrarycancauseaonce-perfectchiptostopfunctioning,especiallyifmistakeshavebeenmadeintheupdates.Updatingalibrarymid-projectisusuallyabadmove.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Atthispoint,weknowwhatgatesweneed,andweknowhowtheymustbeeventuallywiredtoeachother.Thisfile,calledanetlist,willdriveyourauto-matedlayouttools.4|CHAPTER1NetlistSegmentmoduletest(in1,in2,out1);inputin1,in2;outputout1;wire\net1,\net2,\net3;AND2_2XU1(.Z(net1),.A(net2),.B(net3));AND4_2XU2(.Z(net1),.A(net2),.B(net3),.C(net2),.D(net1));endmoduleAsthecircuitdesignerbeginstocompiletheVHDLcode,hewillcontrolvar-iousswitches.Theswitchescontrolparameterssuchasarea,power,andspeed.Dependingonchiprequirements,thecircuitdesignermightdecidetocompiletheVHDLtoprioritizeonlyspeed,onlyarea,onlypower,orsomespecificcombinationoftheseinterests.Resultswillvarydependingonthesepriorities,soheinputsthesechoicestothecompilerbeforeitbegins.DriveStrengthThecompilercancreatenetsthatareextremelylarge.Theremaybehundredsofthousandsofcellsononeparticularnet,forinstance.Themorecellswehaveonanet,themorepowerweneedtodrivethem.Ifwetrytodrivetoomanygatesfromasinglesource,wemightoverloadourdrivingtransistors.Ourcircuitwillnotwork.Therefore,beforewecanstartlayout,weneedtomodifythenetlisttomakesurethattheselargenetsareadequatelydriven.Todothis,wereplacethecellsthataredrivingthenetwithcellsofidenticallogicfunctionthathavelargerdrivingcapability.Drivingcapabilityisreferredtoasthedrivestrength,orfanout,ofthecell.Thefanoutnumberindicateshowmanydevicesagatecandrive.Adrivinggatecanbeanycellinalibrary.Forexample,wemightseethatourcelllibraryhas10or15differentsizesofinverters.Theseinverterselectionsmightbereferredtoas1x,2x,or4xinvert-ers.Thesedesignationsontheinvertersrefertothedrivestrengthofeachinverter.Sincea1xcantypicallydrivetwogates,a2xwoulddrivefourgates,anda4xwoulddriveeightgates.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.DigitalLayout|5Figure1–1.Oneinverterdrivestwoloads,soa2xdrives4loads,anda4xdrives8loads.Youmightwonderwhywedon’tjustbuildonehugegatetocoverallcircuiteventualities.Wecoulddothat.However,wewouldwastecircuitareaandburnmorepowerthanisnecessary.Thewisesttechniqueistobesurethatyoucandrivewhatyouneed,andnomore.So,duringthecompilationprocess,thecompilerexaminesthenumberofgatesoneachnetandadjuststhesizeofthegatedrivingeachnetaccordingly.Ifthenetistoolargetobedrivenbyourmaximumdrivestrengthdevice,thecompilerwillbreakthenetintosmallersectionsthatareeasiertodrive.BufferCellsIfthecompilerbreaksalargenetintosmaller,moreeasilydrivensections,itwillinsertadditionalgatestodriveeachsmallernewlycreatednet.Theseextragateswerenotpartoftheoriginallogic.Thecircuitdesignerdidnotaddthem.Youdidnotaddthem.Thecomputermadethedecisionbyitself.Theseextragatesarecalledbuffercells.Buffercellshelpdrivegateandwiringcapacitance.Abuffercellhasnologicfunctionassociatedwithit.Whateverlogicsignalisfedintothebuffercellappearsatitsoutput.Inthenextsection,wewillseeanexampleofhowthecompilerusesthesecon-ceptstodrivealargeclocknet.ClockTreeSynthesisMostdigitalcircuitshaveaclockwaveformthatclicksawayintheback-ground.Everyfunctionissynchronizedtothatclick.Thewiringnetsforthisclocktimingsignalarecalledclocknets.Aclocknetisusuallyverylarge.Typically,thenetconnectstothousandsofgates.Itisimpossibletocreateacellwithenoughdrivestrengthtodriveallthegatesonaclocknet,sowehavetodosomeextraworktogettheclocknettofunc-tion.Wesplittheclocknetintosmallersectionsandaddbuffercells,asmen-tionedpreviously.Thenetissplitintoabranching-outpattern,calledaclocktree.Establishingthetreeiscalledclocktreesynthesis.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Toillustratehowthetreeconceptworks,let’slookatasmallexample.Let’ssayacertainclocknethassixgatesonit,andthemaximumdrivestrengthourlibraryoffersisafanoutofonlythree.Therefore,wecannotexpectonegatetodrivetheentireclocknet.So,webreakthenetintotwosmallersections,anddriveeachsectionseparately.6|CHAPTER1Figure1–2.Addingbufferstosmallersetsofgatestohelpdrivethesignal.YoucanseeinFigure1–2,thatthecompileraddedtwolowerlevelbufferstothecircuit,onebuffertodriveeachsetofthreegates.Thecompileralsoaddedanotherhigherlevelbuffertodrivethetwolowerlevelbuffers.So,threeextracellshavebeenaddedtoourcircuit.Ifourclocknetwasevenlarger,thecompilerwouldcontinuebranchinginthismanner,splittingthenetandaddingadditionalbuffercells,eachonedrivingnomorethanthreeothers.Youcanseehowthiswouldformaverylargetreewithmanylevels.Figure1–3.Largenetsarebrokenintomanysmallersectionsthatcanmoreeasilybedriven.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Withalargenumberofaddedbuffercells,theextracellswillintroduceextradelaysthatwerenotaccountedforintheoriginalsimulations.Notonlythat,butotherlargenetsmayrequirethissamesortoftreesynthesisaswell,addingevenmorebuffercells,alsocreatingdelays.Therefore,oncetheclocknetissynthe-sized,andanyotherlargefanoutnetsarebuffered,weneedtore-simulateourdesignusingthecompilednetlist.Compilingcreatesaneedtore-simulate.Thissortofiterationiscommoninchipdevelopment.Thegoodnewsisthatitisnotanever-endingstory.Atsomepoint,youwillhaveafinishednetlist.Wearenowreadytostartthelayoutprocess.Webeginwithfloorplanning.LayoutProcessWearenowreadytouseasuite,orpackage,ofautomatedsoftwaretoolscalledtheplaceandroutetools.Placeandroutetoolscoverthegamutofhigherlevelandlowerlevelsoftwareassistanceleadingtoyourfinallayout.Asthenameimplies,theseprogramsgenerallyplacethegatesandroutethewires,inadditiontootherhelpfulfunctions.FloorplanningThefirstpieceofsoftwarewewillusefromtheplaceandroutetoolsuiteiscalledthefloorplanningtool.Itwillhelpyoucreateareasoffunctionalityonyourchip,determinetheconnectivitybetweentheseareas,determineyourI/Opadplacements,andgiveyoufeedbackonhoweasyyourfloorplanmightbetowire.Thefloorplanningtoolgetsitsconnectivityandgateinformationbasedonthenetlistfile,createdbythecompilersoftware.Let’sfollowthefloorplanningtoolinmoredetail,beginningwithyourinitialdecisions.BlockPlacementTypically,yourchipwillbedividedintovariousfunctionalareas.Forexample,ifyouareworkingonalargedigitalchip,theremightbeamicroprocessorunitinyourchip(MPU),perhapsafloatingpointunit(FPU),maybeaRAMblockandaROMblock.Whereyoulocateeachareaoffunctionalityisyourdecision,notthecom-puter’s.Youmightsay,“Ok,allofthegatesforthemicroprocessorIwantinthebottomlefthandcorner.AllthegatesfortheRAMIwantinthetoprightcorner.”Andsoon.Youwillhaveachancetochangethesedecisionslater,onceyouseehowyourdecisionsmightaffectyourlayout,particularlythewiring.DigitalLayout|7DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.GateGroupingOnceyourareasoffunctionalityarespecified,thefirsttaskyouwouldwanttodoisgathertogether,tosomedegree,thegatesusedineachblock.YouwouldnotwantFPUgatesscatteredthroughouttheROMorRAMblocks,forexam-ple.Associatedgatesshouldallbelocatedneareachother.Thefloorplanningtoolbeginsbyhelpingyougatheryourgatestogether.Theexactplacementofeachgateisnotdeterminedatthispoint.Wedonotyetneedthislevelofdetail.Besides,wemightbechangingourblockplacementdeci-sionsatsomelaterpoint.Sogeneralvicinityplacementisgoodenoughfornow.BlockLevelConnectivityNext,yourfloorplanningtoolwillhelpyouplacetheinputandoutput(I/O)cellsofyourchip.Forinstance,youwouldwantalltheinputsthatgototheFPUclosetotheFPUblockinthecorner.Tohelpyouwiththis,sometoolswillactuallyplacetheI/Ocellsintheappropriateareasautomatically;othertoolswillprovidegraphicfeedbackforyoubasedonyourplacementdecisions.8|CHAPTER1Figure1–5.Inputsandoutputscanbelocatedneartheirappropriatecellblock.Thefloorplanningtoolalsoshowsbasicwiringconnectionsthatmusttravelbetweenblocks.ItwillshowconnectionsbetweentheFPUandtheRAMblocks,forexample.Figure1–4.Chipshavewell-definedareasoffunctionality.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.UsingFlylinesTypically,thefloorplanningtoolwillshowyouallthewiringlinescomingfromeachblockconnectingtotheI/Opadsandtootherblocks.Allthesemyr-iadofwiringlinesarewhatmosttoolscallrat’snestsorflylines.Asyouclick,drag,andresizeblocksaroundyourcomputermonitor,youwillseeallthesewiringconnectionsmovingaroundinrealtimewithyourcursor.Asyoudragyourblocksaroundwithyourcursor,watchthelines.Ifthelinesbecomebadlycrossed-overandgenerallymessy,youknowthatitwillbetoughtowirethecircuitry.Iftherearenocross-oversoftheflylines,thenitwillbeeasytowire.DigitalLayout|9Theautomatedsoftwareprogramssuchasthesimulatorandplaceandroutetoolsmakechoicesaconscientioushumanwithenoughtimewouldmake,giventhesameinformation.(Wehope.)However,youcanseethatconstanthumaninterventionandmonitoringareessential.Thesoftwareneveroperateswithouthumansupervision(you).Youhavebroadlydefinedwhereyouwantyourhighlevelsoffunctionalityandyourinputsandyouroutputs.Youhavepredeterminedsomebasiclayoutinstructionsforthesoftware,dependingonthechipspecifications,thesizeofthefinalpackageinwhichtheywillbeplaced,thespecificcir-cuitry,andultimately,onyourunderstandingofhowthesoftwareoperates.Thetoolsneverruncompletelybythemselves.Thehumanbrainmustoverseetheworkingofthetoolsorthetoolsbecomeuseless.2Figure1–6.Neatflylinesindicategoodfloorplanning.2Justasspellcheckerskneadahumanaye.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Youwillmakechangestoyourblockfloorplansothatyourrat’snesteventu-allylooksasclean,nice,andwireableaspossible.3Youmightdecidetorelo-cateentireareasoffunctionality.Youmightbringonesmallblockacrosstotheothersideandfititbetweentwolargerblocks.Youmightbringacenterblocktotheoutside,oranoutsideblocktothecenter.Whenyoufinallyhaveablockdiagramwhichgivesyounice,simplewiring,yousaveyourfloorplanningoutputfiles.TimingChecksSincethefinalfloorplanningtooloutputfilesspecifywherethegateswillbegenerallylocated,theplacementtoolroughlyknowshowlongallthewireswillbe.Thesewiringlengthestimationsarebasedonthephysicaldimensionsofthedigitallibrary.Usingthisinformation,yourfloorplanningtoolcanoutputanestimatedwirelengthfilethatgoesbackintothedigitalcircuitsimulator.Younowcanrunsomesimulationstodeterminehowyourestimatedwiringlengthswillaffectyourdigitalcircuit.Youmustcheckthepossibilitythatlongwireswillslowthecircuitsignalstoomuch,affectingthecircuittiming.10|CHAPTER1Figure1–7.Thefloorplan/timingloop.3AsChrisalwayssays,“Idon’tcareifitworks,aslongasitlooksgood.”DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Ifthewirelengthsareindeedoverlyaffectingthecircuittiming,thedesignerwillneedtomodifyhisdesign,basedonyourfloorplan.Hewillchangethenetlist.Hemightplacehigher-poweredcellsintheblocktodrivetheextrawiringcapacitances,forexample.Asthedesignerworkstobetterorganizethedesign,notonlyisiteasiertowire,butyouwillfindthechipoperatesbetterintheend.Yougoaroundthisfloorplanandtimingcheckloopacoupleoftimes.Thesimulatorwilleventuallyletyouknowwhenyouhavemetthetimingcriteria.So,atsomepoint,youdecideyoufinallyhaveagooddesign.Youthenmoveontocementingyourdevicesinplace,sotospeak.Thefine-tuningnowbeginsthatwehavebeenputtingoff.PlacementWecannownaildowntheexactpositionsofallthelogicgateswithineachblock,usingaplacementtool.Inthenextsection,wewill

IC Mask Design.pdf

IC Mask Design.pdf

上传者: wanglongfei_2002
7次下载 0人收藏 暂无简介 简介 2011-06-21 举报

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ChapterPreviewHere’swhatyou’regoingtoseeinthischapter:CloselookatautomatedlayoutsoftwareWhyautomatedlayoutonlyworkswithcertaincellsKnowingthecircuitreallydoeswhatitshouldHowtoknowinadvanceifyourfloorplanchoiceisgoodAutomatedprogramsgettingstuckTroubleshootingtipsWhichnetstowirefirstWhichnetstowirebyhandTechniquestoguaranteerule-perfectlayoutFlowchartofdigitallayoutproceduresLotsoffeedbackloopsHowtokeepthepowermovingthroughbigcellsChickenoreggwiringandtimingcircleDidyoureallybuildwhatyoudesigned?HowtobuildquickiechipsfortestingOpeningThoughtsonDigitalLayoutThemajorityofintegratedcircuitsbuilttodayarelarge.ImeanreallyhugeCMOSdigitalchips.Onechipmighthaveliterallymillionsoftransistorsinit.It’sbeyondanysinglemaskdesigner’scapabilitiestolayoutachiplikethatbyhand—inanyreasonabletimeframe,atleast.Consequently,themajorityoflargedigitalchipsarelaidoutwiththeassistanceofcomputer-aidedtools.1CHAPTER1DigitalLayoutSource:ICMaskDesignEssentialLayoutTechniquesDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Understandinghowtheseautomateddigitallayouttoolsoperateallowsyoutodevelopskillfuldailyhabitsinyourwork—eveninyouranalogwork.Ifyouunderstandhowthesoftwareoperates,youcanlayoutbettercircuitsfaster,compensateforsoftwareinadequacies,andsteerclearofroadblocksbeforetheyhappen.DesignProcessLet’sbuildadigitalchip.Inthischapter,wewillfollowadesignteamastheyprogressfromconcept,throughcircuittesting,andfinallytotheactualgateplacementandwiringofadigitalchip,usingasuiteofsoftwaretools.Let’sstart.It’sthecircuitdesigner’smovefirst.VerifyingtheCircuitryLogicCircuitdesignerstypicallyuselanguagescalledVHDLorVerilogtodesigntheirenormousdigitalcircuits.VHDLstandsforVHSIC(VeryHighSpeedIntegratedCircuits)HardwareDescriptionLanguage,anIEEEstandardsince1987.Verilogisanotherproprietarylogicdescriptionlanguage.WewilluseVHDLinourexamples.CircuitdesignersusetheVHDLlanguagetocreateachipthatexistsfirstasonlyadatabaseofnumbers.Thecircuitdesigner’sVHDLfilesareveryC-like.1Thefilesessentiallysay,forexample,“Iwantacircuitfunctionthataddstwo16-bitnumberstogether.”Inthisway,theVHDLfilesdescribeourmicro-processor,ourdigitalfunctions,orwhateverfunctionsweneed.TheseVHDLdatafilesarethensubmittedtoacomputersimulator,whichteststhechipcircuitrywhileitisstillinsoftwareform.ThelogicfunctionsoftheVHDLcoderunveryquickly,muchfasterthanatraditionaltransistorlevelSPICEsimulation(butnotasfastastherealsilicon.)TheVHDLsimulatorneedstohaveprocess-specificsoftwaredescriptionsofeachlogicfunctionitwantstouse,suchasrisetime,falltime,gatepropaga-tiondelays.Thisinformation,aswellasotherdeviceparameters,isstoredasaseriesoffilesthattheVHDLsimulatorcanaccess.Alongwiththeseelectri-caldescriptions,therearealsophysicalrepresentationsofeachofthegatesthatthesimulatorandlogicsynthesizercanuse.Allofthesefilesarecollec-tivelyknownasastandardcelllibraryorlogiclibrary.2|CHAPTER11Thecomputerlanguage,C.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.BylookingattheresultsoftheseVHDLsimulations,wecanmakeadjust-mentstothecircuitrybeforewecommitthechiptoactualsilicon.Thisisagreatsaving.CompilingaNetlistOncethecircuitdesignerhasfinishedverifyinghislogicdesign,hewillputhisVHDLcodethroughasiliconcompilerorlogicsynthesizer.ThecompilertranslatesthehighlevelC-likecodeintoafilethatcontainsalltherequiredlogicfunctions,aswellashowtheyaretobeconnectedtoeachother.Thefilebasicallysays,“Inordertoaddtwo16-bitnumberstogether,Ineed25gatesandhere’showtheyshouldbeconnected.”Inthisway,allourlogicfunc-tionsarecreatedandcross-referenced.DigitalLayout|3VHDLCodeSegmentarchitectureSTRUCTUREofTESTiscomponentand2xport(A,B,C,D:instd_ulogic:=‘1’;Y:outstd_ulogic);endcomponent;constantVCC:std_ulogic:=‘1’;signalT,Q:std_ulogic_vector(4downto0);beginT(0)<=VCC;A1:and2xportmap(A=>Q(0),B=>Q(1),Y=>T(2));A2:and2xportmap(A=>Q(0),B=>Q(1),C=>Q(2),D=>Q(3),Y=>T(4));Count<=Q;Thecompanythatissupplyingyoursiliconusuallyprovidesastandardcelllibrary.Theoretically,youaregivenalibrary,whichisperfect,andwillstayperfect.However,updatestothelibrarycanoccurquitefre-quently.Changestothelibrarycancauseaonce-perfectchiptostopfunctioning,especiallyifmistakeshavebeenmadeintheupdates.Updatingalibrarymid-projectisusuallyabadmove.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Atthispoint,weknowwhatgatesweneed,andweknowhowtheymustbeeventuallywiredtoeachother.Thisfile,calledanetlist,willdriveyourauto-matedlayouttools.4|CHAPTER1NetlistSegmentmoduletest(in1,in2,out1);inputin1,in2;outputout1;wire\net1,\net2,\net3;AND2_2XU1(.Z(net1),.A(net2),.B(net3));AND4_2XU2(.Z(net1),.A(net2),.B(net3),.C(net2),.D(net1));endmoduleAsthecircuitdesignerbeginstocompiletheVHDLcode,hewillcontrolvar-iousswitches.Theswitchescontrolparameterssuchasarea,power,andspeed.Dependingonchiprequirements,thecircuitdesignermightdecidetocompiletheVHDLtoprioritizeonlyspeed,onlyarea,onlypower,orsomespecificcombinationoftheseinterests.Resultswillvarydependingonthesepriorities,soheinputsthesechoicestothecompilerbeforeitbegins.DriveStrengthThecompilercancreatenetsthatareextremelylarge.Theremaybehundredsofthousandsofcellsononeparticularnet,forinstance.Themorecellswehaveonanet,themorepowerweneedtodrivethem.Ifwetrytodrivetoomanygatesfromasinglesource,wemightoverloadourdrivingtransistors.Ourcircuitwillnotwork.Therefore,beforewecanstartlayout,weneedtomodifythenetlisttomakesurethattheselargenetsareadequatelydriven.Todothis,wereplacethecellsthataredrivingthenetwithcellsofidenticallogicfunctionthathavelargerdrivingcapability.Drivingcapabilityisreferredtoasthedrivestrength,orfanout,ofthecell.Thefanoutnumberindicateshowmanydevicesagatecandrive.Adrivinggatecanbeanycellinalibrary.Forexample,wemightseethatourcelllibraryhas10or15differentsizesofinverters.Theseinverterselectionsmightbereferredtoas1x,2x,or4xinvert-ers.Thesedesignationsontheinvertersrefertothedrivestrengthofeachinverter.Sincea1xcantypicallydrivetwogates,a2xwoulddrivefourgates,anda4xwoulddriveeightgates.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.DigitalLayout|5Figure1–1.Oneinverterdrivestwoloads,soa2xdrives4loads,anda4xdrives8loads.Youmightwonderwhywedon’tjustbuildonehugegatetocoverallcircuiteventualities.Wecoulddothat.However,wewouldwastecircuitareaandburnmorepowerthanisnecessary.Thewisesttechniqueistobesurethatyoucandrivewhatyouneed,andnomore.So,duringthecompilationprocess,thecompilerexaminesthenumberofgatesoneachnetandadjuststhesizeofthegatedrivingeachnetaccordingly.Ifthenetistoolargetobedrivenbyourmaximumdrivestrengthdevice,thecompilerwillbreakthenetintosmallersectionsthatareeasiertodrive.BufferCellsIfthecompilerbreaksalargenetintosmaller,moreeasilydrivensections,itwillinsertadditionalgatestodriveeachsmallernewlycreatednet.Theseextragateswerenotpartoftheoriginallogic.Thecircuitdesignerdidnotaddthem.Youdidnotaddthem.Thecomputermadethedecisionbyitself.Theseextragatesarecalledbuffercells.Buffercellshelpdrivegateandwiringcapacitance.Abuffercellhasnologicfunctionassociatedwithit.Whateverlogicsignalisfedintothebuffercellappearsatitsoutput.Inthenextsection,wewillseeanexampleofhowthecompilerusesthesecon-ceptstodrivealargeclocknet.ClockTreeSynthesisMostdigitalcircuitshaveaclockwaveformthatclicksawayintheback-ground.Everyfunctionissynchronizedtothatclick.Thewiringnetsforthisclocktimingsignalarecalledclocknets.Aclocknetisusuallyverylarge.Typically,thenetconnectstothousandsofgates.Itisimpossibletocreateacellwithenoughdrivestrengthtodriveallthegatesonaclocknet,sowehavetodosomeextraworktogettheclocknettofunc-tion.Wesplittheclocknetintosmallersectionsandaddbuffercells,asmen-tionedpreviously.Thenetissplitintoabranching-outpattern,calledaclocktree.Establishingthetreeiscalledclocktreesynthesis.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Toillustratehowthetreeconceptworks,let’slookatasmallexample.Let’ssayacertainclocknethassixgatesonit,andthemaximumdrivestrengthourlibraryoffersisafanoutofonlythree.Therefore,wecannotexpectonegatetodrivetheentireclocknet.So,webreakthenetintotwosmallersections,anddriveeachsectionseparately.6|CHAPTER1Figure1–2.Addingbufferstosmallersetsofgatestohelpdrivethesignal.YoucanseeinFigure1–2,thatthecompileraddedtwolowerlevelbufferstothecircuit,onebuffertodriveeachsetofthreegates.Thecompileralsoaddedanotherhigherlevelbuffertodrivethetwolowerlevelbuffers.So,threeextracellshavebeenaddedtoourcircuit.Ifourclocknetwasevenlarger,thecompilerwouldcontinuebranchinginthismanner,splittingthenetandaddingadditionalbuffercells,eachonedrivingnomorethanthreeothers.Youcanseehowthiswouldformaverylargetreewithmanylevels.Figure1–3.Largenetsarebrokenintomanysmallersectionsthatcanmoreeasilybedriven.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Withalargenumberofaddedbuffercells,theextracellswillintroduceextradelaysthatwerenotaccountedforintheoriginalsimulations.Notonlythat,butotherlargenetsmayrequirethissamesortoftreesynthesisaswell,addingevenmorebuffercells,alsocreatingdelays.Therefore,oncetheclocknetissynthe-sized,andanyotherlargefanoutnetsarebuffered,weneedtore-simulateourdesignusingthecompilednetlist.Compilingcreatesaneedtore-simulate.Thissortofiterationiscommoninchipdevelopment.Thegoodnewsisthatitisnotanever-endingstory.Atsomepoint,youwillhaveafinishednetlist.Wearenowreadytostartthelayoutprocess.Webeginwithfloorplanning.LayoutProcessWearenowreadytouseasuite,orpackage,ofautomatedsoftwaretoolscalledtheplaceandroutetools.Placeandroutetoolscoverthegamutofhigherlevelandlowerlevelsoftwareassistanceleadingtoyourfinallayout.Asthenameimplies,theseprogramsgenerallyplacethegatesandroutethewires,inadditiontootherhelpfulfunctions.FloorplanningThefirstpieceofsoftwarewewillusefromtheplaceandroutetoolsuiteiscalledthefloorplanningtool.Itwillhelpyoucreateareasoffunctionalityonyourchip,determinetheconnectivitybetweentheseareas,determineyourI/Opadplacements,andgiveyoufeedbackonhoweasyyourfloorplanmightbetowire.Thefloorplanningtoolgetsitsconnectivityandgateinformationbasedonthenetlistfile,createdbythecompilersoftware.Let’sfollowthefloorplanningtoolinmoredetail,beginningwithyourinitialdecisions.BlockPlacementTypically,yourchipwillbedividedintovariousfunctionalareas.Forexample,ifyouareworkingonalargedigitalchip,theremightbeamicroprocessorunitinyourchip(MPU),perhapsafloatingpointunit(FPU),maybeaRAMblockandaROMblock.Whereyoulocateeachareaoffunctionalityisyourdecision,notthecom-puter’s.Youmightsay,“Ok,allofthegatesforthemicroprocessorIwantinthebottomlefthandcorner.AllthegatesfortheRAMIwantinthetoprightcorner.”Andsoon.Youwillhaveachancetochangethesedecisionslater,onceyouseehowyourdecisionsmightaffectyourlayout,particularlythewiring.DigitalLayout|7DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.GateGroupingOnceyourareasoffunctionalityarespecified,thefirsttaskyouwouldwanttodoisgathertogether,tosomedegree,thegatesusedineachblock.YouwouldnotwantFPUgatesscatteredthroughouttheROMorRAMblocks,forexam-ple.Associatedgatesshouldallbelocatedneareachother.Thefloorplanningtoolbeginsbyhelpingyougatheryourgatestogether.Theexactplacementofeachgateisnotdeterminedatthispoint.Wedonotyetneedthislevelofdetail.Besides,wemightbechangingourblockplacementdeci-sionsatsomelaterpoint.Sogeneralvicinityplacementisgoodenoughfornow.BlockLevelConnectivityNext,yourfloorplanningtoolwillhelpyouplacetheinputandoutput(I/O)cellsofyourchip.Forinstance,youwouldwantalltheinputsthatgototheFPUclosetotheFPUblockinthecorner.Tohelpyouwiththis,sometoolswillactuallyplacetheI/Ocellsintheappropriateareasautomatically;othertoolswillprovidegraphicfeedbackforyoubasedonyourplacementdecisions.8|CHAPTER1Figure1–5.Inputsandoutputscanbelocatedneartheirappropriatecellblock.Thefloorplanningtoolalsoshowsbasicwiringconnectionsthatmusttravelbetweenblocks.ItwillshowconnectionsbetweentheFPUandtheRAMblocks,forexample.Figure1–4.Chipshavewell-definedareasoffunctionality.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.UsingFlylinesTypically,thefloorplanningtoolwillshowyouallthewiringlinescomingfromeachblockconnectingtotheI/Opadsandtootherblocks.Allthesemyr-iadofwiringlinesarewhatmosttoolscallrat’snestsorflylines.Asyouclick,drag,andresizeblocksaroundyourcomputermonitor,youwillseeallthesewiringconnectionsmovingaroundinrealtimewithyourcursor.Asyoudragyourblocksaroundwithyourcursor,watchthelines.Ifthelinesbecomebadlycrossed-overandgenerallymessy,youknowthatitwillbetoughtowirethecircuitry.Iftherearenocross-oversoftheflylines,thenitwillbeeasytowire.DigitalLayout|9Theautomatedsoftwareprogramssuchasthesimulatorandplaceandroutetoolsmakechoicesaconscientioushumanwithenoughtimewouldmake,giventhesameinformation.(Wehope.)However,youcanseethatconstanthumaninterventionandmonitoringareessential.Thesoftwareneveroperateswithouthumansupervision(you).Youhavebroadlydefinedwhereyouwantyourhighlevelsoffunctionalityandyourinputsandyouroutputs.Youhavepredeterminedsomebasiclayoutinstructionsforthesoftware,dependingonthechipspecifications,thesizeofthefinalpackageinwhichtheywillbeplaced,thespecificcir-cuitry,andultimately,onyourunderstandingofhowthesoftwareoperates.Thetoolsneverruncompletelybythemselves.Thehumanbrainmustoverseetheworkingofthetoolsorthetoolsbecomeuseless.2Figure1–6.Neatflylinesindicategoodfloorplanning.2Justasspellcheckerskneadahumanaye.DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Youwillmakechangestoyourblockfloorplansothatyourrat’snesteventu-allylooksasclean,nice,andwireableaspossible.3Youmightdecidetorelo-cateentireareasoffunctionality.Youmightbringonesmallblockacrosstotheothersideandfititbetweentwolargerblocks.Youmightbringacenterblocktotheoutside,oranoutsideblocktothecenter.Whenyoufinallyhaveablockdiagramwhichgivesyounice,simplewiring,yousaveyourfloorplanningoutputfiles.TimingChecksSincethefinalfloorplanningtooloutputfilesspecifywherethegateswillbegenerallylocated,theplacementtoolroughlyknowshowlongallthewireswillbe.Thesewiringlengthestimationsarebasedonthephysicaldimensionsofthedigitallibrary.Usingthisinformation,yourfloorplanningtoolcanoutputanestimatedwirelengthfilethatgoesbackintothedigitalcircuitsimulator.Younowcanrunsomesimulationstodeterminehowyourestimatedwiringlengthswillaffectyourdigitalcircuit.Youmustcheckthepossibilitythatlongwireswillslowthecircuitsignalstoomuch,affectingthecircuittiming.10|CHAPTER1Figure1–7.Thefloorplan/timingloop.3AsChrisalwayssays,“Idon’tcareifitworks,aslongasitlooksgood.”DigitalLayoutDownloadedfromDigitalEngineeringLibrary@McGraw-Hill(www.digitalengineeringlibrary.com)Copyright2004TheMcGraw-HillCompanies.Allrightsreserved.AnyuseissubjecttotheTermsofUseasgivenatthewebsite.Ifthewirelengthsareindeedoverlyaffectingthecircuittiming,thedesignerwillneedtomodifyhisdesign,basedonyourfloorplan.Hewillchangethenetlist.Hemightplacehigher-poweredcellsintheblocktodrivetheextrawiringcapacitances,forexample.Asthedesignerworkstobetterorganizethedesign,notonlyisiteasiertowire,butyouwillfindthechipoperatesbetterintheend.Yougoaroundthisfloorplanandtimingcheckloopacoupleoftimes.Thesimulatorwilleventuallyletyouknowwhenyouhavemetthetimingcriteria.So,atsomepoint,youdecideyoufinallyhaveagooddesign.Youthenmoveontocementingyourdevicesinplace,sotospeak.Thefine-tuningnowbeginsthatwehavebeenputtingoff.PlacementWecannownaildowntheexactpositionsofallthelogicgateswithineachblock,usingaplacementtool.Inthenextsection,wewill
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