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IC Mask Design.pdf

IC Mask Design.pdf

上传者: wanglongfei_2002 2011-06-21 评分1 评论0 下载7 收藏10 阅读量899 暂无简介 简介 举报

简介:本文档为《IC Mask Designpdf》,可适用于硬件技术领域,主题内容包含ChapterPreviewHere’swhatyou’regoingtoseeinthischapter:Closelookatautomated符等。

ChapterPreviewHere’swhatyou’regoingtoseeinthischapter:CloselookatautomatedlayoutsoftwareWhyautomatedlayoutonlyworkswithcertaincellsKnowingthecircuitreallydoeswhatitshouldHowtoknowinadvanceifyourfloorplanchoiceisgoodAutomatedprogramsgettingstuckTroubleshootingtipsWhichnetstowirefirstWhichnetstowirebyhandTechniquestoguaranteeruleperfectlayoutFlowchartofdigitallayoutproceduresLotsoffeedbackloopsHowtokeepthepowermovingthroughbigcellsChickenoreggwiringandtimingcircleDidyoureallybuildwhatyoudesignedHowtobuildquickiechipsfortestingOpeningThoughtsonDigitalLayoutThemajorityofintegratedcircuitsbuilttodayarelargeImeanreallyhugeCMOSdigitalchipsOnechipmighthaveliterallymillionsoftransistorsinitIt’sbeyondanysinglemaskdesigner’scapabilitiestolayoutachiplikethatbyhandinanyreasonabletimeframe,atleastConsequently,themajorityoflargedigitalchipsarelaidoutwiththeassistanceofcomputeraidedtoolsCHAPTERDigitalLayoutSource:ICMaskDesignEssentialLayoutTechniquesDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteUnderstandinghowtheseautomateddigitallayouttoolsoperateallowsyoutodevelopskillfuldailyhabitsinyourworkeveninyouranalogworkIfyouunderstandhowthesoftwareoperates,youcanlayoutbettercircuitsfaster,compensateforsoftwareinadequacies,andsteerclearofroadblocksbeforetheyhappenDesignProcessLet’sbuildadigitalchipInthischapter,wewillfollowadesignteamastheyprogressfromconcept,throughcircuittesting,andfinallytotheactualgateplacementandwiringofadigitalchip,usingasuiteofsoftwaretoolsLet’sstartIt’sthecircuitdesigner’smovefirstVerifyingtheCircuitryLogicCircuitdesignerstypicallyuselanguagescalledVHDLorVerilogtodesigntheirenormousdigitalcircuitsVHDLstandsforVHSIC(VeryHighSpeedIntegratedCircuits)HardwareDescriptionLanguage,anIEEEstandardsinceVerilogisanotherproprietarylogicdescriptionlanguageWewilluseVHDLinourexamplesCircuitdesignersusetheVHDLlanguagetocreateachipthatexistsfirstasonlyadatabaseofnumbersThecircuitdesigner’sVHDLfilesareveryClikeThefilesessentiallysay,forexample,“Iwantacircuitfunctionthataddstwobitnumberstogether”Inthisway,theVHDLfilesdescribeourmicroprocessor,ourdigitalfunctions,orwhateverfunctionsweneedTheseVHDLdatafilesarethensubmittedtoacomputersimulator,whichteststhechipcircuitrywhileitisstillinsoftwareformThelogicfunctionsoftheVHDLcoderunveryquickly,muchfasterthanatraditionaltransistorlevelSPICEsimulation(butnotasfastastherealsilicon)TheVHDLsimulatorneedstohaveprocessspecificsoftwaredescriptionsofeachlogicfunctionitwantstouse,suchasrisetime,falltime,gatepropagationdelaysThisinformation,aswellasotherdeviceparameters,isstoredasaseriesoffilesthattheVHDLsimulatorcanaccessAlongwiththeseelectricaldescriptions,therearealsophysicalrepresentationsofeachofthegatesthatthesimulatorandlogicsynthesizercanuseAllofthesefilesarecollectivelyknownasastandardcelllibraryorlogiclibrary|CHAPTERThecomputerlanguage,CDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteBylookingattheresultsoftheseVHDLsimulations,wecanmakeadjustmentstothecircuitrybeforewecommitthechiptoactualsiliconThisisagreatsavingCompilingaNetlistOncethecircuitdesignerhasfinishedverifyinghislogicdesign,hewillputhisVHDLcodethroughasiliconcompilerorlogicsynthesizerThecompilertranslatesthehighlevelClikecodeintoafilethatcontainsalltherequiredlogicfunctions,aswellashowtheyaretobeconnectedtoeachotherThefilebasicallysays,“Inordertoaddtwobitnumberstogether,Ineedgatesandhere’showtheyshouldbeconnected”Inthisway,allourlogicfunctionsarecreatedandcrossreferencedDigitalLayout|VHDLCodeSegmentarchitectureSTRUCTUREofTESTiscomponentandxport(A,B,C,D:instdulogic:=‘’Y:outstdulogic)endcomponentconstantVCC:stdulogic:=‘’signalT,Q:stdulogicvector(downto)beginT()<=VCCA:andxportmap(A=>Q(),B=>Q(),Y=>T())A:andxportmap(A=>Q(),B=>Q(),C=>Q(),D=>Q(),Y=>T())Count<=QThecompanythatissupplyingyoursiliconusuallyprovidesastandardcelllibraryTheoretically,youaregivenalibrary,whichisperfect,andwillstayperfectHowever,updatestothelibrarycanoccurquitefrequentlyChangestothelibrarycancauseaonceperfectchiptostopfunctioning,especiallyifmistakeshavebeenmadeintheupdatesUpdatingalibrarymidprojectisusuallyabadmoveDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteAtthispoint,weknowwhatgatesweneed,andweknowhowtheymustbeeventuallywiredtoeachotherThisfile,calledanetlist,willdriveyourautomatedlayouttools|CHAPTERNetlistSegmentmoduletest(in,in,out)inputin,inoutputoutwirenet,net,netANDXU(Z(net),A(net),B(net))ANDXU(Z(net),A(net),B(net),C(net),D(net))endmoduleAsthecircuitdesignerbeginstocompiletheVHDLcode,hewillcontrolvariousswitchesTheswitchescontrolparameterssuchasarea,power,andspeedDependingonchiprequirements,thecircuitdesignermightdecidetocompiletheVHDLtoprioritizeonlyspeed,onlyarea,onlypower,orsomespecificcombinationoftheseinterestsResultswillvarydependingonthesepriorities,soheinputsthesechoicestothecompilerbeforeitbeginsDriveStrengthThecompilercancreatenetsthatareextremelylargeTheremaybehundredsofthousandsofcellsononeparticularnet,forinstanceThemorecellswehaveonanet,themorepowerweneedtodrivethemIfwetrytodrivetoomanygatesfromasinglesource,wemightoverloadourdrivingtransistorsOurcircuitwillnotworkTherefore,beforewecanstartlayout,weneedtomodifythenetlisttomakesurethattheselargenetsareadequatelydrivenTodothis,wereplacethecellsthataredrivingthenetwithcellsofidenticallogicfunctionthathavelargerdrivingcapabilityDrivingcapabilityisreferredtoasthedrivestrength,orfanout,ofthecellThefanoutnumberindicateshowmanydevicesagatecandriveAdrivinggatecanbeanycellinalibraryForexample,wemightseethatourcelllibraryhasordifferentsizesofinvertersTheseinverterselectionsmightbereferredtoasx,x,orxinvertersThesedesignationsontheinvertersrefertothedrivestrengthofeachinverterSinceaxcantypicallydrivetwogates,axwoulddrivefourgates,andaxwoulddriveeightgatesDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteDigitalLayout|Figure–Oneinverterdrivestwoloads,soaxdrivesloads,andaxdrivesloadsYoumightwonderwhywedon’tjustbuildonehugegatetocoverallcircuiteventualitiesWecoulddothatHowever,wewouldwastecircuitareaandburnmorepowerthanisnecessaryThewisesttechniqueistobesurethatyoucandrivewhatyouneed,andnomoreSo,duringthecompilationprocess,thecompilerexaminesthenumberofgatesoneachnetandadjuststhesizeofthegatedrivingeachnetaccordinglyIfthenetistoolargetobedrivenbyourmaximumdrivestrengthdevice,thecompilerwillbreakthenetintosmallersectionsthatareeasiertodriveBufferCellsIfthecompilerbreaksalargenetintosmaller,moreeasilydrivensections,itwillinsertadditionalgatestodriveeachsmallernewlycreatednetTheseextragateswerenotpartoftheoriginallogicThecircuitdesignerdidnotaddthemYoudidnotaddthemThecomputermadethedecisionbyitselfTheseextragatesarecalledbuffercellsBuffercellshelpdrivegateandwiringcapacitanceAbuffercellhasnologicfunctionassociatedwithitWhateverlogicsignalisfedintothebuffercellappearsatitsoutputInthenextsection,wewillseeanexampleofhowthecompilerusestheseconceptstodrivealargeclocknetClockTreeSynthesisMostdigitalcircuitshaveaclockwaveformthatclicksawayinthebackgroundEveryfunctionissynchronizedtothatclickThewiringnetsforthisclocktimingsignalarecalledclocknetsAclocknetisusuallyverylargeTypically,thenetconnectstothousandsofgatesItisimpossibletocreateacellwithenoughdrivestrengthtodriveallthegatesonaclocknet,sowehavetodosomeextraworktogettheclocknettofunctionWesplittheclocknetintosmallersectionsandaddbuffercells,asmentionedpreviouslyThenetissplitintoabranchingoutpattern,calledaclocktreeEstablishingthetreeiscalledclocktreesynthesisDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteToillustratehowthetreeconceptworks,let’slookatasmallexampleLet’ssayacertainclocknethassixgatesonit,andthemaximumdrivestrengthourlibraryoffersisafanoutofonlythreeTherefore,wecannotexpectonegatetodrivetheentireclocknetSo,webreakthenetintotwosmallersections,anddriveeachsectionseparately|CHAPTERFigure–AddingbufferstosmallersetsofgatestohelpdrivethesignalYoucanseeinFigure–,thatthecompileraddedtwolowerlevelbufferstothecircuit,onebuffertodriveeachsetofthreegatesThecompileralsoaddedanotherhigherlevelbuffertodrivethetwolowerlevelbuffersSo,threeextracellshavebeenaddedtoourcircuitIfourclocknetwasevenlarger,thecompilerwouldcontinuebranchinginthismanner,splittingthenetandaddingadditionalbuffercells,eachonedrivingnomorethanthreeothersYoucanseehowthiswouldformaverylargetreewithmanylevelsFigure–LargenetsarebrokenintomanysmallersectionsthatcanmoreeasilybedrivenDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteWithalargenumberofaddedbuffercells,theextracellswillintroduceextradelaysthatwerenotaccountedforintheoriginalsimulationsNotonlythat,butotherlargenetsmayrequirethissamesortoftreesynthesisaswell,addingevenmorebuffercells,alsocreatingdelaysTherefore,oncetheclocknetissynthesized,andanyotherlargefanoutnetsarebuffered,weneedtoresimulateourdesignusingthecompilednetlistCompilingcreatesaneedtoresimulateThissortofiterationiscommoninchipdevelopmentThegoodnewsisthatitisnotaneverendingstoryAtsomepoint,youwillhaveafinishednetlistWearenowreadytostartthelayoutprocessWebeginwithfloorplanningLayoutProcessWearenowreadytouseasuite,orpackage,ofautomatedsoftwaretoolscalledtheplaceandroutetoolsPlaceandroutetoolscoverthegamutofhigherlevelandlowerlevelsoftwareassistanceleadingtoyourfinallayoutAsthenameimplies,theseprogramsgenerallyplacethegatesandroutethewires,inadditiontootherhelpfulfunctionsFloorplanningThefirstpieceofsoftwarewewillusefromtheplaceandroutetoolsuiteiscalledthefloorplanningtoolItwillhelpyoucreateareasoffunctionalityonyourchip,determinetheconnectivitybetweentheseareas,determineyourIOpadplacements,andgiveyoufeedbackonhoweasyyourfloorplanmightbetowireThefloorplanningtoolgetsitsconnectivityandgateinformationbasedonthenetlistfile,createdbythecompilersoftwareLet’sfollowthefloorplanningtoolinmoredetail,beginningwithyourinitialdecisionsBlockPlacementTypically,yourchipwillbedividedintovariousfunctionalareasForexample,ifyouareworkingonalargedigitalchip,theremightbeamicroprocessorunitinyourchip(MPU),perhapsafloatingpointunit(FPU),maybeaRAMblockandaROMblockWhereyoulocateeachareaoffunctionalityisyourdecision,notthecomputer’sYoumightsay,“Ok,allofthegatesforthemicroprocessorIwantinthebottomlefthandcornerAllthegatesfortheRAMIwantinthetoprightcorner”AndsoonYouwillhaveachancetochangethesedecisionslater,onceyouseehowyourdecisionsmightaffectyourlayout,particularlythewiringDigitalLayout|DigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteGateGroupingOnceyourareasoffunctionalityarespecified,thefirsttaskyouwouldwanttodoisgathertogether,tosomedegree,thegatesusedineachblockYouwouldnotwantFPUgatesscatteredthroughouttheROMorRAMblocks,forexampleAssociatedgatesshouldallbelocatedneareachotherThefloorplanningtoolbeginsbyhelpingyougatheryourgatestogetherTheexactplacementofeachgateisnotdeterminedatthispointWedonotyetneedthislevelofdetailBesides,wemightbechangingourblockplacementdecisionsatsomelaterpointSogeneralvicinityplacementisgoodenoughfornowBlockLevelConnectivityNext,yourfloorplanningtoolwillhelpyouplacetheinputandoutput(IO)cellsofyourchipForinstance,youwouldwantalltheinputsthatgototheFPUclosetotheFPUblockinthecornerTohelpyouwiththis,sometoolswillactuallyplacetheIOcellsintheappropriateareasautomaticallyothertoolswillprovidegraphicfeedbackforyoubasedonyourplacementdecisions|CHAPTERFigure–InputsandoutputscanbelocatedneartheirappropriatecellblockThefloorplanningtoolalsoshowsbasicwiringconnectionsthatmusttravelbetweenblocksItwillshowconnectionsbetweentheFPUandtheRAMblocks,forexampleFigure–ChipshavewelldefinedareasoffunctionalityDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteUsingFlylinesTypically,thefloorplanningtoolwillshowyouallthewiringlinescomingfromeachblockconnectingtotheIOpadsandtootherblocksAllthesemyriadofwiringlinesarewhatmosttoolscallrat’snestsorflylinesAsyouclick,drag,andresizeblocksaroundyourcomputermonitor,youwillseeallthesewiringconnectionsmovingaroundinrealtimewithyourcursorAsyoudragyourblocksaroundwithyourcursor,watchthelinesIfthelinesbecomebadlycrossedoverandgenerallymessy,youknowthatitwillbetoughtowirethecircuitryIftherearenocrossoversoftheflylines,thenitwillbeeasytowireDigitalLayout|Theautomatedsoftwareprogramssuchasthesimulatorandplaceandroutetoolsmakechoicesaconscientioushumanwithenoughtimewouldmake,giventhesameinformation(Wehope)However,youcanseethatconstanthumaninterventionandmonitoringareessentialThesoftwareneveroperateswithouthumansupervision(you)YouhavebroadlydefinedwhereyouwantyourhighlevelsoffunctionalityandyourinputsandyouroutputsYouhavepredeterminedsomebasiclayoutinstructionsforthesoftware,dependingonthechipspecifications,thesizeofthefinalpackageinwhichtheywillbeplaced,thespecificcircuitry,andultimately,onyourunderstandingofhowthesoftwareoperatesThetoolsneverruncompletelybythemselvesThehumanbrainmustoverseetheworkingofthetoolsorthetoolsbecomeuselessFigure–NeatflylinesindicategoodfloorplanningJustasspellcheckerskneadahumanayeDigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteYouwillmakechangestoyourblockfloorplansothatyourrat’snesteventuallylooksasclean,nice,andwireableaspossibleYoumightdecidetorelocateentireareasoffunctionalityYoumightbringonesmallblockacrosstotheothersideandfititbetweentwolargerblocksYoumightbringacenterblocktotheoutside,oranoutsideblocktothecenterWhenyoufinallyhaveablockdiagramwhichgivesyounice,simplewiring,yousaveyourfloorplanningoutputfilesTimingChecksSincethefinalfloorplanningtooloutputfilesspecifywherethegateswillbegenerallylocated,theplacementtoolroughlyknowshowlongallthewireswillbeThesewiringlengthestimationsarebasedonthephysicaldimensionsofthedigitallibraryUsingthisinformation,yourfloorplanningtoolcanoutputanestimatedwirelengthfilethatgoesbackintothedigitalcircuitsimulatorYounowcanrunsomesimulationstodeterminehowyourestimatedwiringlengthswillaffectyourdigitalcircuitYoumustcheckthepossibilitythatlongwireswillslowthecircuitsignalstoomuch,affectingthecircuittiming|CHAPTERFigure–ThefloorplantimingloopAsChrisalwayssays,“Idon’tcareifitworks,aslongasitlooksgood”DigitalLayoutDownloadedfromDigitalEngineeringLibraryMcGrawHill(wwwdigitalengineeringlibrarycom)CopyrightTheMcGrawHillCompaniesAllrightsreservedAnyuseissubjecttotheTermsofUseasgivenatthewebsiteIfthewirelengthsareindeedoverlyaffectingthecircuittiming,thedesignerwillneedtomodifyhisdesign,basedonyourfloorplanHewillchangethenetlistHemightplacehigherpoweredcellsintheblocktodrivetheextrawiringcapacitances,forexampleAsthedesignerworkstobetterorganizethedesign,notonlyisiteasiertowire,butyouwillfindthechipoperatesbetterintheendYougoaroundthisfloorplanandtimingcheckloopacoupleoftimesThesimulatorwilleventuallyletyouknowwhenyouhavemetthetimingcriteriaSo,atsomepoint,youdecideyoufinallyhaveagooddesignYouthenmoveontocementingyourdevicesinplace,sotospeakThefinetuningnowbeginsthatwehavebeenputtingoffPlacementWecannownaildowntheexactpositionsofallthelogicgateswithineachblock,usingaplacementtoolInthenextsection,wewill

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