74HC112

DATA SHEET Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jun 10 INTEGRATED CIRCUITS 74HC/HCT112 Dual JK flip-flop with set and reset; negative-edge trigger For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 查询74HC112供应商 1998 Jun 10 2 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual nJ, nK, clock (nCP), set (nSD) and reset (nRD) inputs. The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs. A HIGH level at the clock (nCP) input enables the nJ and nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state changes are initiated by the HIGH-to-LOW transition of nCP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V nCP to nQ, nQ 17 19 ns nSD to nQ, nQ 15 15 ns nRD to nQ, nQ 18 19 ns fmax maximum clock frequency 66 70 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop notes 1 and 2 27 30 pF 1998 Jun 10 3 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 ORDERING INFORMATION PIN DESCRIPTION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION 74HC112D; 74HCT112D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC112DB; 74HCT112DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC112N; 74HCT112N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC112PW; 74HCT112PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PIN NO. SYMBOL NAME AND FUNCTION 1, 13 1CP, 2CP clock input (HIGH-to-LOW, edge triggered) 2, 12 1K, 2K data inputs; flip-flops 1 and 2 3, 11 1J, 2J data inputs; flip-flops 1 and 2 4, 10 1SD, 2SD set inputs (active LOW) 5, 9 1Q, 2Q true flip-flop outputs 6, 7 1Q, 2Q complement flip-flop outputs 8 GND ground (0 V) 15, 14 1RD, 2RD reset inputs (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. 1998 Jun 10 4 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 Fig.4 Functional diagram. FUNCTION TABLE Note 1. If nSD and nRD simultaneously go from LOW to HIGH, the output states will be unpredictable. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition X = don’t care ↓ = HIGH-to-LOW CP transition OPERATING MODE INPUTS OUTPUTS nSD nRD nCP nJ nK nQ nQ asynchronous set L H X X X H L asynchronous reset H L X X X L H undetermined L L X X X H L toggle H H ↓ h h q q load “0” (reset) H H ↓ l h L H load “1” (set) H H ↓ h l H L hold “no change” H H ↓ l l q q Fig.5 Logic diagram (one flip-flop). 1998 Jun 10 5 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops 1998 Jun 10 6 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HC UNIT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nCP to nQ 55 175 220 265 ns 2.0 Fig.620 35 44 53 4.5 16 30 37 45 6.0 tPHL/ tPLH propagation delay nCP to nQ 55 175 220 265 ns 2.0 Fig.620 35 44 53 4.5 16 30 37 45 6.0 tPHL/ tPLH propagation delay nRD to nQ, nQ 58 180 225 270 ns 2.0 Fig.721 36 45 54 4.5 17 31 38 46 6.0 tPHL/ tPLH propagation delay nSD to nQ, nQ 50 155 295 235 ns 2.0 Fig.718 31 39 47 4.5 14 26 33 40 6.0 tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.67 15 19 22 4.5 6 13 16 19 6.0 tW clock pulse width HIGH or LOW 80 22 100 120 ns 2.0 Fig.616 8 20 24 4.5 14 6 17 20 6.0 tW set or reset pulse width LOW 80 22 100 120 ns 2.0 Fig.716 8 20 24 4.5 14 6 17 20 6.0 trem removal time nRD to nCP 80 22 125 150 ns 2.0 Fig.716 8 25 30 4.5 14 6 21 26 6.0 trem removal time nSD to nCP 80 −19 100 120 ns 2.0 Fig.716 −7 20 24 4.5 14 −6 17 20 6.0 tsu set-up time nJ, nK to nCP 80 19 100 120 ns 2.0 Fig.616 7 20 24 4.5 14 6 17 20 6.0 th hold time nJ, nK to nCP 0 −11 0 0 ns 2.0 Fig.60 −4 0 0 4.5 0 −3 0 0 6.0 fmax maximum clock pulse frequency 6 20 4.8 4.0 MHz 2.0 Fig.630 60 24 20 4.5 35 71 28 24 6.0 1998 Jun 10 7 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT 1SD, 2SD 0.5 1K, 2K 0.6 1RD, 2RD 0.65 1J, 2J 1 1CP, 2CP 1 1998 Jun 10 8 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HCT UNIT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nCP to nQ 21 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nCP to nQ 23 40 50 60 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nRD to nQ, nQ 22 37 46 56 ns 4.5 Fig.7 tPHL/ tPLH propagation delay nSD to nQ, nQ 18 32 40 48 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 8 20 24 ns 4.5 Fig.6 tW set or reset pulse width LOW 18 10 23 27 ns 4.5 Fig.7 trem removal time nRD to nCP 20 11 25 30 ns 4.5 Fig.7 trem removal time nSD to nCP 20 −8 25 30 ns 4.5 Fig.7 tsu set-up time nJ, nK to nCP 16 7 20 24 ns 4.5 Fig.6 th hold time nJ, nK to nCP 0 −7 0 0 ns 4.5 Fig.6 fmax maximum clock pulse frequency 30 64 24 20 MHz 4.5 Fig.6 1998 Jun 10 9 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC WAVEFORMS Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ, nK to nCP set-up times, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. handbook, full pagewidth MBK218 VM(1) nCP INPUT nSD INPUT nRD INPUT nQ OUTPUT nQ OUTPUT VM(1) VM(1) VM(1) VM(1) tW trem trem tW tPHLtPLH tPLHtPHL Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse width and the nRD and nSD to nCP removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. 1998 Jun 10 10 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 PACKAGE OUTLINES X w M θ AA1 A2 bp D HE Lp Q detail X E Z e c L v M A (A )3 A 8 9 1 16 y pin 1 index UNIT Amax. A1 A2 A3 bp c D (1) E(1) (1)e HE L Lp Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 1.75 0.250.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 SOT109-1 95-01-2397-05-22 076E07S MS-012AC 0.069 0.0100.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.0410.2440.228 0.028 0.020 0.028 0.0120.01 0.25 0.01 0.0040.0390.016 0 2.5 5 mm scale SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1998 Jun 10 11 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 UNIT A1 A2 A3 bp c D(1) E (1) e HE L Lp Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.210.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 8 0 o o0.130.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT338-1 94-01-1495-02-04 (1) w M bp D HE E Z e c v M A X A y 1 8 16 9 θ AA1 A2 Lp Q detail X L (A )3 MO-150AC pin 1 index 0 2.5 5 mm scale SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 A max. 2.0 1998 Jun 10 12 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 UNIT Amax. 1 2 b1 c E e MHL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT38-1 92-10-0295-01-19 A min. A max. b max.wMEe1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.2542.54 7.62 0.30 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.0210.015 0.013 0.009 0.010.100.0200.19 050G09 MO-001AE MH c (e )1 ME A L se a tin g pl an e A1 w M b1 e D A2 Z 16 1 9 8 b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1)D (1)Z DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 1998 Jun 10 13 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 UNIT A1 A2 A3 bp c D (1) E (2) (1)e HE L Lp Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.150.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o0.13 0.10.21.0 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 94-07-1295-04-04 w M bp D Z e 0.25 1 8 16 9 θ AA1 A2 Lp Q detail X L (A )3 HE E c v M A X A y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.10 pin 1 index 1998 Jun 10 14 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: • Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). • Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in 1998 Jun 10 15 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 one operation within 2 to 5 seconds between 270 and 320 °C. DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification.