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首页 VHDL 语言

VHDL 语言.pdf

VHDL 语言

几何老师
2011-06-11 0人阅读 举报 0 0 暂无简介

简介:本文档为《VHDL 语言pdf》,可适用于IT/计算机领域

VHDLTraining©CypressSemiconductor,VersionJK(June)PROGRAMMABLELOGICDESIGNWITHVHDLEricDeng(haitao)FieldApplicationsEngineerCypressSemiconductoredxcypresscomVHDLTraining©CypressSemiconductor,VersionJK(June)ObjectivesYouwilllearnenoughaboutVHDLto:DesignefficientcombinatorialandsequentiallogicDesignstatemachinesandunderstandimplementationtradeoffsDesignusingmultilevelhierarchyIdentifyhowVHDLwillsynthesizeandfitintoaPLDorCPLDVHDLTraining©CypressSemiconductor,VersionJK(June)Objectives(contd)YouwilllearnenoughabouttheWarpsoftwareto:CompileandsynthesizeVHDLdesignsforprogrammablelogicdevicesTargetPLDsCPLDs•SimulatetheresultingdevicefunctionalityinNova•Usethereportfiletodetermineoperatingfrequency,setuptime,clocktooutputdelay,anddeviceresourceusageVHDLTraining©CypressSemiconductor,VersionJK(June)AgendaVHDLDesignDescriptionsTheEntity,Ports,Modes,TypesExercise#TheArchitecture,ArchitectureStylesVHDLStatements,CombinatorialLogicProcesses,SignalsVsVariablesVHDLOperatorsOverloadingInferencingVHDLIdentifiersExercise#MORNINGBREAKUsingWarpExercise#RegisteredLogicImplicitMemoryLUNCHExercise#StateMachinesandStateEncodingExercise#AFTERNOONBREAKHierarchicalDesignsExercise#MiscellaneousTopicsSummaryandConclusionVHDLTraining©CypressSemiconductor,VersionJK(June)WhatisVHDLVHSIC(VeryHighSpeedIntegratedCircuit)HardwareDescriptionLanguageVHDLisaDesignDescriptionLanguageVHDLisaDesignDocumentationLanguageVHDLisaSimulationLanguageItisanIEEEStandardLanguage(IEEE)VHDLTraining©CypressSemiconductor,VersionJK(June)WhyUseVHDLVeryFastTimetoMarketAllowsdesignerstoquicklydevelopdesignsrequiringtensofthousandsoflogicgatesormoreProvidespowerfulhighlevelconstructsfordescribingcomplexlogicSupportsmodulardesignmethodologyandmultiplelevelsofhierarchyOnelanguagefordesignandsimulationAllowscreationofdeviceindependentdesignsthatareportabletomultiplePLDvendorsAllowsusertopickanysynthesistool,vendor,ordeviceVHDLTraining©CypressSemiconductor,VersionJK(June)VHDLDesignDescriptionsVHDLdesigndescriptionsconsistofanENTITYdeclarationandanARCHITECTUREbodyTheENTITYdeclarationdescribesthedesignIOTheARCHITECTUREbodydescribesthecontentorfunctionofthedesignEveryarchitectureneedsanentitysoitiscommontorefertothemtogetherasanENTITYARCHITECTUREPAIRVHDLTraining©CypressSemiconductor,VersionJK(June)TheEntityA“BLACKBOX”TheENTITYdescribestheIOoftheblackboxBLACKBOXrstd:clkq:coVHDLTraining©CypressSemiconductor,VersionJK(June)ExampleEntitydeclarationENTITYblackboxISPORT(clk,rst:INstdlogicd:INstdlogicvector(DOWNTO)q:OUTstdlogicvector(DOWNTO)co:OUTstdlogic)ENDblackboxWhatdoesitallmeanBLACKBOXrstd:clkq:coVHDLTraining©CypressSemiconductor,VersionJK(June)PortsTheEntity(“BLACKBOX”)hasPORTSPORTSarethepointsofcommunication•PORTSareusuallythedevicepinsPORTShaveanassociatedname,mode,andtypeVHDLTraining©CypressSemiconductor,VersionJK(June)PortModesAport‟sMODEindicatesthedirectionthatdataistransferred:INDatagoesintotheentityonlyOUTDatagoesoutoftheentityonly(andisnotusedinternally)INOUTDataisbidirectional(goesintoandoutoftheentity)BUFFERDatathatgoesoutoftheentityandisalsofedbackinternallyEntityVHDLTraining©CypressSemiconductor,VersionJK(June)IEEETypesEveryportontheentityhasaTypeThetypeisalwayscheckedduringanassignmentorcomparisonBITaportoftypebitthatcanonlytakevaluesof''or''BITVECTORagroupingofbits(eachcanbe''or'')ENTITYtypeexampleISPORT(a:INBITb:OUTBITVECTOR(TO)ascendingrangec:OUTBITVECTOR(DOWNTO)descendingrangeENDtypeexampleb<=""Note:<=isanassignmentc<=""doublequotes(“”)usedforvectorsThismeansthat:b()=''c()=''b()=''c()=''b()=''c()=''b()=''c()=''VHDLTraining©CypressSemiconductor,VersionJK(June)INTEGER•usefulasindexholdersforloops,constants,arithmeticfunctions,orsimulationmodelingBOOLEAN•cantakevalues„TRUE‟or„FALSE‟ENUMERATED•hasuserdefinedsetofpossiblevalueseg:TYPEtrafficlightIS(red,yellow,green)IEEETypes(contd)VHDLTraining©CypressSemiconductor,VersionJK(June)IEEEApackagecreatedtosolvethelimitationsoftheBITtypeNinevaluesinsteadofjusttwo(''and'')AllowsincreasedflexibilityinVHDLcoding,synthesis,andsimulationSTDLOGICandSTDLOGICVECTORareusedinsteadofBITandBITVECTORwhenamultivaluedlogicsystemisrequiredSTDLOGICandSTDLOGICVECTORmustbeusedwhentristatelogic(Z)isrequiredTobeabletousethisnewtype,youneedtoaddlinestoyourcode:LIBRARYieeeUSEieeestdlogicALLVHDLTraining©CypressSemiconductor,VersionJK(June)IEEETypesSTDLOGICandSTDLOGICVECTORarenowtheindustrystandardlogictypefordigitaldesignAllvaluesarevalidinaVHDLsimulator,howeveronly:„‟Hard„‟„‟Hard„‟„Z‟HighImpedance„L‟Weak„‟(likeresistorpulldown)„H‟Weak„‟(likeresistorpullup)„‟Don‟tcarearerecognizedforlogicsynthesisVHDLTraining©CypressSemiconductor,VersionJK(June)EntityDeclarationExampleLIBRARYieeeUSEieeestdlogicALLENTITYblackboxISPORT(clk,rst:INstdlogicd:INstdlogicvector(DOWNTO)q:OUTstdlogicvector(DOWNTO)co:OUTstdlogic)ENDblackboxBLACKBOXrstd:clkq:coMODETYPEVHDLTraining©CypressSemiconductor,VersionJK(June)Exercise#:TheEntityWriteanentitydeclarationforthefollowing:PortDisabitbus,inputonlyPortOEandCLKareeachinputbitsPortADisabitbidirectionalbusPortAisabitbus,outputonlyPortINTisanoutputPortASisanoutputalsousedinternallymydesignd:oeclkad:a:intasVHDLTraining©CypressSemiconductor,VersionJK(June)Exercise#:SolutionLIBRARYieeeUSEieeestdlogicALLENTITYmydesignISPORT(d:INstdlogicvector(DOWNTO)oe,clk:INstdlogicad:INOUTstdlogicvector(DOWNTO)a:OUTstdlogicvector(DOWNTO)int:OUTstdlogicas:BUFFERstdlogic)ENDmydesignInthispresentation,VHDLkeywordsarehighlightedinbold,CAPITALSHowever,VHDLisnotcasesensitive:clock,Clock,CLOCKallrefertothesamesignalmydesignd:oeclkad:a:intasVHDLTraining©CypressSemiconductor,VersionJK(June)TheArchitectureArchitecturesdescribewhatisintheblackbox(iethefunctionorbehaviorofentities)DescriptionscanbeeitheracombinationofStructuraldescriptions•Instantiationsofbuildingblocks(placementofcomponentsjustlikeaschematicandtheirconnections)Behavioraldescriptions•Algorithmic(or“highlevel”)descriptions:IFa=bTHENstate<=state•Booleanequations:x<=(aORb)ANDcVHDLTraining©CypressSemiconductor,VersionJK(June)BehavioralArchitectureExampleENTITYblackboxISPORT(a,b:INstdlogicvector(DOWNTO)y:OUTstdlogicvector(DOWNTO))ENDblackboxARCHITECTUREexampleOFblackboxISBEGINy<=aANDbENDexamplexInputANDgate:Thisexampleshowshowtodrivethedevicepins(theentityports)Howdowehandleinternalsignals(ornets)thatdonotconnectdirectlytothedevicepinsVHDLTraining©CypressSemiconductor,VersionJK(June)SignalsTypicallyusedtorepresentwires(ornets)EntityPortsareaspecialtypeofsignalLikeports,theyhaveanameandtype(however,thereisnomode)SignalsaredeclaredinsidethearchitecturebeforetheBEGINForExample,tocreateaninternalbitbus:ARCHITECTUREsignalexampleOFblackboxISSIGNALcount:stdlogicvector(DOWNTO)BEGIN<ManyVHDLStatements>ENDsignalexampleLet‟slearnsomebasicVHDLstatements…VHDLTraining©CypressSemiconductor,VersionJK(June)CombinatorialLogicTherearemanywaystodescribecombinatorialcircuitsInthenextfewslides,wewilltakealookatsomeexamplesofhowtodescribecombinatoriallogicYoushouldreferbacktotheseslidesforsomeideaswhenyoustartwritingyourfirstdesignsVHDLTraining©CypressSemiconductor,VersionJK(June)VHDLStatementExamples()BooleanEquationsAllstandardBooleanoperatorsaresupportedinVHDLAND,OR,NOT,XOR,XNOR,NANDForexample,amultiplexerisshownbelowx<=(aANDNOT(s())ANDNOT(s()))OR(bANDNOT(s())ANDs())OR(cANDs()ANDNOT(s()))OR(dANDs()ANDs())axmuxcbdsVHDLTraining©CypressSemiconductor,VersionJK(June)AssignmentbasedonaselectionsignalWHENclausesmustbemutuallyexclusive(alldifferent)Alwaysuse“WHENOTHERS”tocoverunspecifiedcasesOnlyonereferencetothesignal,onlyoneassignmentoperator(<=)WITHselectionsignalSELECTsignalname<=valueWHENvalueofselectionsignal,valueWHENvalueofselectionsignal,valuenWHENvaluenofselectionsignal,valuexWHENOTHERSVHDLStatementExamples()WITHSELECTWHENVHDLTraining©CypressSemiconductor,VersionJK(June)Thesamemultiplexerwesawearliercouldalsobedescribedasfollows:WITHsSELECTx<=aWHEN“”,meanswhens=“”bWHEN“”,cWHEN“”,dWHENOTHERSVHDLStatementExamples()WITHSELECTWHENaxmuxcbdsVHDLTraining©CypressSemiconductor,VersionJK(June)Therecanbemultipleconditionsoneachline:WITHsSELECTx<=aWHEN””|“”|“”,bWHEN""|"",„|‟means“or”inthiscasecWHENOTHERSVHDLStatementExamples()WITHSELECTWHENVHDLTraining©CypressSemiconductor,VersionJK(June)SignalisassignedavaluebasedonconditionsAnysimpleexpressioncanbeaconditionPrioritygoesinorderofappearanceOnlyonereferencetothesignal,onlyoneassignmentoperator(<=)AlwaysendwithELSEtocoverunspecifiedconditionssignalname<=valueWHENconditionELSEvalueWHENconditionELSEvaluenWHENconditionnELSEvaluexVHDLStatementExamples()WHENELSEVHDLTraining©CypressSemiconductor,VersionJK(June)Thesameexamplemultiplexercouldalsobedescribedasfollows:x<=awhen(s=“”)elsebwhen(s=“”)elsecwhen(s=“”)elsedVHDLStatementExamples()WHENELSEaxmuxcbdsVHDLTraining©CypressSemiconductor,VersionJK(June)WhatisthedifferencebetweenWITHSELECTWHENandWHENELSEWITHSELECTWHENallowsonlyonecontrolsignalWHENELSEsupportsmanydifferentcontrolsignalsExample:Apriorityencoderj<=wwhen(a=„‟)elsexwhen(b=„‟)elseywhen(c=„‟)elsezwhen(d=„‟)else„‟VHDLStatementExamples()WHENELSEVHDLTraining©CypressSemiconductor,VersionJK(June)VHDLStatementsTherearetwotypesofstatements,ConcurrentandSequentialConcurrentStatements(meansinparallel)Concurrentstatementsare“executed”concurrently(atthesametime)Theexampleswehaveseensofarareallconcurrentstatements:–BooleanEquations–WHENELSE–WITHSELECTWHENTheorderofconcurrentstatementsisnotimportantVHDLTraining©CypressSemiconductor,VersionJK(June)TheorderofconcurrentstatementsForexample,supposewehadthefollowinglinesofcode:x<=aORbORcy<=xWHEN(e=„‟)ELSE„‟Thiswillproduceexactlythesameresultas:y<=xWHEN(e=„‟)ELSE„‟x<=aORbORcTheorderthatyouwritethestatementsmakesnodifference,becausetheyareconcurrent(workinginparallel)VHDLTraining©CypressSemiconductor,VersionJK(June)SequentialStatements(meansinseries)SometimesweneedtomodelcomplexfunctionsInthatcase,wecanusean“algorithm”oramodeltodescribethefunctionThisisdonewithSequentialStatementsWithSequentialstatements,theORDERofthestatementsisimportant(examplelater)Therefore,weuseaprocesstomarkthebeginningandendofablockofsequentialstatementsEachcompletedprocessisconsideredtobeonebigconcurrentstatement(therecanbemanyprocessesinsideonearchitecture)VHDLStatements(cont)VHDLTraining©CypressSemiconductor,VersionJK(June)WhatisaVHDL“Process”Processesareeitherawakeorasleep(activeorinactive)AprocessnormallyhasasensitivitylistWhenasignalinthatsensitivitylistchangesvalue,theprocesswakesupandallofthesequentialstatementsare“executed”Forexample,aprocesswithaclocksignalinitssensitivitylistwillbecomeactiveonchangesoftheclocksignalAttheendoftheprocess,alltheoutputsareupdatedandtheprocessgoesbacktosleepuntilthenexttimeasignalchangesinthesensitivitylistVHDLTraining©CypressSemiconductor,VersionJK(June)TheProcess:AnExamplemux:PROCESS(a,b,s)BEGINIFs=''THENx<=aELSEx<=bENDIFENDPROCESSmuxTheprocessmuxissensitivetosignalsa,b,andsThatmeansthatwheneveranyofthosesignalschangesvalue,theprocesswakesup,thesequentialstatementsareexecutedandtheoutputxisupdatedNote:Thelogiccouldberegistered(synchronous)orcombinatorialNote:Theorderofthesignalsinthesensitivitylistisnotimportantx(DOWNTO)sa(DOWNTO)b(DOWNTO)VHDLTraining©CypressSemiconductor,VersionJK(June)CombinatorialLogicusingSequentialStatementsWehavealreadylookedatsomeexamplesofcombinatoriallogicusingConcurrentStatementsLet‟stakealookathowtocreatecombinatoriallogicwithsequentialstatementsVHDLTraining©CypressSemiconductor,VersionJK(June)SequentialStatementExamples()IFTHENELSEForexample,atomulitplexercouldbedescribedasfollows:mux:PROCESS(a,b,c,d,s)BEGINIFs=“”THENx<=aELSIFs=“”THENx<=bELSIFs=“”THENx<=cELSEx<=dENDIFENDPROCESSmuxAnytimeyouwanttouseIFTHENELSE,thenyouMUSTuseaprocess,becauseitisasequentialstatementVHDLTraining©CypressSemiconductor,VersionJK(June)Howcantheorderofsequentialstatementsmakeadifferenceex:PROCESS(a,b)BEGINIFa=„‟THENc<=„‟ifaandbareENDIFboth„‟thenIFb=„‟THENc<=„‟bhaspriorityENDIFsoc<=„‟ENDPROCESSexex:PROCESS(a,b)BEGINIFb=„‟THENc<=„‟ifaandbareENDIFboth„‟thenIFa=„‟THENc<=„‟ahaspriorityENDIFsoc<=„‟ENDPROCESSexVHDLTraining©CypressSemiconductor,VersionJK(June)Anotherwaytodescribethesametomux:mux:PROCESS(a,b,c,d,s)BEGINCASEsISWHEN""=>x<=aWHEN""=>x<=bWHEN"”=>x<=cWHENOTHERS=>x<=dENDCASEENDPROCESSmuxAnytimeyouwanttouseCASEWHEN,thenyouMUSTuseaprocess,becauseitisasequentialstatementSequentialStatementExamples()CASEWHENVHDLTraining©CypressSemiconductor,VersionJK(June)ANoteaboutProcessesSignalAssignmentTakealookatthefollowingpieceofcodeWhichcircuitdoyouthinkwillbesynthesizedPROCESS(clock)BEGINIFrisingedge(clock)THENb<=aaftertherisingclockedge,agoestobc<=baftertherisingclockedge,bgoestocENDIFENDPROCESSaclockcbacclockORVHDLTraining©CypressSemiconductor,VersionJK(June)SignalAssignmentinProcessesInsideprocesses,signalsarenotupdatedimmediatelyInstead,theyarescheduledtobeupdatedThesignalsarenotactuallyupdateduntiltheENDPROCESSstatementisreachedTherefore,onthepreviousslide,tworegisterswillbesynthesized(c<=bwillbetheoldb)Insomecases,theuseofaconcurrentstatementoutsidetheprocesswillfixtheproblem,butthisisnotalwayspossibleSohowelsecanwefixthisproblemVHDLTraining©CypressSemiconductor,VersionJK(June)VariablesWhenaconcurrentsignalassignmentoutsidetheprocesscannotbeused,thepreviousproblemcanbeavoidedusingavariableVariablesarelikesignals,BUTtheycanonlybeusedinsideaPROCESSTheycannotbeusedtocommunicateinformationbetweenprocessesVariablescanbeofanyvalidVHDLdatatypeThevalueassignedtoavariableisavailableimmediatelyAssignmentofvariablesisdoneusingacolon(:),likethis:c:=aANDbVHDLTraining©CypressSemiconductor,VersionJK(June)cUsingVariablesvsSignalsSolutionusingavariablewithinaprocess:PROCESS(clock)VARIABLEb:stdlogicBEGINIFrisingedge(clock)THENb:=athisisimmediatec<=bthisisscheduledENDIFENDPROCESSaclockVHDLTraining©CypressSemiconductor,VersionJK(June)NativeOperators(IEEE)LogicaldefinedfortypeBIT,BITVECTOR,BOOLEANAND,NANDOR,NORXOR,XNORNOTRelationaldefinedfortypesBIT,BITVECTOR,INTEGER=(equalto)=(notequalto)<(lessthan)<=(lessthanorequalto)>(greaterthan)>=(greaterthanorequalto)VHDLTraining©CypressSemiconductor,VersionJK(June)NativeOperators(continued)ArithmeticdefinedfortypeINTEGER(addition),*(multiplication)(subtraction)ConcatenationdefinedforSTRINGASTRINGisanysequenceofcharactersstdlogicvectorisanexampleofaSTRINGNote:NoneoftheseoperatorsweredefinedtosupportstdlogicorstdlogicvectortypesbecauseinIEEE,stdlogicdidnotexistyetHowcanwefixthisproblemVHDLTraining©CypressSemiconductor,VersionJK(June)OverloadedOperatorsInVHDL,anynativeoperatorcanbeoverloaded(meansredefined)toacceptanyotherVHDLtypeThisisveryusefulForexample:SIGNALcounter:stdlogicvector(DOWNTO)counter<=counterthenative''operatorsupportsintegersonly,butwecanoverloadittoacceptstdlogicvectorsalsoThestdarithpackagefromCypressdefi

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