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mc1496  Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 9 1 Publication Order Number: MC1496/D MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (si...

mc1496
 Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 9 1 Publication Order Number: MC1496/D MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications. See ON Semiconductor Application Note AN531 for additional design information. Features • Excellent Carrier Suppression −65 dB typ @ 0.5 MHz −50 dB typ @ 10 MHz • Adjustable Gain and Signal Handling • Balanced Inputs and Outputs • High Common Mode Rejection −85 dB Typical • This Device Contains 8 Active Transistors • Pb−Free Package is Available* http://onsemi.com SOIC−14 D SUFFIX CASE 751A 14 1 14 1 PDIP−14 P SUFFIX CASE 646 PIN CONNECTIONS Signal Input 1 2 3 4 5 6 7 10 11 14 13 12 9 N/C Output Bias Signal Input Gain Adjust Gain Adjust Input Carrier8 VEE N/C Output N/C Carrier Input N/C See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ORDERING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. DEVICE MARKING INFORMATION *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Administrator 高亮 这些设备被设计为使用其输出电压是输入电压(信号)和开关功能(运营商)的产品。典型应用包括抑制载波和幅度调制,同步检测,调频检测,相位检测,斩波器的应用程序。见安森美半导体应用笔记AN531额外的设计信息 Administrator 高亮 载波输入 Administrator 高亮 输入载波 Administrator 高亮 增益调节 Administrator 高亮 偏置 Administrator 高亮 信号输入 MC1496, MC1496B http://onsemi.com 2 IC = 500 kHz, IS = 1.0 kHz IC = 500 kHz IS = 1.0 kHz 60 40 20 0 Lo g S ca le Id 499 kHz 500 kHz 501 kHz IC = 500 kHz IS = 1.0 kHz IC = 500 kHz IS = 1.0 kHz 499 kHz 500 kHz 501 kHz Li ne ar S ca le 10 8.0 6.0 4.0 2.0 0 Figure 1. Suppressed Carrier Output Waveform Figure 2. Suppressed Carrier Spectrum Figure 3. Amplitude Modulation Output Waveform Figure 4. Amplitude−Modulation Spectrum MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating Symbol Value Unit Applied Voltage (V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5) �V 30 Vdc Differential Input Signal V8 − V10 V4 − V1 +5.0 ±(5+ I5Re) Vdc Maximum Bias Current I5 10 mA Thermal Resistance, Junction−to−Air Plastic Dual In−Line Package R�JA 100 °C/W Operating Ambient Temperature Range MC1496 MC1496B TA 0 to +70 −40 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Machine Model (MM) ESD 2000 400 V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. MC1496, MC1496B http://onsemi.com 3 ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = −8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k�, Re = 1.0 k�, TA = Tlow to Thigh, all input and output characteristics are single−ended, unless otherwise noted.) (Note 1) Characteristic Fig. Note Symbol Min Typ Max Unit Carrier Feedthrough VC = 60 mVrms sine wave and offset adjusted to zero VC = 300 mVpp square wave: offset adjusted to zero offset not adjusted fC = 1.0 kHz fC = 10 MHz fC = 1.0 kHz fC = 1.0 kHz 5 1 VCFT − − − − 40 140 0.04 20 − − 0.4 200 �Vrms mVrms Carrier Suppression fS = 10 kHz, 300 mVrms fC = 500 kHz, 60 mVrms sine wave fC = 10 MHz, 60 mVrms sine wave 5 2 VCS 40 − 65 50 − − dB k Transadmittance Bandwidth (Magnitude) (RL = 50 �) Carrier Input Port, VC = 60 mVrms sine wave fS = 1.0 kHz, 300 mVrms sine wave Signal Input Port, VS = 300 mVrms sine wave|VC| = 0.5 Vdc 8 8 BW3dB − − 300 80 − − MHz Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 − V/V Single−Ended Input Impedance, Signal Port, f = 5.0 MHz Parallel Input Resistance Parallel Input Capacitance 6 − rip cip − − 200 2.0 − − k� pF Single−Ended Output Impedance, f = 10 MHz Parallel Output Resistance Parallel Output Capacitance 6 − rop coo − − 40 5.0 − − k� pF Input Bias Current 7 − I 12 30 �A IbS� I1 � I4 2 ; IbC � I8 � I10 2 IbS IbC − − 12 12 30 30 � Input Offset Current IioS = I1−I4; IioC = I8−I10 7 −  IioS IioC − − 0.7 0.7 7.0 7.0 �A Average Temperature Coefficient of Input Offset Current (TA = −55°C to +125°C) 7 − TCIio − 2.0 − nA/°C Output Offset Current (I6−I9) 7 −  Ioo − 14 80 �A Average Temperature Coefficient of Output Offset Current (TA = −55°C to +125°C) 7 − TCIoo − 90 − nA/°C Common−Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV − 5.0 − Vpp Common−Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 − ACM − −85 − dB Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 − Vout − 8.0 − Vpp Differential Output Voltage Swing Capability 10 − Vout − 8.0 − Vpp Power Supply Current I6 +I12 Power Supply Current I14 7 6 ICC IEE − − 2.0 3.0 4.0 5.0 mAdc DC Power Dissipation 7 5 PD − 33 − mW 1. Tlow = 0°C for MC1496 Thigh = +70°C for MC1496 = −40°C for MC1496B = +125°C for MC1496B MC1496, MC1496B http://onsemi.com 4 GENERAL OPERATING INFORMATION Carrier Feedthrough Carrier feedthrough is defined as the output voltage at carrier frequency with only the carrier applied (signal voltage = 0). Carrier null is achieved by balancing the currents in the differential amplifier by means of a bias trim potentiometer (R1 of Figure 5). Carrier Suppression Carrier suppression is defined as the ratio of each sideband output to carrier output for the carrier and signal voltage levels specified. Carrier suppression is very dependent on carrier input level, as shown in Figure 22. A low value of the carrier does not fully switch the upper switching devices, and results in lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The MC1496 has been characterized with a 60 mVrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is generally recommended for balanced modulator applications. Carrier feedthrough is independent of signal level, VS. Thus carrier suppression can be maximized by operating with large signal levels. However, a linear operating mode must be maintained in the signal−input transistor pair − or harmonics of the modulating signal will be generated and appear in the device output as spurious sidebands of the suppressed carrier. This requirement places an upper limit on input−signal amplitude (see Figure 20). Note also that an optimum carrier level is recommended in Figure 22 for good carrier suppression and minimum spurious sideband generation. At higher frequencies circuit layout is very important in order to minimize carrier feedthrough. Shielding may be necessary in order to prevent capacitive coupling between the carrier input leads and the output leads. Signal Gain and Maximum Input Level Signal gain (single−ended) at low frequencies is defined as the voltage gain, AVS � Vo VS � RL Re�2re where re� 26 mV I5(mA) A constant dc potential is applied to the carrier input terminals to fully switch two of the upper transistors “on” and two transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode differential amplifier. Linear operation requires that the signal input be below a critical value determined by RE and the bias current I5. VS � I5 RE (Volts peak) Note that in the test circuit of Figure 10, VS corresponds to a maximum value of 1.0 V peak. Common Mode Swing The common−mode swing is the voltage which may be applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper switching devices. This swing is variable depending on the particular circuit and biasing conditions chosen. Power Dissipation Power dissipation, PD, within the integrated circuit package should be calculated as the summation of the voltage−current products at each port, i.e. assuming V12 = V6, I5 = I6 = I12 and ignoring base current, PD = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer to pin numbers. Design Equations The following is a partial list of design equations needed to operate the circuit with other supply voltages and input conditions. A. Operating Current The internal bias currents are set by the conditions at Pin 5. Assume: I5 = I6 = I12, IB�� IC for all transistors then : R5� V��� I5 �500 � where: R5 is the resistor between where: Pin 5 and ground where: � = 0.75 at TA = +25°C The MC1496 has been characterized for the condition I5 = 1.0 mA and is the generally recommended value. B. Common−Mode Quiescent Output Voltage V6 = V12 = V+ − I5 RL Biasing The MC1496 requires three dc bias voltage levels which must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector−base bias on all transistors while not exceeding the voltages given in the absolute maximum rating table; 30 Vdc � [(V6, V12) − (V8, V10)] � 2 Vdc 30 Vdc � [(V8, V10) − (V1, V4)] � 2.7 Vdc 30 Vdc � [(V1, V4) − (V5)] � 2.7 Vdc The foregoing conditions are based on the following approximations: V6 = V12, V8 = V10, V1 = V4 MC1496, MC1496B http://onsemi.com 5 Bias currents flowing into Pins 1, 4, 8 and 10 are transistor base currents and can normally be neglected if external bias dividers are designed to carry 1.0 mA or more. Transadmittance Bandwidth Carrier transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: �21C� io (each sideband) vs (signal)  Vo� 0 Signal transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: �21S� io (signal) vs (signal)Vc � 0.5 Vdc, Vo� 0 Coupling and Bypass Capacitors Capacitors C1 and C2 (Figure 5) should be selected for a reactance of less than 5.0 � at the carrier frequency. Output Signal The output signal is taken from Pins 6 and 12 either balanced or single−ended. Figure 11 shows the output levels of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single−ended output connection. Negative Supply VEE should be dc only. The insertion of an RF choke in series with VEE can enhance the stability of the internal current sources. Signal Port Stability Under certain values of driving source impedance, oscillation may occur. In this event, an RC suppression network should be connected directly to each input using short leads. This will reduce the Q of the source−tuned circuits that cause the oscillation. Signal Input (Pins 1 and 4) 510 10 pF An alternate method for low−frequency applications is to insert a 1.0 k� resistor in series with the input (Pins 1, 4). In this case input current drift may cause serious degradation of carrier suppression. NOTE: Shielding of input and output leads may be needed to properly perform these tests. Figure 5. Carrier Rejection and Suppression Figure 6. Input−Output Impedance Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth 0.01 �F2.0 k -8.0 Vdc I6 I9 1.0 k I7 I8 6.8 k Zout +�Vo + +�Vo I9 3 RL 3.9 k VCC 12 Vdc 8 C1 0.1 �F MC1496 1.0 k 2 Re 1.0 k C2 0.1 �F 51 10 k Modulating Signal Input Carrier Input VC Carrier Null 515110 k 50 k R1 VS -�Vo RL 3.9 k I6 I4 6 14 5 12 - 2 Re = 1.0 k 3 Zin 0.5 V 8 10 I1 4 1 -�Vo10 1 6 4 14 5 12 6.8 k V- I10 I5 -8.0 Vdc VEE 1.0 k MC1496 MC1496MC1496 6 14 5 12 I10 6.8 k -8.0 Vdc VEE VCC 12 Vdc 2 Re = 1.0 k 3 1.0 k Modulating Signal Input Carrier Input VC VS 0.1 �F 0.1 �F 1.0 k 51 1.0 k 14 5 6 12 1.0 k 2 3 Re VCC 12 Vdc 2.0 k +�Vo -�Vo 6.8 k 10 k Carrier Null 5110 k 50 k V- -8.0 Vdc VEE 50 50 8 10 4 1 8 10 4 1 51 TEST CIRCUITS Administrator 高亮 图7。偏置和失调电流 Administrator 高亮 图8。跨导带宽 Administrator 高亮 图6。输入输出阻抗 Administrator 高亮 图5。载波抑制和制止 Administrator 高亮 输入和输出引线屏蔽可能需要正确执行这些测试 MC1496, MC1496B http://onsemi.com 6 +�Vo 3 3.9 k VCC 12 Vdc 8 MC1496 2 Re = 1.0 k 1.0 k 0.5 V 1.0 k 50 + VS -�Vo 10 1 6 4 14 5 12 6.8 k -8.0 Vdc VEE 3.9 k - A CM � 20 log� � Vo V S Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing V , O U TP U T A M P LI TU D E O F E A C H S ID E B A N D (V rm s) O r , PA R A LL E L IN P U T R E S IS TA N C E (k ip Figure 11. Sideband Output versus Carrier Levels Figure 12. Signal−Port Parallel−Equivalent Input Resistance versus Frequency c , P A R A LL E L IN P U T C A PA C IT A N C E (p F) ip c , P A R A LL E L O U TP U T C A PA C IT A N C E (p F) op Figure 13. Signal−Port Parallel−Equivalent Input Capacitance versus Frequency Figure 14. Single−Ended Output Impedance versus Frequency TYPICAL CHARACTERISTICS Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. I5 = 1.0 mA +�Vo 3 3.9 k VCC 12 Vdc 2 Re = 1.0 k -�Vo 6 14 5 12 6.8 k -8.0 Vdc VEE 3.9 k 0.5 V + - 1.0 k 1.0 k VS 50 1.0 2.0 0 140 -rip +rip 14 12 10 8.0 6.0 4.0 0 10010 120 0 10 1.0 20 5.0 100 40 50 1.0 1.0 f, FREQUENCY (MHz) 80 200 2.0 5.0 10 100 100 500 1.0 M 60 50 100102.0 3.0 2.0 1.0 0 5.0 400 mV Signal Input = 600 mV 4.0 VC, CARRIER LEVEL (mVrms) 1.6 0 0.8 0 0.4 1.2 10050 150 5.0 100 mV 200 mV 300 mV 5020 f, FREQUENCY (MHz)f, FREQUENCY (MHz) MC1496 8 10 1 4 rop Ω ) r , P A R A LL E L O U TP U T R E S IS TA N C E (k op Ω ) cop Administrator 高亮 图9。共模增益 Administrator 高亮 图10。信号增益和输出摆幅 MC1496, MC1496B http://onsemi.com 7 -�30 f, FREQUENCY (MHz) 20 10 0 -�10 -�20 0.1 1.0 10 1000.01 RL = 3.9 k Re = 500 � RL = 3.9 k Re = 2.0 k |VC| = 0.5 Vdc RL = 500 � Re = 1.0 k RL = 3.9 k (Standard Re = 1.0 k Test Circuit) A �, S IN G LE ›E N D E D V O LT A G E G A IN (d B ) V S 1001.0 Side Band 0.3 0.4 0 1000 fC, CARRIER FREQUENCY (MHz) 0.6 0.9 1.0 10 0.8 0.7 0.1 0.2 0.5 0.1 21 , T R A N S A D M IT TA N C E (m m ho ) 80 0 fC ± 3fS 800600400200 VS, INPUT SIGNAL AMPLITUDE (mVrms) fC ± 2fS 0 60 50 40 30 20 10 70 S U P P R E S S IO N B E LO W E A C H F U N D A M E N TA L C A R R IE R S ID E B A N D (d B ) fC 2fC 505.00.05 0.1 0.5 1.0 10 3fC 0 60 50 40 30 20 10 70 fC, CARRIER FREQUENCY (MHz) S U P P R E S S IO N B E LO W E A C H F U N D A M E N TA L C A R R IE R S ID E B A N D (d B ) TA, AMBIENT TEMPERATURE (°C) MC1496 (70°C) -75 -50 60 7550250-25 50 40 30 20 10 100 125 150 175 70 C S V , C A R R IE R S U P P R E S IO N (d B ) AV � RL Re� 2re TYPICAL CHARACTERISTICS (continued) Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. 0.1 5010 10 1.0 0.01 1.0 5.00.05 0.1 0.5 fC, CARRIER FREQUENCY (MHz) V , C A R R IE R O U TP U T V O LT A G E (m Vr m s) C FT Signal Port 0 Figure 15. Sideband and Signal Port Transadmittances versus Frequency Figure 16. Carrier Suppression versus Temperature Figure 17. Signal−Port Frequency Response Figure 18. Carrier Suppression versus Frequency Figure 19. Carrier Feedthrough versus Frequency Figure 20. Sideband Harmonic Suppression versus Input Signal Level γ �21 � Iout Vin �Vout � 0��|VC| � 0.5�Vdc �21 � Iout�(Each�Sideband) Vin�(Signal) �Vout � 0 Sideband Transadmittance Signal Port Transadmittance MC1496, MC1496B http://onsemi.com 8 500100 4003000 200 VC, CARRIER INPUT LEVEL (mVrms) fC = 10 MHz 0 60 50 40 30 20 10 70 C S V , C A R R IE R S U P P R E S S IO N (d B ) 2fC ± fS 2fC ± 2fS 3fC ± fS fC, CARRIER FREQUENCY (MHz) 50101.0 5.00.05 0.1 0.5 0 60 50 40 30 20 10 70 S U P P R E S S IO N B E LO W E A C H F U N D A M E N TA L C A R R IE R S ID E B A N D (d B ) Figure 21. Suppression of Carrier Harmonic Sidebands versus Carrier Frequency Figure 22. Carrier Suppression versus Carrier Input Level fC = 500 kHz OPERATIONS INFORMATION The MC1496, a monolithic balanced modulator circuit, is shown in Figure 23. This circuit consists of an upper quad differential amplifier driven by a standard differential amplifier with dual current sources. The output collectors are cross−coupled so that full−wave balanced multiplication of the two input voltages occurs. That is, the output signal is a constant times the product of the two input signals. Mathematical analysis of linear ac signal multiplication indicates that the output spectrum will consist of only the sum and difference of the two input frequencies. Thus, the device may be used as a balanced modulator, doubly balanced mixer, product detector, frequency doubler, and other applications requiring these particular output signal characteristics. The lower differential amplifier has its emitters connected to the package pins so that an external emitter resistance may be used. Also, external load resistors are employed at the device output. Signal Levels The upper quad differential amplifier may be operated either in a linear or a saturated mode. The lower differential amplifier is operated in a linear mode for most applications. For low−level operation at both input ports, the output signal will contain sum and difference frequency components and have an amplitude which is a function of the product of the input signal amplitudes. For high−level operation at the carrier input port and linear operation at the modulating signal port, the output signal will contain sum and difference frequency components of the modulating signal frequency and the fundamental and odd harmonics of the carrier frequency. The output amplitude will be a constant times the modulating signal amplitude. Any amplitude variations in the carrier signal will not appear in the output. The linear signal handling capabilities of a differential amplifier are well defined. With no emitter degeneration, the maximum input voltage for linear operation is approximately 25 mV peak. Since the upper differential amplifier has its emitters internally connected, this voltage applies to the carrier input port for all conditions. Since the lower differential amplifier has provisions for an external emitter resistance, its linear signal handling range may be adjusted by the user. The maximum input voltage for linear operation may be approximated from the following expression: V = (I5) (RE) volts peak. This expression may be used to compute the minimum value of RE for a given input voltage amplitude. Signal Input Carrier Input 8 (+) 500500 500 14VEE Bias VC (Pin numbers per G package) Vo, Output (-) 12 2 Gain Adjust 3 (+) 6 VS 10 (-) 4 (-) 1 (+) 5 -Vo Re 1.0 k2 12 Vdc RL 3.9 k +Vo VEE -8.0 Vdc 6.8 kI5 14 0.1 �F 12 MC1496 6 8 1.0 k1.0 k 50 k 51 10 k10 k 0.1 �F Carrier Input Modulating Signal Input VS VC Carrier Null 51 3 51 4 1 10 5 RL 3.9 k Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit Administrator 高亮 图24。典型的调制器电路 Administrator 高亮 图23。电路原理图 MC1496, MC1496B http://onsemi.com
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