DG211

1 File Number 3118.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 DG211, DG212 SPST 4-Channel Analog Switches The DG211 and DG212 are low cost, CMOS monolithic, Quad SPST analog switches. These can be used in general purpose switching applications for communications, instrumentation, process control and computer peripheral equipment. Both devices provide true bidirectional performance in the ON condition and will block signals to 30VP-P in the OFF condition. The DG211 and DG212 differ only in that the digital control logic is inverted, as shown in the truth table. Pinout DG211, DG212 (PDIP, SOIC) TOP VIEW Features • Switches ±15V Analog Signals • TTL Compatibility • Logic Inputs Accept Negative Voltages • rON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω Functional Block Diagrams DG211 DG212 Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. DG211CJ 0 to 70 16 Ld PDIP E16.3 DG212CJ 0 to 70 16 Ld PDIP E16.3 DG211CY 0 to 70 16 Ld SOIC M16.15 DG212CY 0 to 70 16 Ld SOIC M16.15 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 IN1 D1 S1 V- GND S4 IN4 D4 IN2 S2 V+ (SUB- VL (+5V) S3 D3 IN3 D2 STRATE)- TRUTH TABLE LOGIC DG211 DG212 0 ON OFF 1 OFF ON Logic “0” ≤0.8V, Logic “1” ≥ 2.4V IN1 S1 D1 IN2 S2 D2 IN3 S3 D3 IN4 S4 D4 IN1 S1 D1 IN2 S2 D2 IN3 S3 D3 IN4 S4 D4 SWITCHES SHOWN FOR LOGIC “1” INPUT Data Sheet June 1999 2 Schematic Diagram DG211 (1/4 AS SHOWN) TTL IN GND +15V +5V VL -15V -15V V- -15V +15V OUTIN DG211, DG212 3 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V VIN to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V VS or VD to V+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to -36V VS or VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 36V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Current, any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = +15V, V- = -15V, VL = +5V, GND, TA = 25oC PARAMETER TEST CONDITIONS (NOTE 2) MIN (NOTE 3) TYP MAX UNITS DYNAMIC CHARACTERISTICS Turn-ON Time, tON See Figure 1 VS = 10V, RL = 1kΩ, CL = 35pF - 460 - ns Turn-OFF Time, tOFF1 - 360 - ns tOFF2 - 450 - ns OFF Isolation, OIRR (Note 5) VIN = 5V, RL = 1kΩ, CL = 15pF, VS = 1VRMS, f = 100kHz - 70 - dB Crosstalk (Channel to Channel), CCRR - -90 - dB Source OFF Capacitance, CS(OFF) VD = VS = 0V, VIN = 5V, f = 1MHz - 5 - pF Drain OFF Capacitance, CD(OFF) - 5 - pF Channel ON Capacitance, CD(ON) + CS(ON) - 16 - pF DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, IIH VIN = 2.4V -1.0 -0.0004 - µA VIN = 15V - 0.003 1.0 µA Input Current with Voltage Low, IIL VIN = 0V -1.0 -0.0004 - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG -15 - 15 V Drain-Source ON Resistance, rDS(ON) VD = ±10V, VIN = 2.4V (DG212) IS = 1mA, VIN = 0.8V (DG211) - 150 175 Ω Source OFF Leakage Current, IS(OFF) VIN = 2.4V (DG211) VIN = 0.8V (DG212) VS = 14V, VD = -14V - 0.01 5.0 nA VS = -14V, VD = 14V -5.0 -0.02 - nA Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V - 0.01 5.0 nA VS = 14V, VD = -14V -5.0 -0.02 - nA Drain ON Leakage Current, ID(ON) (Note 4) VIN = 0.8V (DG211) VIN = 2.4V (DG212) VS = VD = 14V - 0.1 5.0 nA VS = VD = -14V -5.0 -0.15 - nA DG211, DG212 4 Test Circuits and Waveforms Switch output waveform shown for VS = constant with logic input waveform as shown. Note the VS may be + or - as per switching time test circuit. VO is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform. POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ VIN = 0V or 2.4V - 0.1 10 µA Negative Supply Current, I- - 0.1 10 µA Logic Supply Current, IL - 0.1 10 µA NOTES: 2. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet. 3. For design reference only, not 100% tested. 4. ID(ON) is leakage from driver into ON switch. 5. . Electrical Specifications V+ = +15V, V- = -15V, VL = +5V, GND, TA = 25oC (Continued) PARAMETER TEST CONDITIONS (NOTE 2) MIN (NOTE 3) TYP MAX UNITS OFF Isolation 20 VS VD -------- , VSlog Input to OFF switch, VD output= = = † Logic shown for DG211. Invert for DG212. FIGURE 1. SWITCHING TIME MEASUREMENT POINTS FIGURE 2. SWITCHING TIME TEST CIRCUIT 50% 90% 0V tOFF2 LOGIC† INPUT (IN1) SWITCH OUTPUT (VO) VS tON tr < 20ns tf < 20ns 90% SWITCH INPUT 10% tOFF1 VO S1 IN1LOGIC INPUT GND VS = 10V RL 1kΩ CL 35pF SWITCH OUTPUT 15V V+ -15V V- SWITCH INPUT (REPEAT TEST FOR IN2, IN3 AND IN4) VO = VS RL RL + rDS(ON) D1 5V VL DG211, DG212 5 Die Characteristics DIE DIMENSIONS: 2159µm x 2235µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride PSG Thickness: 7kÅ ±1.4kÅ Nitride Thickness: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG211, DG212 PIN 2 D1 PIN 3 S1 PIN 4 V- PIN 5 GND PIN 6 S4 PIN 7 D4 PIN 8 IN 4 PIN 9 IN 3 PIN 10 D3 PIN 11 S3 PIN 12 VL PIN 13 V+ (SUBSTRATE) PIN 14 S2 PIN 15 D2 PIN 16 IN 2 PIN 1 IN 1 DG211, DG212 6 DG211, DG212 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- CL E eA C eB eC -B- E1 INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- D1 B1 B e D D1 AA2 L A1 -A- 0.010 (0.25) C AM B S E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 16 16 9 Rev. 0 12/93 7 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 DG211, DG212 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 1 2 3 -B- 0.25(0.010) C AM B S e -A- L B M -C- A1 A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N 16 16 7 α 0o 8o 0o 8o - Rev. 0 12/93