[翻译版]FPGA设计经验谈

'1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � FPGA/CPLD᭄ᄫ⬉䏃䆒䅵㒣偠ߚѿ ᨬ㽕˖೼᭄ᄫ⬉䏃ⱘ䆒䅵Ёˈᯊᑣ䆒䅵ᰃϔϾ㋏㒳ᗻ㛑ⱘЏ㽕ᷛᖫˈ೼催ሖ⃵䆒䅵ᮍ⊩Ёˈᇍᯊᑣ᥻ࠊⱘ ᢑ䈵ᑺгⳌᑨᦤ催ˈ಴ℸ೼䆒䅵Ё䕗䲒ᡞᦵˈԚ೼⧚㾷 RTL⬉䏃ᯊᑣ῵ൟⱘ෎⸔Ϟˈ䞛⫼ড়⧚ⱘ䆒䅵ᮍ⊩ ೼䆒䅵໡ᴖ᭄ᄫ㋏㒳ᰃ㸠П᳝ᬜⱘˈ䗮䖛䆌໮䆒䅵ᅲ՟䆕ᯢ䞛⫼䖭⾡ᮍᓣৃҹՓ⬉䏃ⱘৢӓⳳ䗮䖛⥛໻໻ ᦤ催ˈᑊϨ㋏㒳ⱘᎹ԰乥⥛ৃҹ䖒ࠄϔϾ䕗催∈ᑇDŽ ݇䬂䆡˖FPGA ᭄ᄫ⬉䏃 ᯊᑣ ᯊᓊ䏃ᕘ ᓎゟᯊ䯈 ֱᣕᯊ䯈 1 ᭄ᄫ⬉䏃䆒䅵Ёⱘ޴Ͼ෎ᴀὖᗉ˖ 1.1 ᓎゟᯊ䯈੠ֱᣕᯊ䯈˖ ᓎゟᯊ䯈˄setup time˅ᰃᣛ೼㾺থ఼ⱘᯊ䩳ֵোϞछ⊓ࠄᴹҹࠡˈ᭄᥂〇ᅮϡবⱘᯊ䯈ˈབᵰᓎゟᯊ 䯈ϡ໳ˈ᭄᥂ᇚϡ㛑೼䖭Ͼᯊ䩳Ϟछ⊓㹿ᠧܹ㾺থ఼˗ֱᣕᯊ䯈˄hold time˅ᰃᣛ೼㾺থ఼ⱘᯊ䩳ֵোϞ छ⊓ࠄᴹҹৢˈ᭄᥂〇ᅮϡবⱘᯊ䯈ˈ བᵰֱᣕᯊ䯈ϡ໳ˈ᭄᥂ৠḋϡ㛑㹿ᠧܹ㾺থ఼DŽ བ೒ 1 DŽ ᭄ ᥂〇ᅮӴ䕧ᖙ乏⒵䎇ᓎゟ੠ֱᣕᯊ䯈ⱘ㽕∖ˈᔧ✊೼ϔѯᚙމϟˈᓎゟᯊ䯈੠ֱᣕᯊ䯈ⱘؐৃҹЎ䳊DŽ PLD/FPGAᓔথ䕃ӊৃҹ㞾ࡼ䅵ㅫϸϾⳌ݇䕧ܹⱘᓎゟ੠ֱᣕᯊ䯈˄བ೒ 2˅ ೒ 1 ᓎゟᯊ䯈੠ֱᣕᯊ䯈݇㋏೒ ⊼˖ ೼㗗㰥ᓎゟֱᣕᯊ䯈ᯊˈᑨ䆹㗗㰥ᯊ䩳ᷥ৥ৢأ᭰ⱘᚙމˈ೼㗗㰥ᓎゟᯊ䯈ᯊᑨ䆹㗗㰥ᯊ䩳ᷥ৥ ࠡأ᭰ⱘᚙމDŽ೼䖯㸠ৢӓⳳᯊˈ᳔໻ᓊ䖳⫼ᴹẔᶹᓎゟᯊ䯈ˈ᳔ᇣᓊᯊ⫼ᴹẔᶹֱᣕᯊ䯈DŽ ᓎゟᯊ䯈ⱘ㑺ᴳ੠ᯊ䩳਼ᳳ᳝݇ˈᔧ㋏㒳೼催乥ᯊ䩳ϟ᮴⊩Ꮉ԰ᯊˈ䰡Ԣᯊ䩳乥⥛ህৃҹՓ㋏㒳 ᅠ៤Ꮉ԰DŽֱᣕᯊ䯈ᰃϔϾ੠ᯊ䩳਼ᳳ᮴݇ⱘখ᭄ˈབᵰ䆒䅵ϡড়⧚ˈՓᕫᏗሔᏗ㒓Ꮉ݋᮴⊩Ꮧ ߎ催䋼䞣ⱘᯊ䩳ᷥˈ䙷М᮴䆎བԩ䇗ᭈᯊ䩳乥⥛г᮴⊩䖒ࠄ㽕∖ˈা᳝ᇍ᠔䆒䅵㋏㒳԰䕗໻ᬍࡼ ᠡ᳝ৃ㛑ℷᐌᎹ԰ˈᇐ㟈䆒䅵ᬜ⥛໻໻䰡ԢDŽ಴ℸড়⧚ⱘ䆒䅵㋏㒳ⱘᯊᑣᰃᦤ催䆒䅵䋼䞣ⱘ݇䬂DŽ ೼ৃ㓪⿟఼ӊЁˈᯊ䩳ᷥⱘأ᭰޴Тৃҹϡ㗗㰥ˈ಴ℸֱᣕᯊ䯈䗮ᐌ䛑ᰃ⒵䎇ⱘDŽ1.2 FPGAЁⱘ ゲѝ੠ݦ䰽⦄䈵 ֵো೼ FPGA఼ӊݙ䚼䗮䖛䖲㒓੠䘏䕥ऩܗᯊˈ䛑᳝ϔᅮⱘᓊᯊDŽᓊᯊⱘ໻ᇣϢ䖲㒓ⱘ䭓ⷁ੠䘏䕥ऩ ܗⱘ᭄Ⳃ᳝݇ˈৠᯊ䖬ফ఼ӊⱘࠊ䗴Ꮉ㡎ǃᎹ԰⬉य़ǃ⏽ᑺㄝᴵӊⱘᕅડDŽֵোⱘ催Ԣ⬉ᑇ䕀ᤶг䳔㽕ϔ ᅮⱘ䖛⏵ᯊ䯈DŽ⬅Ѣᄬ೼䖭ϸᮍ䴶಴㋴ˈ໮䏃ֵোⱘ⬉ᑇؐথ⫳ব࣪ᯊˈ೼ֵোব࣪ⱘⶀ䯈ˈ㒘ড়䘏䕥ⱘ 䕧ߎ᳝ܜৢ乎ᑣˈᑊϡᰃৠᯊব࣪,ᕔᕔӮߎ⦄ϔѯϡℷ⹂ⱘᇪዄֵোˈ䖭ѯᇪዄֵো⿄Ў"↯ࠎ"DŽབᵰϔ Ͼ㒘ড়䘏䕥⬉䏃Ё᳝"↯ࠎ"ߎ⦄ˈህ䇈ᯢ䆹⬉䏃ᄬ೼"ݦ䰽"DŽ˄Ϣߚゟܗӊϡৠˈ⬅Ѣ PLDݙ䚼ϡᄬ೼ᆘ ⫳⬉ᆍ⬉ᛳˈ䖭ѯ↯ࠎᇚ㹿ᅠᭈⱘֱ⬭ᑊ৥ϟϔ㑻Ӵ䗦ˈ಴ℸ↯ࠎ⦄䈵೼ PLDǃFPGA䆒䅵ЁᇸЎさߎ˅ ೒ 2ᰃϔϾ䘏䕥ݦ䰽ⱘ՟ᄤ Ңˈ೒ 3ⱘӓⳳ⊶ᔶৃҹⳟߎ "ˈAǃBǃCǃD"ಯϾ䕧ֵܹো㒣䖛Ꮧ㒓ᓊᯊҹৢˈ 催Ԣ⬉ᑇবᤶϡᰃৠᯊথ⫳ⱘˈ䖭ᇐ㟈䕧ߎֵো"OUT"ߎ⦄њ↯ࠎDŽ˄៥Ӏ᮴⊩ֱ䆕᠔᳝䖲㒓ⱘ䭓ᑺϔ㟈ˈ 1 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ᠔ҹेՓಯϾ䕧ֵܹো೼䕧ܹッৠᯊব࣪ˈԚ㒣䖛 PLDݙ䚼ⱘ䍄㒓ˈࠄ䖒៪䮼ⱘᯊ䯈гᰃϡϔḋⱘˈ↯ࠎ ᖙ✊ѻ⫳˅DŽৃҹὖᣀⱘ䆆ˈা㽕䕧ֵܹোৠᯊব࣪ˈ˄㒣䖛ݙ䚼䍄㒓˅㒘ড়䘏䕥ᖙᇚѻ⫳↯ࠎDŽ ᇚᅗӀ ⱘ䕧ߎⳈ᥹䖲᥹ࠄᯊ䩳䕧ܹッǃ⏙䳊៪㕂ԡッষⱘ䆒䅵ᮍ⊩ᰃ䫭䇃ⱘˈ䖭ৃ㛑Ӯᇐ㟈Ϲ䞡ⱘৢᵰDŽ ᠔ҹ៥ Ӏᖙ乏Ẕᶹ䆒䅵Ё᠔᳝ᯊ䩳ǃ⏙䳊੠㕂ԡㄝᇍ↯ࠎᬣᛳⱘ䕧ܹッষˈ⹂ֱ䕧ܹϡӮ৿᳝ӏԩ↯ࠎ ೒ 2 ᄬ೼䘏䕥ݦ䰽ⱘ⬉䏃⼎՟ ೒ 3 ೒ 2᠔⼎⬉䏃ⱘӓⳳ⊶ᔶ ݦ䰽ᕔᕔӮᕅડࠄ䘏䕥⬉䏃ⱘ〇ᅮᗻDŽᯊ䩳ッষǃ⏙䳊੠㕂ԡッষᇍ↯ࠎֵোकߚᬣᛳˈӏԩϔ⚍↯ ࠎ䛑ৃ㛑ӮՓ㋏㒳ߎ䫭ˈ಴ℸ߸ᮁ䘏䕥⬉䏃Ёᰃ৺ᄬ೼ݦ䰽ҹঞབԩ䙓ܡݦ䰽ᰃ䆒䅵Ҏਬᖙ乏㽕㗗㰥ⱘ䯂 乬DŽ བԩ໘⧚↯ࠎ ៥Ӏৃҹ䗮䖛ᬍব䆒䅵ˈ⸈ണ↯ࠎѻ⫳ⱘᴵӊˈᴹޣᇥ↯ࠎⱘথ⫳DŽ՟བˈ೼᭄ᄫ⬉䏃䆒䅵Ёˈᐌᐌ 䞛⫼Ḑ䳋ⷕ䅵఼᭄পҷ᱂䗮ⱘѠ䖯ࠊ䅵఼᭄ˈ䖭ᰃ಴ЎḐ䳋ⷕ䅵఼᭄ⱘ䕧ߎ↣⃵া᳝ϔԡ䏇বˈ⍜䰸њゲ ѝݦ䰽ⱘথ⫳ᴵӊˈ䙓ܡњ↯ࠎⱘѻ⫳DŽ ↯ࠎᑊϡᰃᇍ᠔᳝ⱘ䕧ܹ䛑᳝ॅᆇˈ՟བ D㾺থ఼ⱘ D䕧ܹッˈা㽕↯ࠎϡߎ⦄೼ᯊ䩳ⱘϞछ⊓ᑊϨ ⒵䎇᭄᥂ⱘᓎゟ੠ֱᣕᯊ䯈 ህˈϡӮᇍ㋏㒳䗴៤ॅᆇ ៥ˈӀৃҹ䇈 D㾺থ఼ⱘ D䕧ܹッᇍ↯ࠎϡᬣᛳDŽḍ ᥂䖭Ͼ⡍ᗻˈ៥Ӏᑨᔧ೼㋏㒳Ёሑৃ㛑䞛⫼ৠℹ⬉䏃ˈ䖭ᰃ಴Ўৠℹ⬉䏃ֵোⱘব࣪䛑থ⫳೼ᯊ䩳⊓ˈা 㽕↯ࠎϡߎ⦄೼ᯊ䩳ⱘ⊓ষᑊϨϡ⒵䎇᭄᥂ⱘᓎゟ੠ֱᣕᯊ䯈 ህˈϡӮᇍ㋏㒳䗴៤ॅᆇDŽ˄⬅Ѣ↯ࠎᕜⷁˈ ໮Ў޴㒇⾦ˈ෎ᴀϞ䛑ϡৃ㛑⒵䎇᭄᥂ⱘᓎゟ੠ֱᣕᯊ䯈˅ এ䰸↯ࠎⱘϔ⾡ᐌ㾕ⱘᮍ⊩ᰃ߽⫼ D㾺থ఼ⱘ D䕧ܹッᇍ↯ࠎֵোϡᬣᛳⱘ⡍⚍ ೼ˈ䕧ߎֵোⱘֱᣕ ᯊ䯈ݙˈ⫼㾺থ఼䇏প㒘ড়䘏䕥ⱘ䕧ߎֵোˈ䖭⾡ᮍ⊩㉏ԐѢᇚᓖℹ⬉䏃䕀࣪Ўৠℹ⬉䏃DŽ ೒ 4㒭ߎњ䖭 ⾡ᮍ⊩ⱘ⼎㣗⬉䏃ˈ೒ 5ᰃӓⳳ⊶ᔶDŽ 2 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 4 ⍜䰸↯ࠎֵোᮍ⊩ПѠ ೒ 5 ೒ 4᠔⼎⬉䏃ⱘӓⳳ⊶ᔶ བࠡ᠔䗄ˈӬ⾔ⱘ䆒䅵ᮍḜˈབ䞛⫼Ḑ䳋ⷕ䅵఼᭄ˈৠℹ⬉䏃ㄝˈৃҹ໻໻ޣᇥ↯ࠎˈԚᅗᑊϡ㛑ᅠ ܼ⍜䰸↯ࠎDŽ ↯ࠎᑊϡᰃᇍ᠔᳝䕧ܹ䛑᳝ॅᆇˈ՟བ D 㾺থ఼ⱘ D 䕧ܹッˈা㽕↯ࠎϡߎ⦄೼ᯊ䩳ⱘϞ छ⊓ᑊϨ⒵䎇᭄᥂ⱘᓎゟ੠ֱᣕᯊ䯈ˈህϡӮᇍ㋏㒳䗴៤ॅᆇDŽ಴ℸ៥Ӏৃҹ䇈 D㾺থ఼ⱘ D䕧ܹッᇍ↯ ࠎϡᬣᛳDŽԚᇍѢ D㾺থ఼ⱘᯊ䩳ッˈ㕂ԡッˈ⏙䳊ッˈ߭䛑ᰃᇍ↯ࠎᬣᛳⱘ䕧ܹッˈӏԩϔ⚍↯ࠎህӮ Փ㋏㒳ߎ䫭ˈԚা㽕䅸ⳳ໘⧚ˈ៥Ӏৃҹᡞॅᆇ䰡ࠄ᳔ԢⳈ㟇⍜䰸DŽϟ䴶៥Ӏህᇍ޴⾡݋ԧⱘֵো䖯㸠᥶ 䅼DŽ 1.3 ⏙䰸੠㕂ԡֵো ೼ FPGA ⱘ䆒䅵Ёˈܼሔⱘ⏙䳊੠㕂ԡֵোᖙ乏㒣䖛ܼሔⱘ⏙䳊੠㕂ԡㅵ㛮䕧ܹˈ಴ЎҪӀгሲѢܼ ሔⱘ䌘⑤ˈ݊᠛ߎ㛑࡯໻ˈ㗠Ϩ೼ FPGA ݙ䚼ᰃⳈ᥹䖲᥹ࠄ᠔᳝ⱘ㾺থ఼ⱘ㕂ԡ੠⏙䳊ッⱘˈ䖭ḋⱘخ⊩ ӮՓ㢃⠛ⱘᎹ԰ৃ䴴ǃᗻ㛑〇ᅮˈ㗠Փ⫼᱂䗮ⱘ IO㛮߭ϡ㛑ֱ䆕䆹ᗻ㛑DŽ ೼ FPGAⱘ䆒䅵Ёˈ䰸њҢ໪䚼ㅵ㛮ᓩܹⱘܼሔ⏙䰸੠㕂ԡֵো໪೼ FPGAݙ䚼䘏䕥ⱘ໘⧚Ёг㒣ᐌ 䳔㽕ѻ⫳ϔѯݙ䚼ⱘ⏙䰸៪㕂ԡֵোDŽ⏙䰸੠㕂ԡֵো㽕∖䈵ᇍᕙᯊ䩳䙷ḋᇣᖗഄ㗗㰥ᅗӀˈ಴Ў䖭ѯֵ োᇍ↯ࠎгᰃ䴲ᐌᬣᛳⱘDŽ ೼ৠℹ⬉䏃䆒䅵Ёˈ᳝ᯊ׭ৃҹ⫼ৠℹ㕂ԡⱘࡲ⊩ᴹ᳓ҷᓖℹ⏙ 0DŽ೼⫼⹀ӊᦣ䗄䇁㿔ⱘ䆒䅵Ёৃҹ ⫼བϟⱘᮍᓣᴹᦣ䗄˖ ᓖℹ⏙ 0ⱘᦣ䗄ᮍ⊩˖ 3 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � process(rst,clk) begin if rst=’1’ then count<=(others=>’0’); elsif clk’event and clk=’1’ then count<=count+1; end if; end process; ৠℹ⏙ 0ⱘᦣ䗄ᮍ⊩˖ process begin wait until clk’event and clk=’1’; if rst=’1’ then count<=(others=>’0’); else count<=count+1; end if; end process; ೒ 6 ᓖℹ⏙ 0ǃ㕂ԡ䘏䕥೒ ೒ 7 ৠℹ⏙ 0ǃ㕂ԡ݇㋏೒ 1.4 㾺থ఼੠䫕ᄬ఼˖ ៥Ӏⶹ䘧ˈ㾺থ఼ᰃ೼ᯊ䩳ⱘ⊓䖯㸠᭄᥂ⱘ䫕ᄬⱘˈ㗠䫕ᄬ఼ᰃ⫼⬉ᑇՓ㛑ᴹ䫕ᄬ᭄᥂ⱘDŽ᠔ҹ㾺থ ఼ⱘ Q䕧ߎッ೼↣ϔϾᯊ䩳⊓䛑Ӯ㹿᳈ᮄˈ㗠䫕ᄬ఼া㛑೼Փ㛑⬉ᑇ᳝ᬜ఼ӊᠡӮ㹿᳈ᮄDŽ೼ FPGA䆒䅵 Ёᓎ䆂བᵰϡᰃᖙ乏䙷Мᑨ䆹ሑ䞣Փ⫼㾺থ఼㗠ϡᰃ䫕ᄬ఼DŽ 䙷М೼Փ⫼⹀ӊᦣ䗄䇁㿔䖯㸠⬉䏃䆒䅵ⱘᯊ׭བԩऎߚ㾺থ఼੠䫕ᄬ఼ⱘᦣ䗄ᮍ⊩ા˛݊ᅲ᳝ϡᇥҎ ೼Փ⫼ⱘ䖛⿟Ёৃ㛑ᑊ≵᳝⡍ᛣऎߚ䖛ˈ᠔ҹгᗑ⬹њѠ㗙೼ᦣ䗄ᮍ⊩Ϟⱘऎ߿DŽϟ䴶ᰃ⫼ VHDL䇁㿔ᦣ 䗄ⱘ㾺থ఼੠䫕ᄬ఼ҹঞ㓐ড়఼ѻ⫳ⱘ⬉䏃䘏䕥೒DŽ 㾺থ఼ⱘ䇁㿔ᦣ䗄˖ 4 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � process begin wait until clk’event and clk=’1’; q<=d; end process; ೒ 㾺থ఼ 䫕ᄬ఼ⱘ䇁㿔ᦣ䗄˖ process(en,d) begin if en=’1’ then q<=d; end if; end process; ೒ 䫕ᄬ఼ ⬅Ϟ䗄ᇍ Latchⱘᦣ䗄ৃ㾕ˈ݊ᕜᆍᯧѢ䗝ᢽ఼ⱘᦣ䗄Ⳍ⏋⎚ˈ⫼ VHDL䇁㿔ᇍ䗝ᢽ఼ⱘᦣ䗄ᮍ⊩བ ϟ˖ process(en,a,b) begin if en=’1’ then q<=a; else q<=b; end if; end process; 5 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 2 FPGA/CPLDЁⱘϔѯ䆒䅵ᮍ⊩ 2.1 FPGA䆒䅵Ёⱘৠℹ䆒䅵 ᓖℹ䆒䅵ϡᰃᘏ㛑⒵䎇(ᅗӀ᠔作䗕ⱘ㾺থ఼ⱘ)ᓎゟ੠ֱᣕᯊ䯈ⱘ㽕∖DŽ಴ℸˈᓖℹ䕧ܹᐌᐌӮᡞ䫭 䇃ⱘ᭄᥂䫕ᄬࠄ㾺থ఼ˈ៪㗙Փ㾺থ఼䖯ܹѮ〇ᅮⱘ⢊ᗕˈ೼䆹⢊ᗕϟˈ㾺থ఼ⱘ䕧ߎϡ㛑䆚߿Ў l៪ 0DŽ བᵰ≵᳝ℷ⹂ഄ໘⧚ˈѮ〇ᗻӮᇐ㟈Ϲ䞡ⱘ㋏㒳ৃ䴴ᗻ䯂乬DŽ ঺໪ ೼ˈ FPGAⱘݙ䚼䌘⑤䞠᳔䞡㽕ⱘϔ䚼ߚህᰃ݊ᯊ䩳䌘⑤˄ ܼሔᯊ䩳㔥㒰˅ˈ ᅗϔ㠀ᰃ㒣䖛 FPGA ⱘ⡍ᅮܼሔᯊ䩳ㅵ㛮䖯ܹ FPGAݙ䚼ˈৢ 㒣䖛ܼሔᯊ䩳 BUF䗖䜡ࠄܼሔᯊ䩳㔥㒰ⱘ 䖭ˈḋⱘᯊ䩳㔥㒰ৃҹ ֱ䆕Ⳍৠⱘᯊ䩳⊓ࠄ䖒㢃⠛ݙ䚼↣ϔϾ㾺থ఼ⱘᓊ䖳ᯊ䯈Ꮒᓖᰃৃҹᗑ⬹ϡ䅵ⱘDŽ ೼ FPGAЁϞ䗄ⱘܼሔᯊ䩳㔥㒰㹿⿄Ўᯊ䩳ᷥˈ᮴䆎ᰃϧϮⱘ㄀ϝᮍᎹ݋䖬ᰃ఼ӊॖଚᦤկⱘᏗሔᏗ 㒓఼೼ᓊᯊখ᭄ᦤপǃߚᵤⱘᯊ׭䛑ᰃձ᥂ܼሔᯊ䩳㔥㒰԰Ў䅵ㅫⱘ෎ޚⱘDŽབᵰϔϾ䆒䅵≵᳝Փ⫼ᯊ䩳 ᷥᦤկⱘᯊ䩳ˈ䙷М䖭ѯ䆒䅵Ꮉ݋᳝ⱘӮᢦ㒱خᓊᯊߚᵤǃ᳝ⱘᓊᯊ᭄᥂ᇚᰃϡৃ䴴ⱘDŽ ೼៥Ӏ᮹ᐌⱘ䆒䅵Ёᕜ໮ᚙᔶϟӮ⫼ࠄ䳔㽕ߚ乥ⱘᚙᔶˈད໮Ҏⱘخ⊩ᰃܜ⫼催乥ᯊ䩳䅵᭄ˈ✊ৢՓ ⫼䅵఼᭄ⱘᶤϔԡ䕧ߎ԰ЎᎹ԰ᯊ䩳䖯㸠݊Ҫⱘ䘏䕥䆒䅵DŽ݊ᅲ䖭ḋⱘᮍ⊩ᰃϡ㾘㣗ⱘDŽ↨བϟ䴶ⱘᦣ䗄 ᮍ⊩˖ 6 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � process begin wait until clk’event and clk=’1’; if fck=’1’ then count<=(others=>’0’); else count<=count+1; end if; end process; process begin wait until count(2)’event and count(2)=’1’ ; shift_reg<=data; end process; ೼Ϟ䗄ⱘ㄀ϔϾ process⬉䏃ᦣ䗄Ёˈ佪ܜ䅵఼᭄ⱘ䕧ߎ㒧ᵰ˄count(2)˅ⳌᇍѢܼሔᯊ䩳 clkᏆ㒣ѻ⫳ њϔᅮⱘᓊᯊ˄ᓊᯊⱘ໻ᇣপއѢ䅵఼᭄ⱘԡ᭄੠᠔䗝ᢽՓ⫼ⱘ఼ӊᎹ㡎˅˗㗠೼㄀ѠϾ processЁՓ⫼䅵 ఼᭄ⱘ bit2԰Ўᯊ䩳ˈ䙷М shift_reg ⳌᇍѢܼሔ clk ⱘᓊᯊᇚবᕫϡད᥻ࠊDŽᏗሔᏗ㒓᳔఼㒜㒭ߎⱘᯊ䯈 ߚᵤгᰃϡৃ䴴ⱘDŽ䖭ḋѻ⫳ⱘ㒧ᵰ⊶ᔶӓⳳབϟ೒᠔⼎˖ ℷ⹂ⱘخ⊩ৃҹᇚ㄀ѠϾ process䖭ḋᴹݭDŽ process begin wait until clk’event and clk=’1’ ; if count(2 downto 0)=”000” then shift_reg<=data; end if; end process; ៪㗙ߚ៤ϸℹᴹݭ˖ process(count) begin if count(2 downto 0)=”000” then en<=’1’; else en<=’0’; end if; end process; process begin wait until clk’event and clk=’1’ ; if en=’1’ then shift_reg<=data; end if; end process; 7 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 䖭ḋخᰃⳌᔧѢѻ⫳њϔϾ 8ߚ乥ⱘՓ㛑ֵোˈ೼Փ㛑ֵো᳝ᬜⱘᯊ׭ᇚ data᭄᥂䞛ḋࠄ shift_regᆘ ᄬ఼ЁDŽԚℸ⾡ᚙᔶϟ shift_regⱘᓊᯊᰃⳌᇍѢܼሔᯊ䩳 clkⱘDŽϟ䴶ⱘ೒ᔶ᳈㛑ⳟᕫ⏙ἮDŽ ೒ Ϟ೒Ё⊶ᔶⱘሔ䚼ᬒ໻ 2.2 FPGA䆒䅵Ёⱘᓊᯊ⬉䏃ⱘѻ⫳˖ ೼᮹ᐌⱘ⬉䏃䆒䅵Ёˈ᳝ᯊ׭៥Ӏ䳔㽕ᇍֵো䖯㸠ᓊᯊ໘⧚ᴹ䗖ᑨᇍ໪᥹ষⱘᯊᑣ݇㋏ˈ᳔㒣ᐌгᰃ ᳔݌ൟⱘᚙމᰃخ໘⧚ᴎⱘ᥹ষ˗಴ЎϢ໘⧚ⱘ᥹ষᯊᑣ݇㋏ᰃᓖℹⱘˈ㗠ϔϾ㾘㣗ⱘ FPGA 䆒䅵ᑨ䆹ᰃ ሑৃ㛑䞛⫼ৠℹ䆒䅵DŽ䙷М䘛ࠄ䖭⾡ᚙމ䆹བԩ໘⧚ਸ਼˛ 佪ܜ೼ FPGAЁ㽕ѻ⫳ᓊᯊˈֵোᖙ乏㒣䖛ϔᅮⱘ⠽⧚䌘⑤DŽ೼⹀ӊᦣ䗄䇁㿔Ё᳝݇䬂䆡Wait for xx nsˈ䳔㽕䇈ᯢⱘᰃ䆹䇁⊩ᰃҙҙ⫼Ѣӓⳳ㗠ϡ㛑⫼Ѣ㓐ড়ⱘˈৃ㓐ড়ⱘᓊᯊᮍ⊩᳝˖ ! Փֵো㒣䖛䘏䕥䮼ᕫࠄᓊᯊ˄བ䴲䮼˅˗ ! Փ⫼఼ӊᦤկⱘᓊᯊऩܗ˄བ Altera݀ৌⱘ LCELLˈXilinx݀ৌⱘ˅˗ ⊼ᛣ˖ᔧՓ⫼໮㑻䴲䮼ⱘᯊ׭㓐ড়఼ᕔᕔӮᇚ݊Ӭ࣪ᥝˈ಴Ў㓐ড়఼Ӯ䅸ЎϔϾֵো䴲ϸ⃵䖬ᰃᅗ㞾ᏅDŽ 䳔㽕䇈ᯢⱘᰃ೼ FPGA/CPLDݙ䚼㒧ᵘᰃϔ⾡ᷛޚⱘᅣऩܗˈϟ೒ᰃ Xilinx݀ৌⱘ Spartans II㋏఼߫ӊⱘ ϔϾᷛޚᅣऩܗDŽ㱑✊ϡৠⱘॖᆊⱘ㢃⠛ᅣऩܗⱘ㒧ᵘϡৠˈԚὖᣀ㗠㿔䛑ᰃ⬅ϔѯ㒘ড়䘏䕥໪ࡴϔ៪Ѡ Ͼ㾺থ఼㗠ᵘ៤DŽ೼ᅲ䰙ᑨ⫼Ё ᔧˈϔϾ῵ഫݙⱘ㒘ড়䘏䕥㹿Փ⫼њ䙷МϢ݊ᇍᑨⱘ㾺থ఼гህϡ㛑⫼њ˗ ৠḋབᵰ㾺থ఼ऩܗ㹿⫼њ䙷М㒘ড়䘏䕥ऩܗгህᑳњDŽ䖭ህᰃ᳝ᯊ׭˄⡍߿ᰃՓ⫼ CPLD˅㱑✊䆒䅵Փ ⫼ⱘ䌘⑤ᑊϡ໮ԚᏗሔᏗ㒓఼ै᡹ਞ䌘⑤ϡ໳Փ⫼ⱘॳ಴DŽ 8 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ⦄䴶ⱘϔϾ՟ᄤᰃࠡϔ↉ᯊ䯈៥೼݀ৌ䘛ࠄⱘϔϾ䆒䅵DŽ䆒䅵Փ⫼ Altera݀ৌⱘ EPM7256ൟোⱘ CPLDDŽ 䆹䆒䅵ᅲ䰙Փ⫼ⱘᆘᄬ఼䌘⑤া᳝ 109ϾˈऴᭈϾ఼ӊ䌘⑤ⱘ 42%DŽৃᰃ䆹䆒䅵Փ⫼њབϟ೒᠔⼎ⱘᓊᯊ ᮍ⊩ᴹخ໘⧚఼᥹ষⱘᯊᑣ˖ ೼䆹⬉䏃ⱘ䆒䅵ЁՓ⫼њ໻䞣ⱘ LCELLᴹѻ⫳ 100໮㒇⾦ⱘᓊᯊ 䖭ˈḋخⱘৢᵰᰃ㱑✊ᭈϾ⬉䏃ⱘ㾺থ఼ 䌘⑤াՓ⫼њ 42%ˈৃᰃ⫼ MaxplusII 䖯㸠ᏗሔᏗ㒓Ꮖ㒣ϡ㛑໳䗮䖛њDŽ㗠Ϩ៥ᗔ⭥㒣䖛䖭М໮䘏䕥ⱘᓊ ᯊৢ᠔ѻ⫳ⱘֵো䖬㛑ֱᣕॳᴹⱘᗻ㛑ϡ? 9 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ᔧ䳔㽕ᇍᶤϔֵো԰ϔ↉ᓊᯊᯊˈ߱ᄺ㗙ᕔᕔ೼ℸֵোৢІ᥹ϔѯ䴲䮼៪݊ᅗ䮼⬉䏃ˈℸᮍ⊩೼ߚ⾏ ⬉䏃Ёᰃৃ㸠ⱘDŽԚ೼ˢˬˣ˝Ёˈᓔথ䕃ӊ೼㓐ড়䆒䅵ᯊӮᇚ䖭ѯ䮼ᔧ԰ݫԭ䘏䕥এᥝˈ䖒ϡࠄᓊᯊⱘ ᬜᵰDŽ⫼ALTERA݀ৌⱘMaxplusIIᓔথˢˬˣ˝ᯊˈৃ ҹ䗮䖛ᦦܹϔѯ˨˟ˡ˨˨ॳ䇁ᴹѻ⫳ϔᅮⱘᓊᯊˈ Ԛ䖭ḋᔶ៤ⱘᓊᯊ೼ˢˬˣ˝㢃⠛Ёᑊϡ〇ᅮ Ӯˈ䱣⏽ᑺㄝ໪䚼⦃๗ⱘᬍব㗠ᬍব ಴ˈℸᑊϡᦤ׵䖭ḋخDŽ ೼ℸˈৃҹ⫼催乥ᯊ䩳ᴹ偅ࡼ⿏ԡᆘᄬ఼ˈᕙᓊᯊֵো԰᭄᥂䕧ܹˈᣝ᠔䳔ᓊᯊℷ⹂䆒㕂⿏ԡᆘᄬ఼ⱘ㑻 ᭄ˈ⿏ԡᆘᄬ఼ⱘ䕧ߎेЎᓊᯊৢⱘֵোDŽℸᮍ⊩ѻ⫳ⱘᓊᯊֵোϢॳֵো↨᳝䇃Ꮒˈ䇃Ꮒ໻ᇣ⬅催乥ᯊ 䩳ⱘ਼ᳳᴹއᅮDŽᇍѢ᭄᥂ֵোⱘᓊᯊˈ೼䕧ߎッ⫼᭄᥂ᯊ䩳ᇍᓊᯊৢֵো䞡ᮄ䞛ḋˈህৃҹ⍜䰸䇃ᏂDŽ ᇍѢ䖭ḋ໻ⱘᓊᯊ៥ᓎ䆂ⱘᅲ⦄ᮍ⊩ᰃ䞛⫼ᯊ䩳䫕ᄬᴹѻ⫳ᓊᯊⱘᮍ⊩ˈ៥Ӏⶹ䘧ᔧϔϾֵো⫼ᯊ䩳 䫕ᄬϔ⃵ˈᇚӮऴ⫼ϔϾ㾺থ఼䌘⑤ˈֵোӮ৥ৢ᥼⿏ϔϾᯊ䩳਼ᳳ˗䆹ৠџⱘ䆒䅵䞠 CPLD㢃⠛ℷད䖲 ᥹᳝ 32MHzⱘᯊ䩳 䙷ˈМ↣⫼ᯊ䩳䫕ᄬϔ⃵ sspֵোህӮ᥼⿏ 31ns 䖭ˈḋা䳔໮Փ⫼ 3Ͼ㾺থ఼䌘⑤ህৃ ҹ䖒ࠄⳂⱘњDŽ⬉䏃೒੠ӓⳳ⊶ᔶབϟ೒᠔⼎˖ᔧ✊䖭ḋخᇍॳᴹֵো催Ԣ⬉ᑇⱘᆑᑺӮ⿡᳝ᬍবˈԚা 㽕ᰃ೼Ϣ݊᥹ষⱘ㢃⠛ⱘᆍ䆌㣗ೈПݙህϡӮᕅડࠄࡳ㛑ⱘᅲ⦄DŽ ೒ ⫼Ѣᓊᯊⱘ⬉䏃೒ Ϟ೒ӓⳳ⊶ᔶ 2.3 བԩᦤ催㋏㒳ⱘ䖤㸠䗳ᑺ ৠℹ⬉䏃ⱘ䗳ᑺᰃᣛৠℹᯊ䩳ⱘ䗳ᑺDŽৠℹᯊ䩳ᛜᖿˈ⬉䏃໘⧚᭄᥂ⱘᯊ䯈䯈䱨䍞ⷁˈ⬉䏃೼ऩԡᯊ 䯈໘⧚ⱘ᭄᥂䞣ህᛜ໻. ៥Ӏܜᴹⳟϔⳟৠℹ⬉䏃Ё᭄᥂Ӵ䗦ⱘϔϾ෎ᴀ῵ൟˈབϟ೒˖ 10 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ˄Tcoᰃ㾺থ఼ᯊ䩳ࠄ᭄᥂䕧ߎⱘᓊᯊ˗Tdelayᰃ㒘ড়䘏䕥ⱘᓊᯊ˗Tsetupᰃ㾺থ఼ⱘᓎゟᯊ䯈˅ ؛䆒᭄᥂Ꮖ㒣㹿ᯊ䩳ⱘϞछ⊓ᠧܹ D㾺থ఼ˈ䙷М᭄᥂ࠄ䖒㄀ϔϾ㾺থ఼ⱘ Qッ䳔㽕 Tcoˈݡ㒣䖛㒘 ড়䘏䕥ⱘᓊᯊ Tdelayࠄ䖒ⱘ㄀ѠϾ㾺থ఼ⱘ Dッˈ㽕ᛇᯊ䩳㛑೼㄀ѠϾ㾺থ఼ݡ⃵㹿〇ᅮⱘ䫕ܹ㾺থ఼ˈ ߭ᯊ䩳ⱘᓊ䖳ϡ㛑ᰮѢ Tco+Tdelay+Tsetupˈ˄ ៥Ӏৃҹಲ乒ϔϟࠡ䴶䆆䖛ⱘᓎゟ੠ֱᣕᯊ䯈ⱘὖᗉˈህৃ ҹ⧚㾷ЎҔМ݀ᓣ᳔ৢ㽕ࡴϞϔϾ Tdelay˅ ⬅ҹϞߚᵤৃⶹ˖᳔ᇣᯊ䩳਼ᳳ˖T=Tco+Tdelay+Tsetup ᳔ ᖿᯊ䩳乥⥛ F= 1/T PLDᓔথ䕃ӊгℷᰃ䗮䖛䖭Ͼ݀ᓣᴹ䅵ㅫ㋏㒳䖤㸠䗳ᑺ Fmax ⊼˖೼䖭Ͼ䘏䕥೒Ё᳝Ͼখ᭄˖Tpd ,ेᯊ䩳ⱘᓊᯊখ᭄ˈ៥Ӏ೼߮ᠡخᯊ䯈ߚᵤⱘᯊ׭ˈ≵᳝ᦤ䖭Ͼ খ᭄ˈ˄བᵰՓ⫼ PLD ⱘܼሔᯊ䩳ൟোˈTpd ৃҹЎ 0ˈབᵰᰃ᱂䗮ᯊ䩳ˈ߭ϡЎ 0˅DŽ᠔ҹབᵰ㗗㰥ࠄ ᯊ䩳ⱘᓊᯊ ㊒ˈ⹂ⱘ݀ᓣᑨ䆹ᰃ T=Tco+Tdelay+Tsetup-TpdDŽᔧ✊ҹϞܼ䚼ߚᵤⱘ䛑ᰃ఼ӊݙ䚼ⱘ䖤㸠䗳ᑺˈ བᵰ㗗㰥㢃⠛ I/Oㅵ㛮ᓊᯊᇍ㋏㒳䗳ᑺⱘᕅડˈ䙷М䖬䳔㽕ࡴϔѯׂℷDŽ ⬅Ѣ TcoǃTsetup ᰃ⬅݋ԧⱘ఼ӊ੠Ꮉ㡎އᅮⱘˈ៥Ӏ䆒䅵⬉䏃ᯊাৃҹᬍব TdelayDŽ᠔ҹ㓽ⷁ㾺থ ఼䯈㒘ড়䘏䕥ⱘᓊᯊᰃᦤ催ৠℹ⬉䏃䗳ᑺⱘ݇䬂DŽ⬅Ѣϔ㠀ৠℹ⬉䏃䛑ϡℶϔ㑻䫕ᄬ˄བ೒ 3˅ˈ㗠㽕Փ ⬉䏃〇ᅮᎹ԰ˈᯊ䩳਼ᳳᖙ乏⒵䎇᳔໻ᓊᯊ㽕∖ˈ㓽ⷁ᳔䭓ᓊᯊ䏃ᕘˈᠡৃᦤ催⬉䏃ⱘᎹ԰乥⥛DŽ བ೒ 2 ᠔⼎˖៥Ӏৃҹᇚ䕗໻ⱘ㒘ড়䘏䕥ߚ㾷Ў䕗ᇣⱘ޴ഫˈЁ䯈ᦦܹ㾺থ఼ˈ䖭ḋৃҹᦤ催⬉䏃ⱘ Ꮉ԰乥⥛DŽ䖭гᰃ᠔䇧“⌕∈㒓”˄pipelining˅ᡔᴃⱘ෎ᴀॳ⧚DŽ ᇍѢ೒ 3 ⱘϞञ䚼ߚˈᅗᯊ䩳乥⥛ফࠊѢ㄀ѠϾ䕗໻ⱘ㒘ড়䘏䕥ⱘᓊᯊˈ䗮䖛䗖ᔧⱘᮍ⊩ᑇഛߚ䜡㒘 ড়䘏䕥ˈৃҹ䙓ܡ೼ϸϾ㾺থ఼П䯈ߎ⦄䖛໻ⱘᓊᯊˈ⍜䰸䗳ᑺ⫊乜DŽ 11 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � FPGA/CPLDᓔথ䕃ӊЁг᳝ϔѯখ᭄䆒㕂ˈ䗮䖛ׂᬍ䖭ѯ䆒㕂ˈৃҹᦤ催㓪䆥/ᏗሔᏗ㒓ৢ㋏㒳䗳ᑺˈ Ԛᰃḍ᥂㒣偠䖭⾡䗳ᑺⱘᦤ催ᰃᕜ᳝䰤ⱘ ˈ؛བᣝ✻㽕∖៥Ӏ䳔㽕䆒䅵ϔϾৃҹᎹ԰ࠄ 50MHzⱘ㋏㒳 ᅲˈ 䰙ᏗሔᏗ㒓఼᡹ਞߎᴹⱘ Fmax া᳝ 40MHzˈℸᯊབᵰ៥ӀՓ⫼ᏗሔᏗ㒓఼ⱘ䆒㕂䗝乍᳔໮ৃҹᦤ催ࠄ 45MHzˈ䖭䖬ᰃ䖤⇨↨䕗དⱘᚙމDŽ㗠ϨԴᖙ乏њ㾷䖭ѯ䗝乍ⱘ৿НǃՓ⫼㚠᱃ㄝDŽ ݊ᅲ೼ϔϾ䆒䅵䞠ᕅડ䗳ᑺⱘ⫊乜㒣ᐌাӮ᳝޴ᴵˈ៥Ӏᇚᓊᯊ᳔໻ⱘ䏃ᕘ⿄԰݇䬂䏃ᕘDŽᔧ䆒䅵ⱘ 䖤㸠䗳ᑺϡヺড়㋏㒳䆒䅵㽕∖ⱘᯊ׭៥Ӏৃҹ佪ܜᡒࠄϡ㛑⒵䎇㽕∖ⱘ݇䬂䏃ᕘˈᣝ✻Ϟ䗄ⱘᮍ⊩ᇚ݇䬂 䏃ᕘϞⱘ㒘ড়䘏䕥ᢚߚ៤໮ϾЁ䯈⫼㾺থ఼䱨ᓔˈ䖭ḋᕜᆍᯧህৃҹҢḍᴀϞᦤछ㋏㒳ⱘ䖤㸠䗳ᑺњDŽ ᳝ⱘ䆒䅵೼䆒䅵ᓔྟህⶹ䘧䙷䚼ߚ⬉䏃Ӯѻ⫳↨䕗໻ⱘ㒘ড়䘏䕥ˈᇐ㟈䗳ᑺ⫊乜ⱘѻ⫳ˈ䙷Мህᑨ䆹 ೼ᓔྟህᛇད㾷އࡲ⊩DŽ↨བ⦄೼䆒䅵䳔㽕ѻ⫳ϔϾ 32 ԡⱘࡴ⊩఼ˈᑊϨ㽕∖㛑໳Ꮉ԰೼ 50MHzDŽḍ᥂ 㒣偠Ⳉ᥹⫼ 32ԡࡴ⊩఼㚃ᅮᰃ䖒ϡࠄ 50MHzⱘ㽕∖ⱘˈ䖭ᯊ៥Ӏৃҹᇚ݊ߚ៤ 3Ͼ 12ԡ䅵఼᭄ᴹ᪡԰ˈ ৢ䴶ⱘ䅵఼᭄া㽕ᇚࠡ䴶䅵఼᭄㒧ᵰⱘ催ԡ˄䖯ԡԡ˅ⳌࡴህৃҹњDŽ ϟ䴶ᰃॳᴹ೼ᆑᏺ᥹ܹ᳡ࡵ఼䆒䅵Ёⱘ⌕䞣㒳䅵ऩܗЁⱘ 32ԡࡴ⊩఼ⱘᦣ䗄˖ ---------------------------------------------------------- ---- flow count element ---------------------------------------------------------- -----temporary computing 12 bits adder process(Count_0_en,count_buffer,Len,Carry_0_0,Carry_0_1) begin case Count_0_en is ---1st Step addition (10 downto 0) + (10 downto 0) when "001" => add_12_a_0 <= ('0' & count_buffer(0)(10 downto 0)); add_12_b_0 <= ('0' & Len(10 downto 0)); ---2nd Step addition (21 downto 11) + Carry_0_0 when "010" => add_12_a_0 <= ('0' & count_buffer(0)(21 downto 11)); add_12_b_0 <= ("00000000000" & Carry_0_0); ---3rd Step addition (31 downto 22) + Carry_0_1 when "100" => add_12_a_0 <= ("00" & count_buffer(0)(31 downto 22)); add_12_b_0 <= ("00000000000" & Carry_0_1); when others => add_12_a_0 <=˄others=>’X’˅; add_12_b_0 <=˄others=>’X’˅; end case; end process; ------12 bits adder add_12_result_0 <= add_12_a_0 + add_12_b_0; ------Bytes Count 12 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � process(RST,CLK_25MHz,IO,OE_bar,data_sel,Count_0_en) begin if(RST = '1')then -----system Reset count_buffer(0) <= (others => '0'); Carry_0_0 <= '0'; Carry_0_1 <= '0'; Carry_0_2 <= '0'; elsif(CLK_25MHz'event and CLK_25MHz = '0')then if(OE_bar = '0' and data_sel = '0')then count_buffer(0) <= IO; Carry_0_2 <= '0'; else case Count_0_en is ---1st Step addition (10 downto 0) + (10 downto 0) when "001" => count_buffer(0)(10 downto 0) <= add_12_result_0(10 downto 0); Carry_0_0 <= add_12_result_0(11);--first step carry ---2nd Step addition (21 downto 11) + Carry_0_0 when "010" => count_buffer(0)(21 downto 11) <= add_12_result_0(10 downto 0); Carry_0_1 <= add_12_result_0(11);--Second step carry ---3rd Step addition (31 downto 22) + Carry_0_1 when "100" => count_buffer(0)(31 downto 22) <= add_12_result_0(9 downto 0); Carry_0_2 <= add_12_result_0(10);--Third step carry when others => Carry_0_2 <= '0'; end case; end if; end if; end process; 2.4 ֵো䕧ߎ ᔧԴ䳔㽕ᇚ FPGA/CPLDݙ䚼ⱘֵো䗮䖛ㅵ㛮䕧ߎ㒭໪䚼Ⳍ఼݇ӊⱘᯊ׭ བˈᵰϡᕅડࡳ㛑᳔དᰃᇚ䖭 ѯֵো䗮䖛⫼ᯊ䩳䫕ᄬৢ䕧ߎDŽ಴Ў䗮ᐌᚙމϟϔϾᵓᄤᰃᎹ԰Ѣϔ⾡៪ϸ⾡ᯊ䩳῵ᓣϟ Ϣˈ FPGA/CPLD Ⳍ䖲᥹ⱘ㢃⠛ⱘᎹ԰ᯊ䩳໻໮᭄ᚙᔶϟϢ FPGA ⱘᯊ䩳ৠ⑤ˈབᵰ䕧ߎⱘֵো㒣䖛ᯊ䩳䫕ᄬৃҹ䍋ࠄབϟ ⱘ԰⫼˖ ! ᆍᯧ⒵䎇㢃⠛䯈ֵো䖲᥹ⱘᯊᑣ㽕∖˗ ! ᆍᯧ⒵䎇ֵোⱘᓎゟֱᣕᯊ䯈˗ � � &/. 6,* 6,*� 6,*� བϞ೒᠔⼎ˈ↨བ FPGA/CPLD೼ CLKⱘᯊ䩳⊓ 1䫕ᄬϔϾֵোᕫࠄ SIG᠔⼎ⱘ⊶ᔶ SˈIGֵো䳔㽕㒭঺ ໪ⱘϔϾϢ݊᥹ষⱘ㢃⠛ 䙷ˈМ䆹㢃⠛ᇚϔᅮӮ೼ CLKⱘᯊ䩳⊓ 2ℷ⹂䞛ḋࠄ SIGֵোDŽԚᰃབᵰ䆹ֵো ೼ FPGA/CPLDЁ䕧ߎⱘᯊ׭ϡᰃ⫼ᯊ䩳⊓䫕ᄬⱘˈ䙷ᇚ᳝ৃ㛑ߎ⦄ SIG1/SIG2᠔⼎ⱘᯊᑣ݇㋏ˈ߭Ϣ݊ ᥹ষⱘ㢃⠛೼ᯊ䩳⊓ 2໘䞛ḋ䆹ֵোⱘᯊ׭᳝ৃ㛑ߎ⦄ᓎゟֱᣕᯊ䯈ϡ⒵䎇㽕∖㗠ߎ⦄䞛ḋϡৃ䴴ǃ⊓ᠧ 13 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ⊓ㄝᚙމDŽ঺໪䗮䖛㒘ড়䘏䕥䕧ߎ䖬᳝ৃ㛑ߎ⦄↯ࠎⱘᚙމDŽ᠔᳝䖭ѯϡ㾘㣗ⱘ䆒䅵䛑Ӯᓩ䍋㋏㒳Ꮉ԰ᯊ ⱘϡৃ䴴ǃϡ〇ᅮⱘᚙᔶDŽ 2.5 ᆘᄬᓖℹ䕧ֵܹো ៥Ӏ೼᮹ᐌⱘ䆒䅵Ꮉ԰ЁˈFPGA/CPLDᘏᰃ㽕Ϣ߿ⱘ㢃⠛Ⳍ䖲᥹ⱘˈFPGA/CPLDӮ㒭߿ⱘ㢃⠛䕧ߎ ֵোˈৠᯊг㽕໘⧚߿ⱘ㢃⠛䗕ᴹⱘֵোˈ䖭ѯֵোᕔᕔᇍ FPGA/CPLD ݙ䚼ⱘᯊ䩳㋏㒳㗠㿔ᰃᓖℹⱘˈ Ўњৃ䴴ⱘ䞛ḋࠄ䖭ѯ䕧ֵܹোˈᓎ䆂ᇚ䖭ѯ䕧ֵܹোՓ⫼Ⳍᑨⱘᯊ䩳䫕ᄬৢ೼໘⧚ˈ䖭ḋخ˖ ! ᇚॳᴹⱘᓖℹֵো䕀࣪៤ৠℹᴹ໘⧚˗ ! এ䰸䕧ֵܹোЁⱘ↯ࠎ˄⡍߿ᰃᇍѢ᭄᥂ᘏ㒓˅˗ ೒ FPGA/CPLDЁֵোⱘ䕧ܹǃ䕧ߎ䫕ᄬ 2.6 FPGA/CPLDЁⱘᯊ䩳䆒䅵 ᮴≺ᰃ⫼⾏ᬷ䘏䕥ǃৃ㓪⿟䘏䕥ˈ䖬ᰃ⫼ܼᅮࠊ⸙఼ӊᅲ⦄ⱘӏԩ᭄ᄫ䆒䅵ˈЎњ៤ࡳഄ᪡԰ˈৃ䴴 ⱘᯊ䩳ᰃ䴲ᐌ݇䬂ⱘDŽ䆒䅵ϡ㡃ⱘᯊ䩳೼ᵕ䰤ⱘ⏽ᑺǃ⬉य़៪ࠊ䗴Ꮉ㡎ⱘأᏂᚙމϟᇚᇐ㟈䫭䇃ⱘ㸠Ўˈ ᑊϨ䇗䆩ೄ䲒ǃ㢅䫔ᕜ໻DŽ೼䆒䅵 FPGA/CPLD ᯊ䗮ᐌ䞛⫼޴⾡ᯊ䩳㉏ൟDŽᯊ䩳ৃߚЎབϟಯ⾡㉏ൟ˖ܼ ሔᯊ䩳ǃ䮼᥻ᯊ䩳ǃ໮㑻䘏䕥ᯊ䩳੠⊶ࡼᓣᯊ䩳DŽ໮ᯊ䩳㋏㒳㛑໳ࣙᣀϞ䗄ಯ⾡ᯊ䩳㉏ൟⱘӏᛣ㒘ড়DŽ ᮴䆎䞛⫼ԩ⾡ᮍᓣˈ⬉䏃Ёⳳᅲⱘᯊ䩳ᷥг᮴⊩䖒ࠄ؛ᅮⱘ⧚ᛇᯊ䩳ˈ಴ℸ៥Ӏᖙ乏ձ᥂⧚ᛇᯊ䩳ˈ ᓎゟϔϾᅲ䰙Ꮉ԰ᯊ䩳῵ൟᴹߚᵤ⬉䏃ˈ䖭ḋᠡৃҹՓᕫ⬉䏃ⱘᅲ䰙Ꮉ԰ᬜᵰ੠乘ᳳⱘϔḋDŽ೼ᅲ䰙ⱘᯊ 䩳῵ൟЁˈ៥Ӏ㽕㗗㰥ᯊ䩳ᷥӴ᪁Ёⱘأ᭰ǃ䏇ব੠㒱ᇍൖⳈⱘأᏂҹঞ݊ᅗϔѯϡ⹂ᅮ಴㋴DŽ 14 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ᇍѢᆘᄬ఼㗠㿔ˈᔧᯊ䩳Ꮉ԰⊓ࠄᴹᯊᅗⱘ᭄᥂ッᑨ䆹Ꮖ㒣〇ᅮˈ䖭ḋᠡ㛑ֱ䆕ᯊ䩳Ꮉ԰⊓䞛ḋࠄ᭄ ᥂ⱘℷ⹂ᗻˈ䖭↉᭄᥂ⱘ乘໛ᯊ䯈៥Ӏ⿄ПЎᓎゟᯊ䯈˄setup time DŽ˅᭄᥂ৠḋᑨ䆹೼ᯊ䩳Ꮉ԰⊓䖛এৢֱ ᣕϔ↉ᯊ䯈ˈ䖭↉ᯊ䯈⿄Ўֱᣕᯊ䯈˄hold time DŽ˅಴ℸ݋ԧⱘᯊ䩳བ೒ 5᠔⼎DŽ݊Ё㔥㒰ᓊ䖳ᰃᣛᯊ䩳ⱘ Ӵ᪁ᓊᯊҹঞ಴Ў䏇বϡൖⳈㄝᬜⱘأᏂ ೼ˈℸ෎⸔Ϟ㗗㰥ϔѯϡ⹂ᅮ಴㋴ᅲ䰙ⱘᎹ԰ᯊ䩳⊓བ೒Ё᠔⼎DŽ ֱᣕᯊ䯈˄hold˅੠ᓎゟᯊ䯈˄setup˅䛑ᰃⳌᇍѢᅲ䰙ᯊ䩳䏇ব㗠㿔ⱘDŽ಴ℸ೼⹂ᅮ⬉䏃ᯊᑣᯊˈᖙ乏㽕 㗗㰥ࠄ䖭ѯ಴㋴ˈՓᕫᓎゟᯊ䯈੠ֱᣕᯊ䯈ヺড়㽕∖DŽ hold setup ⧚ᛇ 䏇ব 㔥㒰 ᓊ䖳 ᅲ䰙ᯊ 䩳⊓ 㔥㒰 ᓊ䖳 ᅲ䰙ᯊ 䩳⊓ ⧚ᛇ 䏇ব 㔥㒰 ᓊ䖳 ᳝ᬜᎹ԰ऎ ೒ 5 Ꮉ԰ᯊ䩳῵ൟ ЎњՓ⬉䏃ℷᐌᎹ԰ˈᓎゟᯊ䯈੠ֱᣕᯊ䯈ᑨ䆹ߚ߿⒵䎇˖ min_logmin__ icQclockskewhold tttt ! skewsetupicQclockclock ttttt " max_logmax__ ݊Ёtclock_Q_maxᰃᯊ䩳⊓ব࣪ࠄ᭄᥂䕧ߎッব࣪ⱘ᳔᜶ব࣪ᚙމˈtlogic_maxᰃᆘᄬ఼䯈㒘ড়䘏䕥ⱘ᳔໻ৃ 㛑ᓊ䖳 tˈclock_Q_min੠tlogic_min㸼⼎᳔ᖿᚙމDŽ೼㗗㰥ᓎゟֱᣕᯊ䯈ᯊˈᑨ䆹㗗㰥ᯊ䩳ᷥ৥ৢأ᭰ⱘᚙމˈ೼㗗 㰥ᓎゟᯊ䯈ᯊᑨ䆹㗗㰥ᯊ䩳ᷥ৥ࠡأ᭰ⱘᚙމDŽ೼䖯㸠ৢӓⳳᯊˈ᳔໻ᓊ䖳⫼ᴹẔᶹᓎゟᯊ䯈ˈ᳔ᇣᓊᯊ ⫼ᴹẔᶹֱᣕᯊ䯈DŽ 2.6.1 ܼሔᯊ䩳 ᇍѢϔϾ䆒䅵乍Ⳃᴹ䇈ˈܼሔᯊ䩳(៪ৠℹᯊ䩳)ᰃ᳔ㅔऩ੠᳔ৃ乘⌟ⱘᯊ䩳DŽ೼ PLD/FPGA 䆒䅵Ё᳔ དⱘᯊ䩳ᮍḜᰃ˖⬅ϧ⫼ⱘܼሔᯊ䩳䕧ܹᓩ㛮偅ࡼⱘऩϾЏᯊ䩳এ䩳᥻䆒䅵乍ⳂЁⱘ↣ϔϾ㾺থ఼DŽা㽕 ৃ㛑ህᑨሑ䞣೼䆒䅵乍ⳂЁ䞛⫼ܼሔᯊ䩳DŽPLD/FPGA 䛑݋᳝ϧ䮼ⱘܼሔᯊ䩳ᓩ㛮ˈᅗⳈ᥹䖲ࠄ఼ӊЁⱘ ↣ϔϾᆘᄬ఼DŽ䖭⾡ܼሔᯊ䩳ᦤկ఼ӊЁ᳔ⷁⱘᯊ䩳ࠄ䕧ߎⱘᓊᯊDŽ ೒ 1 ⼎ߎܼሔᯊ䩳ⱘᅲ՟DŽ೒ 1 ᅮᯊ⊶ᔶ⼎ߎ㾺থ఼ⱘ᭄᥂䕧ܹ D[1..3]ᑨ䙉ᅜᓎゟᯊ䯈੠ֱᣕᯊ䯈ⱘ 㑺ᴳᴵӊDŽᓎゟ੠ֱᣕᯊ䯈ⱘ᭄ؐ೼ PLD᭄᥂᠟ݠЁ㒭ߎˈгৃ⫼䕃ӊⱘᅮᯊߚᵤ఼䅵ㅫߎᴹDŽབᵰ೼ᑨ ⫼Ёϡ㛑⒵䎇ᓎゟ੠ֱᣕᯊ䯈ⱘ㽕∖ˈ߭ᖙ乏⫼ᯊ䩳ৠℹ䕧ֵܹো(খⳟϟϔゴ“ᓖℹ䕧ܹ”)DŽ 15 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 1 ܼሔᯊ䩳 ˄᳔དⱘᮍ⊩ᰃ⫼ܼሔᯊ䩳ᓩ㛮এ䩳᥻ PLDݙⱘ↣ϔϾᆘᄬ఼ Ѣˈᰃ᭄᥂া㽕䙉ᅜⳌᇍᯊ䩳ⱘᓎゟᯊ䯈 tsu ੠ֱᣕᯊ䯈 th˅ 2.6.2 䮼᥻ᯊ䩳 ೼䆌໮ᑨ⫼ЁˈᭈϾ䆒䅵乍Ⳃ䛑䞛⫼໪䚼ⱘܼሔᯊ䩳ᰃϡৃ㛑៪ϡᅲ䰙ⱘDŽPLD݋᳝Ь⿃乍䘏䕥䰉߫ ᯊ䩳˄ेᯊ䩳ᰃ⬅䘏䕥ѻ⫳ⱘ˅ˈܕ䆌ӏᛣߑ᭄ऩ⣀ഄ䩳᥻৘Ͼ㾺থ఼DŽ✊㗠ˈᔧԴ⫼䰉߫ᯊ䩳ᯊˈᑨҨ 㒚ഄߚᵤᯊ䩳ߑ᭄ˈҹ䙓ܡ↯ࠎDŽ 䗮ᐌ⫼䰉߫ᯊ䩳ᵘ៤䮼᥻ᯊ䩳DŽ䮼᥻ᯊ䩳ᐌᐌৠᖂ໘⧚఼᥹ষ᳝݇ˈ⫼ഄഔ㒓এ᥻ࠊݭ㛝ކDŽ✊㗠ˈ↣ ᔧ⫼㒘ড়ߑ᭄䩳᥻㾺থ఼ᯊˈ䗮ᐌ䛑ᄬ೼ⴔ䮼᥻ᯊ䩳DŽབᵰヺড়ϟ䗄ᴵӊˈ䮼᥻ᯊ䩳ৃҹ䈵ܼሔᯊ䩳ϔḋ ৃ䴴ഄᎹ԰˖ 偅ࡼᯊ䩳ⱘ䘏䕥ᖙ乏াࣙ৿ϔϾ“Ϣ”䮼៪ϔϾ“៪”䮼DŽབᵰ䞛⫼ӏԩ䰘ࡴ䘏೼ᶤѯᎹ԰⢊ᗕϟˈ Ӯߎ⦄ゲѝѻ⫳ⱘ↯ࠎDŽ 䘏䕥䮼ⱘϔϾ䕧ܹ԰Ўᅲ䰙ⱘᯊ䩳ˈ㗠䆹䘏䕥䮼ⱘ᠔᳝݊ᅗ䕧ܹᖙ乏ᔧ៤ഄഔ៪᥻ࠊ㒓ˈᅗӀ䙉 ᅜⳌᇍѢᯊ䩳ⱘᓎゟ੠ֱᣕᯊ䯈ⱘ㑺ᴳDŽ ೒ 2੠೒ 3 ᰃৃ䴴ⱘ䮼᥻ᯊ䩳ⱘᅲ՟DŽ೼ ೒ 2 Ёˈ⫼ϔϾ“Ϣ”䮼ѻ⫳䮼᥻ᯊ䩳ˈ೼ ೒ 3 Ёˈ⫼ϔϾ“៪” 䮼ѻ⫳䮼᥻ᯊ䩳DŽ೼䖭ϸϾᅲ՟Ёˈᓩ㛮 nWR੠ nWE㗗㰥Ўᯊ䩳ᓩ㛮ˈᓩ㛮 ADD[oˊˊ3]ᰃഄഔᓩ㛮ˈ ϸϾ㾺থ఼ⱘ᭄᥂ᰃֵো D[1..n]㒣䱣ᴎ䘏䕥ѻ⫳ⱘDŽ 16 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 2 “Ϣ”䮼䮼᥻ᯊ䩳 � � ೒ 3 “៪”䮼䮼᥻ᯊ䩳 ೒ 2੠೒ 3 ⱘ⊶ᔶ೒ᰒ⼎ߎ᳝݇ⱘᓎゟᯊ䯈੠ֱᣕᯊ䯈ⱘ㽕∖DŽ䖭ϸϾ䆒䅵乍Ⳃⱘഄഔ㒓ᖙ乏೼ᯊ䩳ֱᣕ ᳝ᬜⱘᭈϾᳳ䯈ݙֱᣕ〇ᅮ(nWR੠ nWEᰃԢ⬉ᑇ᳝ᬜ)DŽབᵰഄഔ㒓೼㾘ᅮⱘᯊ䯈ݙ᳾ֱᣕ〇ᅮˈ߭ ೼ᯊ 䩳ϞӮߎ⦄↯ࠎˈ䗴៤㾺থ఼থ⫳䫭䇃ⱘ⢊ᗕব࣪DŽ঺ϔᮍ䴶ˈ᭄᥂ᓩ㛮 D[1ˊ nˊ]া㽕∖೼ nWR੠ nWE ⱘ᳝ᬜ䖍⊓໘⒵䎇ᷛޚⱘᓎゟ੠ֱᣕᯊ䯈ⱘ㾘ᅮDŽ ៥Ӏᕔᕔৃҹᇚ䮼᥻ᯊ䩳䕀ᤶ៤ܼሔᯊ䩳ҹᬍ୘䆒䅵乍Ⳃⱘৃ䴴ᗻDŽ೒ 4 ⼎ߎབԩ⫼ܼሔᯊ䩳䞡ᮄ䆒 䅵 ೒ 2 ⱘ⬉䏃DŽഄഔ㒓೼᥻ࠊ D㾺থ఼ⱘՓ㛑䕧ܹˈ䆌໮ PLD䆒䅵䕃ӊˈབ MAX+PLUSII䕃ӊ䛑ᦤկ 䖭⾡ᏺՓ㛑ッⱘ D㾺থ఼DŽᔧ ENAЎ催⬉ᑇᯊˈD䕧ܹッⱘؐ㹿䩳᥻ࠄ㾺থ఼Ё˖ᔧ ENAЎԢ⬉ᑇᯊˈ 㓈ᣕ⦄೼ⱘ⢊ᗕDŽ 17 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 4 “Ϣ”䮼䮼᥻ᯊ䩳䕀࣪៤ܼሔᯊ䩳 ೒ 4 Ё䞡ᮄ䆒䅵ⱘ⬉䏃ⱘᅮᯊ⊶ᔶ㸼ᯢഄഔ㒓ϡ䳔㽕೼ nWR ᳝ᬜⱘᭈϾᳳ䯈ݙֱᣕ〇ᅮ˗㗠া㽕∖ᅗӀ ੠᭄᥂ᓩ㛮ϔḋヺড়ৠḋⱘᓎゟ੠ֱᣕᯊ䯈ˈ䖭ḋᇍഄഔ㒓ⱘ㽕∖ህᇥᕜ໮DŽ ೒ 5㒭ߎϔϾϡৃ䴴ⱘ䮼᥻ᯊ䩳ⱘ՟ᄤDŽ3ԡৠℹࡴ⊩䅵఼᭄ⱘ RCO䕧ߎ⫼ᴹ䩳᥻㾺থ఼DŽ✊㗠ˈ䅵఼᭄ 㒭ߎⱘ໮Ͼ䕧ܹ䍋ࠄᯊ䩳ⱘ԰⫼ˈ䖭䖱ডњৃ䴴䮼᥻ᯊ䩳᠔䳔ⱘᴵӊПϔDŽ೼ѻ⫳ RCOֵোⱘ㾺থ఼Ёˈ ≵᳝ϔϾ㛑㗗㰥Ўᅲ䰙ⱘᯊ䩳㒓ˈ䖭ᰃ಴Ў᠔᳝㾺থ఼೼޴ТⳌৠⱘᯊࠏথ⫳㗏䕀DŽ㗠៥Ӏᑊϡ㛑ֱ䆕೼ PLD/FPGAݙ䚼 QA,QB,QCࠄ D㾺থ఼ⱘᏗ㒓䭓ⷁϔ㟈ˈ಴ℸˈབ ೒ 5 ⱘᯊ䯈⊶ᔶ᠔⼎ˈ೼఼Ң 3䅵ࠄ 4ᯊˈRCO㒓ϞӮߎ⦄↯ࠎ˄؛䆒 QCࠄ D㾺থ఼ⱘ䏃ᕘ䕗ⷁˈे QCⱘ䕧ߎܜ㗏䕀˅DŽ 18 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 5 ϡৃ䴴ⱘ䮼᥻ᯊ䩳 (ᅮᯊ⊶ᔶ⼎ߎ೼䅵఼᭄Ң 3ࠄ 4ᬍবᯊˈRCOֵোབԩߎ⦄↯ࠎⱘ) ೒ 6 㒭ߎϔ⾡ৃ䴴ⱘܼሔ䩳᥻ⱘ⬉䏃ˈᅗᰃ೒ 5 ϡৃ䴴䅵఼᭄⬉䏃ⱘᬍ䖯ˈRCO ᥻ࠊ D 㾺থ఼ⱘՓ㛑䕧 ܹDŽ䖭Ͼᬍ䖯ϡ䳔㽕๲ࡴ PLDⱘ䘏䕥ऩܗDŽ ೒ 6 ϡৃ䴴ⱘ 䮼᥻ᯊ䩳䕀ᤶЎܼሔᯊ䩳 2.6.3 ໮㑻䘏䕥ᯊ䩳 ᔧѻ⫳䮼᥻ᯊ䩳ⱘ㒘ড়䘏䕥䍙䖛ϔ㑻(े䍙䖛ऩϾⱘ“Ϣ”䮼៪“៪”䮼)ᯊ 䆕ˈ䆒䅵乍Ⳃⱘৃ䴴ᗻবᕫᕜೄ 䲒DŽेՓḋᴎ៪ӓⳳ㒧ᵰ≵᳝ᰒ⼎ߎ䴭ᗕ䰽䈵ˈԚᅲ䰙Ϟҡ✊ৃ㛑ᄬ೼ⴔॅ䰽DŽ䗮ᐌˈ៥Ӏϡᑨ䆹⫼໮㑻 㒘ড়䘏䕥এ䩳᥻ PLD䆒䅵Ёⱘ㾺থ఼DŽ ೒ 7 㒭ߎϔϾ৿᳝䰽䈵ⱘ໮㑻ᯊ䩳ⱘ՟ᄤDŽᯊ䩳ᰃ⬅ SELᓩ㛮᥻ࠊⱘ໮䏃䗝ᢽ఼䕧ߎⱘDŽ໮䏃䗝ᢽ఼ⱘ䕧 ܹᰃᯊ䩳(CLK)੠䆹ᯊ䩳ⱘ 2 ߚ乥(DIV2)DŽ⬅೒ 7 ⱘᅮᯊ⊶ᔶ೒ⳟߎˈ೼ϸϾᯊ䩳ഛЎ䘏䕥 1 ⱘᚙމϟˈ ᔧ SEL㒓ⱘ⢊ᗕᬍবᯊˈᄬ೼䴭ᗕ䰽䈵DŽ䰽䈵ⱘ⿟ᑺপއѢᎹ԰ⱘᴵӊDŽ ໮㑻䘏䕥ⱘ䰽䈵ᰃৃҹএ䰸ⱘDŽ ՟བˈԴৃҹᦦܹ“ݫԭ䘏䕥”ࠄ䆒䅵乍ⳂЁDŽ✊㗠ˈPLD/FPGA㓪䆥఼೼䘏䕥㓐ড়ᯊӮএᥝ䖭ѯݫԭ䘏䕥ˈ Փᕫ偠䆕䰽䈵ᰃ৺ⳳℷ㹿এ䰸বᕫೄ䲒њDŽЎℸˈᖙ乏ᑨᇏ∖݊ᅗᮍ⊩ᴹᅲ⦄⬉䏃ⱘࡳ㛑DŽ 19 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 7 ᳝䴭ᗕ䰽䈵ⱘ໮㑻ᯊ䩳 ೒ 8 㒭ߎ ೒ 7 ⬉䏃ⱘϔ⾡ऩ㑻ᯊ䩳ⱘ᳓ҷᮍḜDŽ೒Ё SELᓩ㛮੠ DIV2ֵো⫼ѢՓ㛑 D㾺থ఼ⱘՓ㛑䕧 ܹッˈ㗠ϡᰃ⫼Ѣ䆹㾺থ఼ⱘᯊ䩳ᓩ㛮DŽ䞛⫼䖭Ͼ⬉䏃ᑊϡ䳔㽕䰘ࡴ PLD ⱘ䘏䕥ऩܗˈᎹ԰ैৃ䴴໮ њDŽ ϡৠⱘ㋏㒳䳔㽕䞛⫼ϡৠⱘᮍ⊩এ䰸໮㑻ᯊ䩳ˈᑊ≵᳝೎ᅮⱘ῵ᓣDŽ � ೒ 7 ᮴䴭ᗕ䰽䈵ⱘ໮㑻ᯊ䩳 ˄䖭Ͼ⬉䏃䘏䕥ϞㄝᬜѢ೒ 7ˈԚैৃ䴴ⱘ໮˅� 2.6.4 㸠⊶ᯊ䩳 ঺ϔ⾡⌕㸠ⱘᯊ䩳⬉䏃ᰃ䞛⫼㸠⊶ᯊ䩳ˈेϔϾ㾺থ఼ⱘ䕧ߎ⫼԰঺ϔϾ㾺থ఼ⱘᯊ䩳䕧ܹDŽབᵰҨ 㒚ഄ䆒䅵ˈ㸠⊶ᯊ䩳ৃҹ䈵ܼሔᯊ䩳ϔḋഄৃ䴴Ꮉ԰DŽ✊㗠ˈ㸠⊶ᯊ䩳ՓᕫϢ⬉䏃᳝݇ⱘᅮᯊ䅵ㅫবᕫᕜ 20 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ໡ᴖDŽ㸠⊶ᯊ䩳೼㸠⊶䫒Ϟ৘㾺থ఼ⱘᯊ䩳П䯈ѻ⫳䕗໻ⱘᯊ䯈أ⿏ ᑊˈϨӮ䍙ߎ᳔ണᚙމϟⱘᓎゟᯊ䯈ǃ ֱᣕᯊ䯈੠⬉䏃Ёᯊ䩳ࠄ䕧ߎⱘᓊᯊˈՓ㋏㒳ⱘᅲ䰙䗳ᑺϟ䰡DŽ ⫼䅵᭄㗏䕀ൟ㾺থ఼ᵘ៤ᓖℹ䅵఼᭄ᯊᐌ䞛⫼㸠⊶ᯊ䩳ˈϔϾ㾺থ఼ⱘ䕧ߎ䩳᥻ϟϔϾ㾺থ఼ⱘ䕧ܹˈ খⳟ೒ 9 ৠℹ䅵఼᭄䗮ᐌᰃҷ᳓ᓖℹ䅵఼᭄ⱘ᳈དᮍḜˈ䖭ᰃ಴Ўϸ㗙䳔㽕ৠḋ໮ⱘᅣऩܗ㗠ৠℹ䅵᭄ ఼᳝䕗ᖿⱘᯊ䩳ࠄ䕧ߎⱘᯊ䯈DŽ೒ 10 㒭ߎ݋᳝ܼሔᯊ䩳ⱘৠℹ䅵఼᭄ˈᅗ੠ ೒ 9 ࡳ㛑Ⳍৠˈ⫼њৠḋ໮ ⱘ䘏䕥ऩܗᅲ⦄ˈै᳝䕗ᖿⱘᯊ䩳ࠄ䕧ߎⱘᯊ䯈DŽ޴Т᠔᳝ PLDᓔথ䕃ӊ䛑ᦤկ໮⾡໮ḋⱘৠℹ䅵఼᭄DŽ � ೒ 9 㸠⊶ᯊ䩳� ೒ 10 㸠⊶ᯊ䩳䕀ᤶ៤ܼሔᯊ䩳 (䖭Ͼ 3ԡ䅵఼᭄ᰃ೒ 9ᓖℹ䅵఼᭄ⱘ᳓ҷ⬉䏃 ᅗˈ⫼њৠḋⱘ 3Ͼᅣऩܗ Ԛˈ᳝᳈ⷁⱘᯊ䩳ࠄ䕧ߎⱘᓊᯊ) 2.6.5 ໮ᯊ䩳㋏㒳 䆌໮㋏㒳㽕∖೼ৠϔϾ PLDݙ䞛⫼໮ᯊ䩳DŽ᳔ᐌ㾕ⱘ՟ᄤᰃϸϾᓖℹᖂ໘⧚఼఼П䯈ⱘ᥹ষˈ៪ᖂ໘ ⧚఼੠ᓖℹ䗮ֵ䗮䘧ⱘ᥹ষDŽ⬅ѢϸϾᯊ䩳ֵোП䯈㽕∖ϔᅮⱘᓎゟ੠ֱᣕᯊ䯈ˈ᠔ҹˈϞ䗄ᑨ⫼ᓩ䖯њ 䰘ࡴⱘᅮᯊ㑺ᴳᴵӊDŽᅗӀгӮ㽕∖ᇚᶤѯᓖℹֵোৠℹ࣪DŽ ೒ 11 㒭ߎϔϾ໮ᯊ䩳㋏㒳ⱘᅲ՟DŽCLK_A⫼ҹ䩳᥻ REG_A CˈLK_B⫼Ѣ䩳᥻ REG_B ⬅ˈѢ REG_A 偅ࡼⴔ䖯ܹ REG_Bⱘ㒘ড়䘏䕥ˈᬙ CLK_AⱘϞछ⊓ⳌᇍѢ CLK_BⱘϞछ⊓᳝ᓎゟᯊ䯈੠ֱᣕᯊ䯈ⱘ㽕 ∖DŽ⬅Ѣ REG_Bϡ偅ࡼ作ࠄ REG_Aⱘ䘏䕥 CˈLK_BⱘϞछ⊓ⳌᇍѢ CLK_A≵᳝ᓎゟᯊ䯈ⱘ㽕∖DŽℸ໪ˈ ⬅Ѣᯊ䩳ⱘϟ䰡⊓ϡᕅડ㾺থ఼ⱘ⢊ᗕ ᠔ˈҹ CLK_A੠ CLK_Bⱘϟ䰡⊓П䯈≵᳝ᯊ䯈Ϟⱘ㽕∖DŽབ೒ 4ˈ 21 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 2 IˊI᠔⼎ˈ⬉䏃Ё᳝ϸϾ⣀ゟⱘᯊ䩳ˈৃᰃˈ೼ᅗӀП䯈ⱘᓎゟᯊ䯈੠ֱᣕᯊ䯈ⱘ㽕∖ᰃϡ㛑ֱ䆕ⱘDŽ೼ 䖭⾡ᚙމϟˈᖙ乏ᇚ⬉䏃ৠℹ࣪DŽ೒ 12 㒭ߎ REG_A ⱘؐ(བԩ೼Փ⫼ࠡ)ৠ CLK_B ৠℹ࣪DŽᮄⱘ㾺থ఼ REG_C⬅ GLK_B㾺᥻ˈֱ䆕 REG_Gⱘ䕧ߎヺড় REG_Bⱘᓎゟᯊ䯈DŽ✊㗠ˈ䖭Ͼᮍ⊩Փ䕧ߎᓊᯊњϔϾ ᯊ䩳਼ᳳDŽ ೒ ll ໮ᯊ䩳㋏㒳 (ᅮᯊ⊶ᔶ⼎ߎ CLK_AⱘϞछ⊓ⳌᇍѢ CLK_BⱘϞछ⊓᳝ᓎゟᯊ䯈੠ֱᣕᯊ䯈ⱘ㑺ᴳᴵӊ) � ೒ 12 ݋᳝ৠℹᆘᄬ఼䕧ߎⱘ໮ᯊ䩳㋏㒳 (བᵰ CLK_A੠ CLK_BᰃⳌѦ⣀ゟⱘˈ߭ REG—Aⱘ䕧ߎᖙ乏೼ᅗ作䗕ࠄ 1REG_BПࠡˈ⫼ REG_Cৠ ℹ࣪)� ೼䆌໮ᑨ⫼Ёাᇚᓖℹֵোৠℹ࣪䖬ᰃϡ໳ⱘˈᔧ㋏㒳Ё᳝ϸϾ៪ϸϾҹϞ䴲ৠ⑤ᯊ䩳ⱘᯊ׭ˈ᭄᥂ ⱘᓎゟ੠ֱᣕᯊ䯈ᕜ䲒ᕫࠄֱ䆕ˈ៥Ӏᇚ䴶Ј໡ᴖⱘᯊ䯈䯂乬DŽ᳔དⱘᮍ⊩ᰃᇚ᠔᳝䴲ৠ⑤ᯊ䩳ৠℹ࣪DŽ Փ⫼ PLDݙ䚼ⱘ䫕乍⦃˄PLL៪ DLL˅ᰃϔϾᬜᵰᕜདⱘᮍ⊩ˈԚϡᰃ᠔᳝ PLD䛑ᏺ᳝ PLLǃDLLˈ㗠 Ϩᏺ᳝ PLLࡳ㛑ⱘ㢃⠛໻໮ӋḐᯖ䌉ˈ᠔ҹ䰸䴲᳝⡍⅞㽕∖ˈϔ㠀എড়ৃҹϡՓ⫼ᏺ PLLⱘ PLDDŽ 䖭ᯊ ៥Ӏ䳔㽕Փ⫼ᏺՓ㛑ッⱘ D㾺থ఼ˈᑊᓩܹϔϾ催乥ᯊ䩳DŽ 22 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೒ 13 ϡৠ⑤ᯊ䩳 བ೒ 13᠔⼎ˈ㋏㒳᳝ϸϾϡৠ⑤ᯊ䩳ˈϔϾЎ 3MHzˈϔϾЎ 5MHzˈϡৠⱘ㾺থ఼Փ⫼ϡৠⱘᯊ䩳DŽЎ њ㋏㒳〇ᅮˈ៥ӀᓩܹϔϾ 20MHzᯊ䩳ˈᇚ 3M੠ 5Mᯊ䩳ৠℹ࣪ˈབ೒ 15᠔⼎DŽ 20Mⱘ催乥ᯊ䩳ᇚ԰ Ў㋏㒳ᯊ䩳ˈ䕧ܹࠄ᠔᳝㾺থ఼ⱘⱘᯊ䩳ッDŽ3M_EN ੠ 5M_EN ᇚ᥻ࠊ᠔᳝㾺থ఼ⱘՓ㛑ッDŽेॳᴹ᥹ 3Mᯊ䩳ⱘ㾺থ఼ˈ᥹ 20Mᯊ䩳ˈৠᯊ 3M_EN ᇚ᥻ࠊ䆹㾺থ఼Փ㛑 ˈॳ᥹ 5Mᯊ䩳ⱘ㾺থ఼ˈг᥹ 20M ᯊ䩳ˈৠᯊ 5M_EN ᇚ᥻ࠊ䆹㾺থ఼Փ㛑DŽ 䖭ḋ៥Ӏህৃҹᇚӏԩ䴲ৠ⑤ᯊ䩳ৠℹ࣪DŽ ೒ 13 ৠℹ࣪ӏᛣ䴲ৠ⑤ᯊ䩳 ˄ϔϾ DFF੠ৢ䴶䴲䮼ˈϢ䮼ᵘ៤ᯊ䩳Ϟछ⊓Ẕ⌟⬉䏃˅ ঺໪ˈᓖℹֵো䕧ܹᘏᰃ᮴⊩⒵䎇᭄᥂ⱘᓎゟֱᣕᯊ䯈ˈᆍᯧՓ㋏㒳䖯ܹѮ〇ᗕˈ᠔ҹгᓎ䆂䆒䅵㗙 ᡞ᠔᳝ᓖℹ䕧ܹ䛑ܜ㒣䖛ঠ㾺থ఼䖯㸠ৠℹ࣪. � ᇣ㒧˖〇ᅮৃ䴴ⱘᯊ䩳ᰃ㋏㒳〇ᅮৃ䴴ⱘ䞡㽕ᴵӊˈ៥Ӏϡ㛑໳ᇚӏԩৃ㛑৿᳝↯ࠎⱘ䕧ߎ԰Ўᯊ䩳 ֵোˈᑊϨሑৃ㛑াՓ⫼ϔϾܼሔᯊ䩳ˈᇍ໮ᯊ䩳㋏㒳㽕⊼ᛣৠℹᓖℹֵো੠䴲ৠ⑤ᯊ䩳DŽ 2.6.6 ໮ᯊ䩳㋏㒳䆒䅵ⱘϔѯᮍ⊩˖ བᵰᯊ䩳䯈ᄬ೼ⴔ೎ᅮⱘ乥⥛ס᭄ˈ䖭⾡ᚙމϟᅗӀⱘⳌԡϔ㠀݋᳝೎ᅮ݇㋏ˈৃҹ䞛⫼ϟ䗄ᮍ⊩໘⧚˗ Փ⫼催乥ᯊ䩳԰ЎᎹ԰ᯊ䩳ˈՓ⫼Ԣ乥ᯊ䩳԰ЎՓ㛑ֵোˈᔧࡳ㗫ϡ԰Ў佪㽕಴㋴ᯊᓎ䆂Փ⫼䖭 ⾡ᮍᓣ˗ 23 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ೼Ҩ㒚ߚᵤᯊᑣⱘ෎⸔Ϟᦣ䗄ϸϾᯊ䩳䕀ᤶ໘ⱘ⬉䏃˗ བᵰ⬉䏃Ёᄬ೼ϸϾϡৠ乥⥛ⱘᯊ䩳ˈᑊϨ乥⥛᮴݇ˈৃҹ䞛⫼བϟㄪ⬹˖ ߽⫼催乥ᯊ䩳䞛ḋϸϾᯊ䩳ˈ೼⬉䏃ЁՓ⫼催乥ᯊ䩳԰Ў⬉䏃ⱘᎹ԰ᯊ䩳ˈ㒣䞛ḋৢⱘԢ乥ᯊ䩳 ԰ЎՓ㛑˗ ೼ᯊ䩳ৠℹऩܗЁ䞛⫼ϸ⃵ৠℹ⊩ Փ⫼ᦵ᠟ֵো Փ⫼ঠᯊ䩳 FIFO䖯㸠᭄᥂㓧ކ ᯊ䩳ৠℹ࣪ བˈᵰ㋏㒳Ёᄬ೼ϸϾᯊ䩳 clk_a੠ clk_b,䆒䅵㗙ৃҹՓ⫼乥⥛催Ѣ max(clk_a,clk_b)ϸסⱘ ᯊ䩳ᴹ԰Ў䞛ḋᯊ䩳ˈϸϾԢ乥ᯊ䩳㒣䖛໘⧚ৢৃҹ԰Ў㾺থ఼ⱘՓ㛑ֵোˈ䞛⫼䖭⾡ᮍḜⱘད໘ᰃᭈϾ ⬉䏃䞛⫼ऩᯊ䩳Ꮉ԰ˈԚ䳔㽕ϔϾ乱໪ⱘ催乥ᯊ䩳ˈᔧ⬉䏃᳝ࡳ㗫㽕∖ᯊˈ䆒䅵㗙ᑨ䆹Ҩ㒚㗗㰥˗ Փ⫼ 20M䞛ḋ 3M੠ 5M,syn_5M԰Ўॳᴹ 5Mֵো偅ࡼᆘᄬ఼ⱘՓ㛑ֵো˗ ೒ Փ⫼催乥ᯊ䩳䞛ḋ 2ϾԢ乥ᯊ䩳ॳ⧚೒ ೒ Փ⫼催乥ᯊ䩳䞛ḋ 2ϾԢ乥ᯊ䩳⊶ᔶ೒ ೼ᵘӊ⬅ϸϾϡৠ㋏㒳ᯊ䩳᥻ࠊᎹ԰ⱘ῵ഫП䯈ⱘৠℹ῵ഫᯊˈᑨ䆹䙉ᅜϟ䴶ॳ߭˖ϸϾ䞛⫼ϡৠᯊ 䩳Ꮉ԰ⱘᆘᄬ఼П䯈ϡᑨ䆹ݡߎ⦄䘏䕥⬉䏃ˈ㗠ᑨ䆹ҙҙᰃϔ⾡䖲᥹݇㋏ˈ݋ԧབϟ೒᠔⼎ˈ䖭⾡ᮍ⊩᳝ ߽Ѣ᥻ࠊᓎゟֱᣕᯊ䯈ⱘ⒵䎇DŽ ᦵ᠟ֵোᴎࠊᰃᓖℹ㋏㒳П䯈䗮ֵⱘ෎ᴀᮍᓣˈ៥Ӏ೼໘⧚ϡৠᯊ䩳П䯈ⱘ᥹ষᯊˈгৃҹ䞛⫼䖭⾡ ᮍᓣˈԚ䳔㽕⊼ᛣⱘᰃ䆒䅵㗙ᑨ䆹Ҩ㒚ߚᵤᦵ᠟੠ᑨㄨֵো᳝ᬜᣕ㓁ⱘᯊ䯈ˈ⹂ֱ䞛ḋ᭄᥂ⱘℷ⹂ᗻDŽ Ⳃࠡ৘⾡఼ӊЁᦤկⱘঠᯊ䩳 FIFOᅣऩܗᕜདⱘᦤկњᇍᓖℹঠᯊ䩳ⱘ䆓䯂 ऩˈܗⱘݙ䚼᳝ण䇗ϸϾ ᯊ䩳ⱘ⬉䏃ˈ⹂ֱ䇏ݭⱘℷ⹂ᗻDŽৃҹ߽⫼䖭Ͼ఼ӊᅠ៤᭄᥂ⱘৠℹDŽ 1. 䞛⫼ܼሔᯊ䩳ˈϡ㽕ᇚᯊ䩳খϢ䖤ㅫDŽ㋏㒳ᦤկϔᅮ᭄䞣ⱘܼሔᯊ䩳㒓ˈ೼ᏗሔᏗ㒓ᯊˈሑ䞣⒵䎇䖭 ѯֵোⱘ㽕∖ҹޣᇣᯊ䩳أ⿏੠ؒ᭰DŽབᵰᯊᑣᅝᥦϡড়⧚Փ⫼њ䕗໮ gated clockˈ䙷М䖭ѯᯊ䩳ⱘ 24 '1("�$1-%໢਎ᖂ℡ῆᾫ᧌❶� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � أ᭰ህӮ䕗໻ˈϡ㛑ֱ䱰ᓎゟᯊ䯈੠ֱᣕᯊ䯈ˈᇐ㟈⬉䏃Ꮉ԰乥⥛䰡Ԣ៪᮴⊩Ꮉ԰DŽ 2. ҹᆘ