74HC138

DATA SHEET Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines September 1993 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Active LOW mutually exclusive outputs • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The “138” features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter. The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The ”138” is identical to the “238” but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT propagation delay CL = 15 pF; VCC = 5 V tPHL/ tPLH An to Yn 12 17 ns tPHL/ tPLH E3 to Yn En to Yn 14 19 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 67 67 pF September 1993 3 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 A0 to A2 address inputs 4, 5 E1, E2 enable inputs (active LOW) 6 E3 enable input (active HIGH) 8 GND ground (0 V) 15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7 outputs (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage MLB312 A0 A1 A2 1 2 3 15 13 11 7 9 10 12 14 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 4 5 6 E1 E2 E3 Fig.3 IEC logic symbol. (a) (b) Fig.4 Functional diagram. September 1993 4 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care INPUTS OUTPUTS E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H X X X H X X X L X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H L L L L L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L Fig.5 Logic diagram. September 1993 5 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay An to Yn 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay E3 to Yn 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay En to Yn 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 September 1993 6 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF INPUT UNIT LOAD COEFFICIENT An 1.50 En 1.25 E3 1.00 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay An to Yn 20 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay E3 to Yn 18 40 50 60 ns 4.5 Fig.6 tPHL/ tPLH propagation delay En to Yn 19 40 50 60 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 September 1993 7 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.