CD74HC42

1 Data sheet acquired from Harris Semiconductor SCHS133A Features • Buffered Inputs and Outputs • Typical Propagation Delay: 12ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il £ 1m A at VOL, VOH Description The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL decoders with the low power consumption of standard CMOS integrated circuits. These devices have the capability of driving 10 LSTLL loads and are compatible with the standard LS logic family. One of ten outputs (low on select) is selected in accordance with the BCD input. Non-valid BCD inputs result in none of the outputs being selected (all outputs are high). Pinout CD54HC42 (CERDIP) CD74HC42, CD74HCT42 (PDIP, SOIC) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC42F3A -55 to 125 16 Ld CERDIP CD74HC42E -55 to 125 16 Ld SOIC CD74HC42M -55 to 125 16 Ld SOIC CD74HCT42E -55 to 125 16 Ld PDIP NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or cus- tomer service for ordering information. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 Y0 Y1 Y2 Y3 Y4 Y5 GND Y6 VCC A1 A2 A3 Y9 Y8 Y7 A0 August 1997 - Revised May 2000 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2000 Texas Instruments Incorporated. CD54/74HC42, CD74HCT42 High Speed CMOS Logic BCD To Decimal Decoder (1 of 10) [ /Title (CD74H C42, CD74H CT42) /Subject (High Speed CMOS Logic BCD To Deci- 2 Functional Diagram TRUTH TABLE INPUTS OUTPUTS A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 L L L L L H H H H H H H H H L L L H H L H H H H H H H H L L H L H H L H H H H H H H L L H H H H H L H H H H H H L H L L H H H H L H H H H H L H L H H H H H H L H H H H L H H L H H H H H H L H H H L H H H H H H H H H H L H H H L L L H H H H H H H H L H H L L H H H H H H H H H H L H L H L H H H H H H H H H H H L H H H H H H H H H H H H H H L L H H H H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H NOTE: H = High Voltage Level, L = Low Voltage Level Y0 Y1 Y2 Y3 Y5 Y7 Y9 Y8 Y6 Y4 11 10 1 2 3 4 5 6 7 9 15 14 13 12 A0 A1 A2 A3 CD54/74HC42, CD74HCT42 3 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . . – 20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . – 20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . – 25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . . – 50mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) Thermal Resistance (Typical, Note 3) q JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. q JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSVI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output Voltage TTL Loads - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output Voltage CMOS Loads VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage Current II VCC or GND - 6 - - – 0.1 - – 1 - – 1 m A Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 m A CD54/74HC42, CD74HCT42 4 HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V High Level Output Voltage TTL Loads -4 4.5 3.98 - - 3.84 - 3.7 - V Low Level Output Voltage CMOS Loads VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads 4 4.5 - - 0.26 - 0.33 - 0.4 V Input Leakage Current II VCC and GND 0 5.5 - – 0.1 - – 1 - – 1 m A Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 m A Additional Quiescent Device Current Per Input Pin: 1 Unit Load D ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m A NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. DC Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSVI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS All 1 NOTE: Unit Load is D ICC limit specified in DC Electrical Table, e.g. 360m A max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay, Input to Y (Figure 1) tPLH, tPHL CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns 6 - - 26 - 33 - 38 ns Any Input to Y tPLH, tPHL CL = 15pF 5 - 12 - - - - - ns Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CIN - - - - 10 - 10 - 10 pF CD54/74HC42, CD74HCT42 5 Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 65 - - - - - pF HCT TYPES Propagation Delay, Input to Y (Figure 2) tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns Any Input to Y tPLH, tPHL CL = 15pF 5 - 14 - - - - - ns Output Transition Time (Figure 2) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CIN - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 70 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per package. 5. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Switching Specifications Input tr, tf = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX Test Circuits and Waveforms FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPHL tPLH tTHL tTLH 90% 50% 10% 50% 10%INVERTING OUTPUT INPUT GND VCC tr = 6ns tf = 6ns 90% tPHL tPLH tTHL tTLH 2.7V 1.3V 0.3V 1.3V 10%INVERTING OUTPUT INPUT GND 3V tr = 6ns tf = 6ns 90% CD54/74HC42, CD74HCT42