使用MATLAB和Simulink设计高级通信系统

5/27/2010 1 1 使用 使用使用 使用MATLAB和 和和 和Simulink 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 高级通信系统 设计高级通信系统设计高级通信系统 设计高级通信系统 2010年 年年 年6月 月月 月 中国 中国中国 中国 2 ® ® 请将手机关闭或调整为静音状态 会议即将开始 会议即将开始会议即将开始 会议即将开始 5/27/2010 2 3 ® ® 会议日程 会议日程会议日程 会议日程 上午课程 9:00 a.m. 致欢迎辞和公司介绍 9:05 a.m. 通信系统的可执行 规范 编程规范下载gsp规范下载钢格栅规范下载警徽规范下载建设厅规范下载 9:45 a.m. 特定的通信系统的设计 10:30a.m. 茶歇 10:45 a.m. 设计实现和验证（包括定点调试/自动代码生成/软件协同仿真/硬件原型等） 11:30 a.m. Q&A 下午课程- Hands-on Workshop (只针对MATLAB正版 license用户，并有名额限制) 1:15 p.m. 检查电脑的MATLAB运行环境 1:30 p.m. Simulink基础建模 1:50 p.m. QPSK建模和BER验证 2:30 p.m. 接收机同步 –载波同步，定时和帧同步 3:30 p.m. OFDM同步 4:30 p.m. • 信号的可视化处理 • Simulink模型的调试 5:00 p.m. 结束 4 MathWorks公司 公司公司 公司 � 公司总部 公司总部公司总部 公司总部: 美国马萨诸塞州Natick市, � 美国办事处 美国办事处美国办事处 美国办事处: 加州/密歇根州/华盛顿/德州 � 欧洲区分公司 欧洲区分公司欧洲区分公司 欧洲区分公司: 英国/法国/德国/瑞士/意大利 西班牙/荷兰/瑞典 � 亚太区分公司 亚太区分公司亚太区分公司 亚太区分公司: 中国/韩国/澳大利亚/日本/印度 � 全球 全球全球 全球25国家及地区设有代理商和分销商 国家及地区设有代理商和分销商国家及地区设有代理商和分销商 国家及地区设有代理商和分销商 Earth’s topography on an equidistant cylindrical projection, created with MATLAB® and Mapping Toolbox™. MathWorks Office 代理商 Office 5/27/2010 3 5 � 2008年收入以超过 $500M � 1984年创建 � 全球超过 2,200 员工 � 百万级的正版用户数量覆盖超过全球的 175个国家及地区 1985 1990 1995 2000 2005 MathWorks Today 6 主要行业应用 主要行业应用主要行业应用 主要行业应用 � 航天航空 � 汽车 � 通信 � 电子 � 半导体 � 教育 � 电力和能源 � 工业自动化和机械 � 金融服务 � 生物科学和制药 � 化学和石油 5/27/2010 4 7 MathWorks 核心产品 核心产品核心产品 核心产品 科学计算标准平台 – 数值计算 – 数据 分析 定性数据统计分析pdf销售业绩分析模板建筑结构震害分析销售进度分析表京东商城竞争战略分析 与可视化 – 从事算法开发的高级编程语言 – 丰富的工具箱:信号处理,图像处理,统 计，优化，符号数学等多个领域 – 是MathWorks其他家族产品的基础 8 MathWorks 核心产品 核心产品核心产品 核心产品 建模,仿真,嵌入式系统实现的标准平台 – 线性, 非线性,离散, 连续,混合,及多速率 系统建模仿真 – 是基于模型设计(Model-Based Design) 基础, 包括多域物理建模, 自动代码生成, 和验证与确认 – 开发的架构,可与由其他工具创建的模 型集成 – 多领域的应用: 控制,信号处理,通讯,及 其它系统 工程 路基工程安全技术交底工程项目施工成本控制工程量增项单年度零星工程技术标正投影法基本原理 领域 5/27/2010 5 9 会议日程 会议日程会议日程 会议日程 � 介绍 � 通信系统的可执行规范 通信系统的可执行规范通信系统的可执行规范 通信系统的可执行规范 � 特定的通信系统的设计 � 设计实现和验证 � 后续工作 10 ® ® Fires, Beacons, Smoke Signals Carrier Pigeon Telegraph 5/27/2010 6 11 ® ® 1980s 1990s Today and Beyond * Gordon Gekko – Wall Street, 1987 12 ® ® Communications Systems Design Challenges What if we could… Fast Changing Standards Do Faster Design Iterations o Rich libraries of pre-built blocks for multiple domains & applications o Rapid system construction and faster simulations High Data-Rate Transceivers Have Reusable and Reconfigurable Designs o OFDM, MIMO within 802.16e, 802.20m, 802.11n, LTE- advanced o Receiver Synchronization, Symbol/Timing Recovery, Equalizers o Multi-Rate, Feedback, State Machines System Complexity Use Integrated Design and Simulation Platform o Incorporate RF, baseband, and control logic components o Include and co-simulate analog, mixed-signal, and digital designs o Reuse intellectual property in C, MATLAB, HDL 5/27/2010 7 13 ® ® Demo: Model-Based Design Workflow **About the design: Bandlimited audio input (250-3250 Hz) is translated by it’s approximate center freq (1600 Hz) and filtered to create a complex baseband spectrum centered at DC. This complex spectrum is then translated to the desired RF output frequency and re-combined to create a real (bandpass) signal. Weaver’s “Third Method” of SSB Generator TX 14 ® ® Model-Based Design for Communication Systems Radio Hardware IMPLEMENTATION DESIGN T E S T & V E R IF IC A T IO N RESEARCH REQUIREMENTS Baseband PHY Layer VHDL, Verilog MCU DSP FPGA ASIC C, C++ RF IMPLEMENTATION RX Sync OFDM/ OFDMA DPD Fixed Point The process we followed: Collect Requirements and Define Specifications o Collected requirements like audio signal bandwidth, RF carrier frequency, etc o Created Simulink executable model, simulated behavioral model to verify against specs Design Elaboration and Prototyping o Elaborated and prototyped model to include additional details such as filter designs, AGC, polyphase filters, interp/decim, ddc, duc and RF o Added implementation details such as fixed-point conversion, partition the model to match HW architecture Implementation o Generated target specific C and HDL code with automatic code generation and co-simulation capabilities Continuous Verification o Verify against requirements during every stage of the process Radio Hardware RESEARCH REQUIREMENTS Baseband PHY Layer RF RX Sync OFDM/ OFDMA DPD Fixed Point VHDL, Verilog MCU DSP FPGA ASIC C, C++ T E S T & V E R IF IC A T IO N 5/27/2010 8 15 ® ® AT4 Develop test systems for LTE wireless equipment “Our physical layer model in MATLAB and Simulink enabled us to better understand the LTE specifications, and Model-Based Design enabled us to verify that our FPGA implementation conformed to those specifications.” BridgeWave Communications Deliver high-capacity data links for wireless backhaul ”MathWorks tools enabled us to evaluate different design approaches and parameters, verify the design, and then examine the details of our implementation. We tested and simulated all aspects of the system before building a hardware prototype.” ETRI Develop and prove a complex 4G communications design “The intuitive block diagram environment of Simulink enabled us to implement our base station system design precisely and ensure optimal synchronous performance.” Communications Design Successes 16 ® ® Executable Specifications of Communications System Radio Hardware IMPLEMENTATION DESIGN T E S T & V E R IF IC A T IO N RESEARCH REQUIREMENTS Baseband PHY Layer VHDL, Verilog MCU DSP FPGA ASIC C, C++ RF RX Sync OFDM/ OFDMA DPD Fixed Point Our Goal � Quickly construct a functional baseline executable model from specification � Verify the design against requirements � Interact with design and rapidly iterate and prototype the design � Run fast simulations 5/27/2010 9 17 ® ® QPSK Transceiver from Specification Modulation: QPSK Constellation: Gray Code Data Rate: 1Mbps RRCOS Filter Group Delay: 3 Rolloff = .25; UpsampleFactor: 8 Verify System with AWGN Channel 18 ® ® Verify Design: AWGN Channel, BER Analysis and BERTool BERTool 5/27/2010 10 19 ® ® Demo: Speeding Up Simulation Modeling Tip Simulation Time Speed Up Factor Baseline 30 seconds N/A GraphicsDisabled 3.7 seconds 8.1 Frame Based 3.3 seconds 0.12 Simulink Accelerator 0.1 seconds 33 TOTAL SPEED UP 300X Simple techniques to try: 20 ® ® Low Bit Error Rate and Other Intensive Computations Don’t let graphics be the bottleneck � Turn off scopes after you have debugged the model Use frame-based processing � Frames are sequences of samples, grouped together for efficient execution Use Simulink Accelerator � Additional optimizations are performed during initialization Use parallel computing (“server farm”) � Use PCT to distribute tasks on multi-core processes � Use MDCS to distribute tasks on computing cluster 5/27/2010 11 21 ® ® Task Parallel Applications Time Time Task 1 Task 2 Task 3 Task 4Task 1 Task 2 Task 3 Task 4 TOOLBOXES BLOCKSETS Worker Worker Worker Worker 22 ® ® Parallel Computing with MATLAB � Implicit Multithreaded MATLAB � Built-in Toolbox Support: Optimization Toolbox Genetic Algorithm and Direct Search Bioinformatics Toolbox Model Calibration Toolbox SystemTest Simulink Design Optimization � parfor � job and tasks No code changes Replace for loop Some code changes Task Parallel 5/27/2010 12 23 ® ® Parallel Computing with MATLAB and Simulink 24 ® ® Large Datasets (Data Parallel) 1111 26 41 1212 27 42 1313 28 43 1414 29 44 1515 30 45 1616 31 46 1717 32 47 1717 33 48 1919 34 49 2020 35 50 2121 36 51 2222 37 52 TOOLBOXES BLOCKSETS 1111 26 4141 1212 27 4242 1313 28 4343 1414 29 4444 1515 30 4545 1616 31 4646 1717 32 4747 1717 33 4848 1919 34 4949 2020 35 5050 2121 36 5151 2222 37 5252 5/27/2010 13 25 ® ® IEEE 802.11a System 26 ® ® Summary: Executable Specifications of Communications System � Quickly constructed a functional baseline executable model by using libraries of pre-defined communications algorithms � Verified the designs per specifications using qualitative methods (Scatter plots, spectrum scopes, eye diagrams) and quantitative methods (BER, SNR, etc) � Rapidly iterated and prototyped the design with interactive, tunable executable model and advanced visualizations � Increased simulation speed through options such as frame based processing, Simulink Accelerator and parallel computing 5/27/2010 14 27 会议日程 会议日程会议日程 会议日程 � 介绍 � 通信系统的可执行规范 � 特定的通信系统的设计 特定的通信系统的设计特定的通信系统的设计 特定的通信系统的设计 � 设计实现和验证 � 后续工作 28 Advanced Communication System Designs Radio Hardware IMPLEMENTATION DESIGN T E S T & V E R IF IC A T IO N RESEARCH REQUIREMENTS Baseband PHY Layer VHDL, Verilog MCU DSP FPGA ASIC C, C++ RF RX Sync OFDM/ OFDMA DPD MAC Layer Designs that typically require domain expertise • RF • Receiver Synchronization • OFDM/OFDMA • Digital Pre-Distortion • Fixed Point • MAC Layer Control • Mixed Signal 5/27/2010 15 29 How to Bridge the Gap Between Engineers Who Speak Different Languages? Huh? BER Amplitude@nominal 1ΩΩΩΩ Eb/N0 Intersymbol interference Delay spread RF 30 How to Bridge the Gap Between Engineers Who Speak Different Languages? Noise figure Power@50ΩΩΩΩ IP3 S-parameters Huh? 5/27/2010 16 31 Share RF behavior between RF engineer and Communication System engineer � RF Toolbox “Design and analyze networks of RF components” “Here’s the verification model” “Here’s the specs” � RF Blockset “Design and simulate the behavior of RF systems and components in a wireless system” 32 RF Blockset Key Features “Design and simulate the behavior of RF systems and components in a wireless system” � Fast, baseband-complex, time-domain modeling – Compatible with Simulink modeling paradigm � High fidelity simulation with measured network parameter data files � Cascade components with RF connection lines: – Network parameters and noise figure of: � Filters, Transmission lines, Linear and non- linear amplifiers, Linear and non-linear mixers � Visualize frequency response with rectangular and polar plots and Smith charts 5/27/2010 17 33 Example: IEEE 802.11a System Demo >> wlan_eml_rf 34 Voice of Customers: Challenges in Receiver Design and Simulation � Modeling decoupled clocks/logic in transmitter and receiver “We need asynchronous models because nodes are running on their own clocks. We need a system-level model to produce asynchronous clocks for the transmitter and receiver models.” “Even with one transmit-receive link, you have asynchronous clocks. In wireless, with multiple users, you have hundreds of them.” � Designing and simulating receiver synchronization algorithms “One of the biggest challenges of radio design is that the receiver and transmitter are not synchronized.” “Major problem of radio design is synchronization.” “We need models and examples for users.” RX Sync 5/27/2010 18 35 Receiver Synchronization Path Delay: 4 µs Doppler Shift: 150 Hz Preamble Data Symbols Modulator DAC Radio Transmitter (Tx) Data Symbols ADC RadioDemodulator Synchronization Receiver (Rx) Detect preamble to find start of data frame Tx Carrier: 2440.03 MHz Rx LO: 2439.98 MHz DAC: 8.0001 MHz ADC: 7.9999 MHz 36 Synchronization Carrier Synchronization ej(∆w0*n - θ) arg(·) Phase Detector Z-1 K1 K2 Loop Filter e-j(∆ŵ0*n - ˆθ) DDS Z-1ej(·) Rice, M. (2008). Digital Communications: A Discrete-Time Approach, Prentice Hall. 5/27/2010 19 37 Carrier Recovery Design � Error Detection algorithm – Calculate rotation from ideal QPSK constellation points � P+I Loop Filter – Set gain constants to produce desired step response � DDS – Phase accumulator and complex sinusoid generator Demo >> edit SyncTest1.m >> CarrierSyncSolution_eml Z-1ej(·) ej(∆w0*n - θ) arg(·) Phase Detector Z- 1 K1 K2 Loop Filter DDS 38 Carrier Synchronization with MATLAB 38 Built in communication functions Data visualization Synchronization loop Custom Functions Connect to Simulink Memory and persistence 5/27/2010 20 39 QPSK Receiver Synchronization: Complete Solution � Timing Recovery – Error Detector – Loop Filter – Timing Control Unit – Farrow Fractional Delay Filter Demo >> cont_time_sync � Carrier Recovery � Error Detector � Loop Filter � DDS � Multiplier � MATLAB for: � Algorithm design � Simulink for: � Closed loop control � Complex timing relationships � Interactivity and visualization � Self documenting design RX Sync 40 System Level OFDM Model � OFDM Specs – 64 tones, 48 carrying data, 4 carrying pilots, 12 guard band tones – 4-QAM modulation for each data tone – 1 Mbps data rate � Standard Channel Impairments – Phase/Frequency Offset – Dispersive Channel – AWGN – I/Q imbalance � End-to end BER Simulation Demo >> ofdm_basic 5/27/2010 21 41 Pilot Directed OFDM Synchronization Demo >> ofdm_syncFinal OFDM/ OFDMA OFDM/ OFDMA � Timing Recovery � Error Detector � Loop Filter � Timing Control Unit � Farrow Fractional Delay Filter � Carrier Recovery � Error Detector � Loop Filter � DDS � Multiplier � MATLAB for: � Algorithm design � Simulink for: � Closed loop control � Complex timing relationships � Interactivity and visualization � Self documenting design 42 Lightning Round!!! � Featuring – MAC Layer – DPD – MIMO – OFDMA – 3G/LTE 5/27/2010 22 43 Variable Packet Sources and Network Layers 43 � Stateflow � Control of Transmitter Modes, Packet acquisition, Packet assembly, Header decodingDemo >> packet2 MAC/Data Link Layer PHY LayerSignal Processing, Communications Blockset Stateflow Transmitter Receiver MAC/Data Link Layer PHY Layer � 802.11a Example � Variable sized, irregularly spaced packets � Multiple modulation modes � Packet acquisition and synchronization MAC Layer 44 Demo: IEEE 802.16-2004 w/ DPD � DPD: Use a signal processing technique to compensate for non- ideal RF characteristics � Single model that encompasses both the digital and RF domains � MATLAB + Simulink for multi- domain models: Analyze the impact of a design choice (RF component, FEC algorithm) on the overall system performance (SNR, BER) Demo >> DPD80216_1 DPD 5/27/2010 23 45 Demo: MMSE-SIC Receiver in Fading Channel for MIMO OFDM Systems � Applicable MIMO example for LTE, 802.16M � 2x2 MIMO receiver � Linear MMSE, MLD, MMSE-SIC algorithms � Evaluate MIMO Tradeoffs – Computational Complexity vs. BER Performance Demo >> OFDM_2X2_MMSE_SIC5 MIMO 46 802.16e OFDMA � WiMAX Slot Allocation and Framing – Preamble, FCH, DL-MAP � 802.16e modulator bank � 1024 FFT � Tail biting convolutional code Demo >> commwman80216e_1k_2user OFDM/ OFDMA 5/27/2010 24 47 会议日程 会议日程会议日程 会议日程 � 介绍 � 通信系统的可执行规范 � 特定的通信系统的设计 � 设计实现和验证 设计实现和验证设计实现和验证 设计实现和验证 � 后续工作 48 实现 实现实现 实现 工作流程 1. 黄金参考模型 2. 定点细化 3. 自动产生 C/HDL 代码 4. 软件联合仿真 5. 硬件原型 5/27/2010 25 49 在 在在 在HDL工作流程中使用 工作流程中使用工作流程中使用 工作流程中使用MathWorks工具 工具工具 工具 � 将详细的算法交给HDL 程序员 � 通过联合仿真用系统模 型验证 HDL 代码 � 采用自动产生的HDL 代 码创建原型 50 黄金参考模型 黄金参考模型黄金参考模型 黄金参考模型 � 实例: LTE 应用中的DDC 5/27/2010 26 51 DDC是什么 是什么是什么 是什么? � DDC 执行任务 – 输入信号的数字混频 – 窄带低通滤波和抽取 – 增益调整和最终数据流的重采样 � DDC 通常是定点实现 – 高速计算 – 降低成本，功耗和散热 52 接收端的 接收端的接收端的 接收端的DDC 例子 例子例子 例子 ~70 MSPS ~270 KSPS Digital Down Converter A/D Conv RF Section Demod >> Demo DDC Behavioral Model 5/27/2010 27 53 实现 实现实现 实现 工作流程 1. 黄金参考模型 2. 定点细化 3. 自动产生 C/HDL 代码 4. 软件联合仿真 5. 硬件原型 54 定点细化 定点细化定点细化 定点细化 � MATLAB 及 Fixed Point Toolbox : – 更好的算法灵活性 – 更精细的定点设置控制 � Simulink 及 Simulink Fixed Point : – 更多内置模块支持 – 自动定标特性 – 定点属性设置更简单 � 同时使用两个工具获得最大的灵活性 – 尽可能使用Simulink 模块 – 使用Embedded MATLAB 获得算法灵活性和对定点特性的更 多控制 5/27/2010 28 55 评估定点实现 评估定点实现评估定点实现 评估定点实现 � 创建测试平台包括: – 黄金参考浮点模型 – 定点模型 � 仿真和对比: – 功能级别结果 (如. 比特位对比 ) – 系统级别结果(如. BER, SNR, 等.) 56 评估定点实现 评估定点实现评估定点实现 评估定点实现 � 实例: DDC-LTE 模型测试平台 >> Demo DDC Fixed Point Test Bench 5/27/2010 29 57 评估定点实现 评估定点实现评估定点实现 评估定点实现 � 实例: 使用Simulink Fixed Point Tool 58 评估定点实现 评估定点实现评估定点实现 评估定点实现 System Level Metric Bit Level Compare 5/27/2010 30 59 实现 实现实现 实现 工作流程 1. 黄金参考模型 2. 定点细化 3. 自动产生 C/HDL 代码 4. 软件联合仿真 5. 硬件原型 60 产生 产生产生 产生HDL 代码的步骤 代码的步骤代码的步骤 代码的步骤 � 选择要产生代码的子系统 � 使用相容性检查 � 产生HDL 代码 � 通过联合仿真在模型里验证 HDL 代码 >> Demo Create HDL Code 5/27/2010 31 61 实现 实现实现 实现 工作流程 1. 黄金参考模型 2. 定点细化 3. 自动产生 C/HDL 代码 4. 软件联合仿真 5. 硬件原型 62 Simulink 和 和和 和 HDL 联合仿真 联合仿真联合仿真 联合仿真 � 验证自动产生代码的正确性 � 保持到模型的连接 Simulink Model HDL Code� 使用EDA Simulator 模块进行联合仿真 � 信号数据类型，端口，同步及时钟可以被定义 � HDL仿真可以在本地或网络上运行 � 支持 Mentor Graphics, Cadence, 和 Synopsys 5/27/2010 32 63 DDC-LTE HDL 代码产生 代码产生代码产生 代码产生 � 实例: 与 ModelSim进行HDL 联合仿真 >> Demo DDC Co-simulation 64 实现 实现实现 实现 工作流程 1. 黄金参考模型 2. 定点细化 3. 自动产生 C/HDL 代码 4. 软件联合仿真 5. 硬件原型 5/27/2010 33 65 硬件原型 硬件原型硬件原型 硬件原型 � 可编译C的实现 (DSP ) � 可综合 HDL-RTL 的实现(FPGA ) � 硬件在回路执行MATLAB/Simulink 模型 66 硬件原型 硬件原型硬件原型 硬件原型 实例 实例实例 实例: 在目标硬件上的 在目标硬件上的在目标硬件上的 在目标硬件上的SSB 通信 通信通信 通信 Lyrtech SignalWAVe � Texas Instruments C6713 DSP � Xilinx Virtex-II XC2V3000 FPGA � 存储器 – 32 MB SDRAM (DSP) – 32 MB SDRAM (FPGA) � Input/Output – 65MSPS 14-bit可编程增益 ADC – 125MSPS 14-bit DAC – NTSC/PAL复合视频解码 – NTSC/PAL复合视频编码 – Audio Codec www.mathworks.com/connections 5/27/2010 34 67 实例的开发流程 实例的开发流程实例的开发流程 实例的开发流程 • 算法 – 选择基本的系统拓扑结构 � Weaver’s (not phasing or filter) – 设计数字滤波器 � 多速率设计 � 验证滤波器的级联反应 • 验证可执行规范 • 分割, 细化, 设计 – RF 处理� FPGA – Audio 处理� TI DSP • 下载到目标硬件 Weaver's "Third Method" of SSB Generation TX B andli mit ed audio i nput (250-3250 Hz ) i s transl at ed by it s approxi mate c ent er freq (1600 Hz) and f il tered to c reate a c ompl ex baseband spect rum centered about DC. T hi s complex spect rum i s then transl at ed to t he desired RF out put frequency and re-combined to create a real (bandpass) si gnal. A Third Method of Generat ion and Detecti on of Si ngl e-Sideband Si gnal s, Donal d K. Weaver J r., Proc. IRE Dec 1956, pp 1703-1705 mix_4 mix_3 mix_2 mix_1 B-FFT Translated (real) Upper Sideband DSP Sine (1600Hz) DSP Multi Tone Audio In Re Im I,Q to cmplx x[n/8] FIR Interp Q x[n/8] FIR Interp I DSP Cos (1600Hz) B-FFT Complex Baseband Buffer FFT Audio Spectrum DSP 25+ kHz sine DSP 25+ kHz cos Simulink HF SSB Transceiver Red = 64MHz Cyan = 64MHz/4096 Dark Green = 64MHz/8192 Re(u) Im(u) c2ri Tx_out B-FFT Tx RF Spectrum lo_sin lo_cos IQ_in RF_out Tx Digital Up Converter 0 Sideband Select lsb_sel bfo_sin bfo_cos Audio_in IQ_out SSB Modulator IQ_in bfo_sin bfo_cos lsb_sel audio_out SSB Demodulator Rx_out Fo Rx/Tx Frequency B-FFT Rx I_Q Rx IQ_out RF_in lo_sin lo_cos I_Q_out Rx Digital Down ConverterRF input B-FFT RF Input Spectrum Fin LSB_sel hf_lo_sin hf_lo_cos bfo_sin bfo_cos Local Oscillators -K- Gain Freq (MHz) B-FFT AF Spectrum AF Input double (2) double double double double double double double double double (c) double double double double (c) double (2) double double SBSRAM 64k X 32 VIM- 2 MEZZANI NE VIRTEX XC2V1000/ 6000 BiF IFO Nod e A GPIO (59:0) C6x DSP Processor McBSP(1:0) CS4228 C6X BUS HEAD ER VIM_McBSP(1:0) JTAG VIM BUS CS4228 BiFI FO Node B (6)(2) R CA (6)(2) RC A TBC + JTAG connector J TAG SDRAM 16 MB PCI INTERFACE EEPR OM GLOBAL BUS cPCI J1 c P C I J 3 HPI MUX/ DEMUX C o nt r o l B U S ISA Contr ol CPLD F PG A C ON FIG SDRAM 4M X 32 cPCI J4 HEAD ER H.110 68 实例的开发流程 实例的开发流程实例的开发流程 实例的开发流程 选择构架 选择构架选择构架 选择构架， ，， ，设计算法 设计算法设计算法 设计算法， ，， ，验证可执行规范 验证可执行规范验证可执行规范 验证可执行规范， ，， ，验证设计 验证设计验证设计 验证设计 SSB Modulator Using Weaver’s Third Method 5/27/2010 35 69 实例的开发流程 实例的开发流程实例的开发流程 实例的开发流程 设计分割 设计分割设计分割 设计分割 70 实例的开发流程 实例的开发流程实例的开发流程