01.PowerPC.History

© Copyright IBM Corporation 2009 A Brief Introduction of The A Brief Introduction of The History of PowerPCHistory of PowerPC © Copyright IBM Corporation 2009Page 2 IBM 801 IBM 801 -- The Very Beginning of PowerPCThe Very Beginning of PowerPC �In 1970s, John Cocke at IBM Watson Research Lab started a research project on improving computer architecture design in a manner now collectively known as “RISC” �In 1977, the resulting CPU, IBM 801, is produced � All instructions complete in one clock cycle � 15MIPS, � No FPU � Was one of the first RISC CPU chip � 801 was named after the building where the project was done �IBM 801 was used in many IBM products, including 370 main frames in early 1980s �John Cocke later won both the Turing award and the Presidential Medal of Science for his work on the 801. © Copyright IBM Corporation 2009Page 3 POWER POWER –– The Parent of PowerPCThe Parent of PowerPC �1985, IBM Watson Research Lab started the research project on the second-generation RISC architecture based on the lessons learned from IBM 801 �The main research points include � Superscaler � Add of FPU �The effort resulted in the POWER architecture � Stands for Power Optimization With Enhanced RISC �The first implementation of POWER architecture was released on 1990 – the POWER1 �POWER1 were used in � RS/6000 in early 1990s � Central Processor for Mars Pathfinder mission �POWER1 is the chip where PowerPC is descended © Copyright IBM Corporation 2009Page 4 The Birth of PowerPCThe Birth of PowerPC �Around 1991, IBM approached Apple with the goal to develop microprocessors for large volume market based on POWER �Apple, then the largest customers of Motorola’s desktop-class microprocessor, asked Motorola to join the effort as a second source of manufacture of the target microprocessors �The 3 companies (the alliance is known as AIM )jointly published the PowerPC architecture � Basically follows POWER architecture � Supporting both big-endian and little-endian � Added single-precision floating point instructions and general register-to-register multiply and divide instructions � Removed some POWER features such as the specialized multiply and divide instructions using the MQ register. � Added 64 bit architecture � PC stands for Performance Computing �The first PowerPC architecture implementation is PowerPC 601 released on 1992 � Derived from POWER1 � But with Motorola 88000 like bus interface � Up to 66Mhz � Used in PowerMAC 6100 © Copyright IBM Corporation 2009Page 5 The Development of PowerPC by AIM Alliance in Mid 1990s The Development of PowerPC by AIM Alliance in Mid 1990s �PowerPC 603 � Low-end, low-power � Targeted for Apple’s notebook product, but the first model founds its 8K L1 cache is too small to hold the 68K emulator of MAC OS completely in cache. 603e corrected this problem by enlarging the cache to 16K � Mostly used in car � Become the ancestor of many Motorola’s variations of PowerPC latterly �PowerPC 604 � The first microprocessor to implement the entire PowerPC architecture. � The most powerful high-volume chip in its day � PowerPC604e is widely used in Apple’ Power Macintosh prior to 1997 as well as some IBM RS/6000 systems �PowerPC 620 � First 64-bit microprocessor implementing the entire PowerPC architecture and a sub-set of the POWER architecture. © Copyright IBM Corporation 2009Page 6 The G3 Era The G3 Era �Around 1997, IBM and Motorola published PowerPC740/750 � G3 is the name Apple used to describe PPC 740/750 �Derived from 604e �Outperformed contemporary Pentium II while consuming far less power and having smaller die size � 750 features in a off-die 512KB/1MB L2 cache which further boost the performance by 30% �750 is the world’s first cooper-fabrication chip �Used widely in Apple’s Power Mac G3, Power Book G3, iMac and iBook up to 2000 �Initial models runs up to 333Mhz and in 2002, IBM introduced a 1Ghz model of 750FX © Copyright IBM Corporation 2009Page 7 The G4 EraThe G4 Era �Refers to the PowerPC74xx CPUs used in Apple G4 product line �Debut around 1999 with 400-500Mhz models �PowerPC 74xx introduced the 128 bit AltiVec SIMD extension � Two vector paths � Each path can do 4-way SP floating point operation in single cycle �Enhanced support for SMP by improving cache coherency protocol �The latest 7447 model run up to 1.67Ghz © Copyright IBM Corporation 2009Page 8 The Evolution of POWER in IBM During The Same TimeThe Evolution of POWER in IBM During The Same Time � POWER 2 was released in 1993 � Added one more FPU and more cache � Best known as the CPU powered the 32 nodes DEEP BLUE supercomputer which beat Garry Kasparov at chess in 1997 � POWER 3 was released in 1998 � The first 64 bits SMP processor in POWER � Started the unification of POWER and PowerPC ISA by supporting both architecture � All subsequent POWER processors implemented the full 32-bit and 64-bit PowerPC instruction sets � Feature in two FPUs, three fixed-point units, and two load-store units � POWER 4 was released in 2001 � The first sever processor with a multicore design on a single die � Each module has two 64-bit 1Ghz+ cores � Was the single most powerful chip on the market at that time � Used both in IBM RS/6000 and AS/400 systems � Where PowerPC970 was derived � POWER 5 was released in 2003 � Implemented 2-way simultaneous multithreading (SMT) in each core � Implemented the hypervisor technology which used to only be found in mainframe � Allow multiple instances of different OS to be run in the same chip in the same time � POWER 6 was released in 2007 � Implemented 4.7G frequency,dual-core processor , power consumption is the same as POWER 5 � Implemented hardware decimal FPP, 65 nm, ultra-low power. © Copyright IBM Corporation 2009Page 9 The G5 EraThe G5 Era �Refers to the PowerPC 9xx CPUs used in Apple G5 product line �The previous 64 bit PPC 620 designed by AIM alliance turned out not to be so successful, so IBM decided to design a new 64 bit PowerPC chip based its POWER4 chip �2002, the first PowerPC 970 is released �Basically it is the one core version of POWER4 + VMX SIMD extension � VMX is IBM’s implementation of AltiVec �Up to 2.5Ghz, both single core and two core modules available �Used also in IBM Blade Server and some high end embedded devices © Copyright IBM Corporation 2009Page 10 PPC 4xx PPC 4xx -- The Scale Down of PowerPC for Embedded AreaThe Scale Down of PowerPC for Embedded Area �From later 1990s, IBM (and lately AMCC) developed the 4xx family targeted for low cost embedded application �Core optimized for embedded and lower power application �A SoC design with abundant integrated peripherals like Ethernet, USB, PCI, ATA �Clock speed ranges from 133Mhz-1.6Ghz �Currently in the form of hardcore/softcore IP � 405 family, entry level, No-FPU, 5-stage pipeline � 440/460 family, high performance, 2 way superscaler, out-of-order some models have FPU � 470 family, 9-stage,5 issue/out-of-order, PLB6 interface, SMP multi-core support �440 powered the world’s No.1 and No.2 fastest supercomputer, BlueGene as Nov 2005. � No. 1 - 280.6 TFLOPS with 131,072 440 core © Copyright IBM Corporation 2009Page 11 405LP 9SF 0.3 GHz 2.2mm2 / 0.04W PowerPC 4xx CPU Core Roadmap PowerPC 4xx CPU Core Roadmap 405 9SF 0.43 GHz 2.2mm2 / 0.1W 464FP 9SF 0.833 GHz 6.4mm2 / 0.85W464LP 9SF 0.55GHz 5.46mm2 / 0.36W440 9SF 0.667 GHz 6.2mm2 / 1.1W 440S 2008 2009 2010 2011 2012200720062005 460S405S 2.00 DMIPS / MHz 1.52 DMIPS / MHz 464 9SF 0.866 GHz 5.46mm2 / 0.6W 405 12S 0.466 GHz 1.1mm2 / 0.7W 476FP* 12S 1.6 GHz 3.5mm2 / 1.6 W 476FP 13S 2.1 GHz 2.5m2 / 1.3 W 90nm 65nm 45nm 32nm Synthesizable 405 10SF 0.33 GHz 1.4mm2 2.3 DMIPS / MHz 470S © Copyright IBM Corporation 2009Page 12 New Evolution in Game Console New Evolution in Game Console �All top 3 game console vendors selected PowerPC as the CPU architecture for their next generation console �Microsoft Xbox 360; published Nov 2005 � The CPU is basically a 3 core PowerPC and each core runs at 3.2Ghz with SMT and VMX support �SONY PS3; published Nov 2006 � Cell CPU, which contains one PPU plus 8 SPUs. PPU is basically a customized 970 core running at 3.2Ghz �Nintendo Wii; published Nov 2006 � PowerPC750 CL based, with performance enhanced and power optimized. © Copyright IBM Corporation 2009Page 13 Thank YouThank You