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MPIS处理器.pdf

MPIS处理器.pdf

上传者: sulinux 2010-12-18 评分 0 0 0 0 0 0 暂无简介 简介 举报

简介:本文档为《MPIS处理器pdf》,可适用于IT/计算机领域,主题内容包含ForewordJohnLHennessy,Founder,MIPSTechnolagiesIncFrederickEmmonsTermanDean符等。

ForewordJohnLHennessy,Founder,MIPSTechnolagiesIncFrederickEmmonsTermanDeanofEngineering,StanfordUniversityIamverypleasedtoseethisnewbookontheMIPSarchitectureatsuchaninterestingtimeintheyearhistoryofthearchitectureTheMIPSarchitecturehaditsbeginningsinandwasfirstdeliveredinBythelates,thearchitecturehadbeenadoptedavarietyofworkstationandservercompanies,includingSiliconGraphicsandDigitalEquipmentCorporationTheearlyssawtheintroductionoftheR,thefirstbitmicroprocessor,whilethemidssawtheintroductionoftheRatthetimeofitsintroduction,themostarchitecturallysophisticatedCPUeverbuiltTheendofthesheraldsanewerafortheMIPSarchitecture:itsemergenceasaleadingarchitectureintheembeddedprocessormarketTodate,overmillionMIPSprocessorshavebeenshippedinapplicationsrangingfromvideogamesandpalmtops,tolaserprintersandnetworkrouters,toemergingmarkets,suchassettopboxesEmbeddedMIPSprocessorsnowournumberMIPSprocessorsingeneralpurposecomputersbymorethan,toThisgrowthoftheMIPSarchitectureintheembeddedspaceanditsenormouspotentialledtothespinoutofMIPSTechnologies(fromSiliconGraphics)asanindependentcompanyinThus,thisbookfocusingontheMIPSarchitectureintheembeddedmarketcomesataverypropitioustimeUnlikethewellknownMIPSarchitecturehandbook,whichislargelyareferencemanual,thisbookishighlyreadableandcontainsawealthofsageadvicetohelptheprogrammertoavoidpitfalls,tounderstandsomeofthetradeoffsamongMIPSimplementations,andtooptimizeperformanceonMIPSprocessorsThecoverageisextremeIybroad,discussingnotonlythebasicsoftheMIPSarchitecture,butissuessuchasmemorymanagementandsystemsinstructions,cacheorganizationsandcontrol,andthefloatingpointinstructionsset(Althoughsomeembeddeduserswillbeuninterestedinthefloatingpoint,suchinstructionsareheavilyusedingraphicsintensiveapplications,suchasvideogamesandsettopboxes)iiiSeveralofthechaptersareuniqueinthattheauthorshareshisexperienceinprogrammingtheMIPSarchitectureThesechapterscovertopicsthatarecriticaltotheembeddedsystemsprogrammer,suchasCprogrammingconventions(eg,forregisteruseandprocedurelinkage),howtowriteportableMIPScode,andhowtoobtainthebestperformanceThecoverageofexceptionhandlingguidestheprogrammer,bytheuseofexamplecodesequences,whileincludingadescriptionofthecompleteexceptionarchitectureAsimportantasthetechnicalcontentofthisbookisitsreadabilitySimplystated,thisisbookfuntoreadDominicSweetman’sinsightsandpresentationhelpenticethereaderInmyview,thisbookisthebestcombinationofcompletenessandreadabilityofanybookontheMIPSarchitecture,andisfarbetterthanmostonotherarchitecturesInclosing,letmementionthatSweetman’sinsightsintothedevelopmentoftheMIPSarchitecturearetrulyexceptionalAsayearcontributortotheMIPSarchitecture,IamastoundedbytheperceptivenessoftheauthorinhisexplanationsoftherationaleforboththeMIPSarchitectureandthespecificimplementationsIamconfidentthatreadersinterestedinunderstandingorprogrammingtheMIPSarchitecturewilllearnwhattheyneedtoknowfromthisbook,andthattheywillenjoyreadingitAsafounderofMIPS,acontributortoboththefirstMIPSimplementation(theR)andseveralsubsequentimplementations,I’mdelightedthattheauthorbecameaMIPSconvertandchosetowritethisbook!ContentsForewordiPrefacexvStyleandLimitsxviiConventionsxviiiAcknowledgmentsxviiiRICSsandMIPSPipelinesWhatMakesaPipelineInefficientThePipelineandCachingTheMIPSFiveStagePipelineRISCandCISCGreatMIPSChipsofthePastandPresentRtoRR:ADiversionTheRRevolutionRandRMIPSComparedwithCISCArchitecturesConstraintsonInstructionsAddressingandMemoryAccessesFeaturesYouWon’tFindAFeatureYouMightNotExpectProgrammerVisiblePipelineEffectsiiiivContentsMIPSArchitectureAFlavorofMIPSAssemblyLanguageRegistersConventionalNamesandUsesofGeneralPurposeRegistersIntegerMultiplyUnitandRegistersLoadingandStoring:AddressingModesDataTypesinMemoryandRegistersIntegerDataTypesUnalignedLoadsandStoresFloatingFointDatainMemorySynthesizedInstructionsinAssemblyLanguageMIPSItoMIPSIVBit(andOther)ExtensionsToBitsWhoNeedsBitsRegardingBitsandNoModeSwitch:DatainRegistersOtherInnovationsinMIPSIIIBasicAddressSpaceAddressinginSimpleSystemsKernelvsUserPrivilegeLevelTheFullPicture:TheBitviewoftheMemoryMapPipelineHazardsCoprocessor:MIPSProcessorControlCPUControlInstructionsWhatRegistersAreRelevantWhenEncodingsofStandardCPUControlRegistersProcessorID(PRId)RegisterStatusRegister(SR)CauseRegisterExceptionReturnAddress(EPC)RegisterContentsvBadVirtualAddress(BadVaddr)RegisterControlRegistersfortheRCPUandFollowersCountCompareRegisters:TheRTimerConfigRegister:RxConfigurationLoadLinkedAddress(LLAddr)RegisterDebuggerWatchpoint(WatchLoWatchHi)RegistersCachesforMIPSCachesandCacheManagementHowCachesWorkWriteThroughCachesinEarlyMIPSCPUsWriteBackCachesinRecentMIPSCPUsOtherChoicesinCacheDesignManagingCachesSecondaryandTertiaryCachesCacheConfigurationsforMIPSCPUsProgrammingRStyleCachesUsingCacheIsolationandSwappingInitializingandSizingInvalidationTestingandProbingProgrammingRStyleCachesCacheERR,ERR,andErrorEPCRegisters:CacheErrorHandlingTheCacheInstructionCacheSizingandFiguringOutConfigurationInitializationRoutinesInvalidatingorWritingBackaRegionofMemoryintheCacheCacheEfficiencyReorganizingSoftwaretoInfluenceCacheEfficiencyWriteBuffersandWhenYouNeedtoWorryviContentsImplementingwbfiushMoreaboutMIPSCachesMultiprocessorCacheFeaturesCacheAliasesExceptions,Interrupts,andInitializationPreciseExceptionsWhenExceptionsHappenExceptionVectors:WhereExceptionHandlingStartsExceptionHandling:BasicsReturningfromanExceptionNestingExceptionsAnExceptionRoutineInterruptsInterruptResourcesinMIPSCPUsImplementingInterruptPriorityAtomicityandAtomicChangestoSRCriticalRegionswithInterruptsEnabled:SemaphorestheMIPSWayStartingUpProbingandRecognizingYourCPUBootstrapSequencesStartingUpanApplicationEmulatingInstructionsMemoryManagementandtheTLBMemoryManagementinBigComputersBasicProcessLayoutandProtectionMappingProcessAddressestoRealMemoryPagedMappingPreferredWhatWeReallyWantOriginsoftheMIPSDesignMIPSTLBFactsandFiguresContentsviiMMURegistersDescribedEntryHi,EntryLo,andPageMaskIndexRandomWiredContextandXContextMMUControlInstructionsProgrammingtheTLBHowRefillHappensUsingASIDsTheRandomRegisterandWiredEntriesMemoryTranslation:SetupTLBExceptionSampleCodeTheBitRStyleUserTLBMissExceptionHandlerTLBMissExceptionHandlerforRxCPUXTLBMissHandlerKeepingTrackofModifiedPages(Simulating“Dirty”Bits)MemoryTranslationandBitPointersEverydayUseoftheMIPSTLBMemoryManagementinaNonUNIXOSFloatingPointSupportABasicDescriptionofFloatingPointTheIEEEStandardandItsBackgroundHowIEEEFloatingPointNumbersAreStoredIEEEMantissaandNormalizationReservedExponentValuesforUsewithStrangeValuesMIPSFPDataFormatsMIPSImplementationofIEEENeedforFPTrapHandlerandEmulatorinAllMIPSCPUsFloatingPointRegistersConventionalNamesandUsesofFloatingPointRegistersviiiContentsFloatingPointExceptionsInterruptsFloatingPointControl:TheControlStatusRegisterFloatingPointImplementationRevisionRegisterGuidetoFPInstructionsLoadStoreMovebetweenRegistersThreeOperandArithmeticOperationsMultiplyAddOperationsUnary(SignChanging)OperationsConversionOperationsConditionalBranchandTestInstructionsInstructionTimingRequirementsInstructionTimingforSpeedInitializationandEnablingonDemandFloatingPointEmulationCompleteGuidetotheMIPSInstructionSetASimpleExampleAssemblerMnemonicsandWhatTheyMeanUandNonUMnemonicsDivideMnemonicsInventoryofInstructionsFloatingPointinstructionsPeculiarInstructionsandTheirPurposesLoadLeftLoadRight:UnalignedLoadandStoreLoadLinkedStoreConditionalConditionalMoveInstructionsBranchLikelyIntegerMultiplyAccumulateandMultiplyAddInstructionsFloatingPointMultiplyAddInstructionsMultipleFPConditionBitsPrefetchContentsixSync:ALoadStoreBarrierInstructionEncodingsFieldsintheInstructionEncodingTableNotesontheInstructionEncodingTableEncodingsandSimpleImplementationInstructionsbyFunctionalGroupNopRegisterRegisterMovesLoadConstantArithmeticalLogicalIntegerMultiply,Divide,andRemainderIntegerMultiplyAccumulateLoadsandStoresJumps,SubroutineCalls,andBranchesBreakpointandTrapCPfunctionsFloatingPointATMizerIIFloatingPointAssemblerLanguageProgrammingASimpleExampleSyntaxOverviewLayout,Delimiters,andIdentifiersGeneralRulesforInstructionsComputationalInstructions:Three,Two,andOneRegisterRegardingBitandBitInstructionsAddressingModesGpRelativeAddressingAssemblerDirectivesSelectingSectionsPracticalProgramLayoutIncludingStackandHeapDataDefinitionandAlignmentxContentsSymbolBindingAttributesFunctionDirectivesAssemblerControl(set)CompilerDebuggerSupportAdditionalDirectivesinSGIAssemblyLanguageCProgrammingonMIPSTheStack,SubroutineLinkage,andParmeterPassingStackArgumentStructureUsingRegisterstoPassArgumentsExamplesfromtheCLibraryAnExoticExample:PassingStructuresPassingaVariableNumberofargumentsReturningaValuefromaFunctionEvolvingRegisterUseStandards:SGI’snandnStackLayouts,StackFrames,andHelpingDebuggersLeafFunctions

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