HA-2540

1 ® HA-2540 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 400MHz, Fast Settling Operational Amplifier The Intersil HA-2540 is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. Bipolar construction coupled with dielectric isolation allows this truly differential device to deliver outstanding performance in circuits where closed loop gain is 10 or greater. Additionally, the HA-2540 has a drive capability of ±10V into a 1kΩ load. Other desirable characteristics include low input voltage noise, low offset voltage, and fast settling time. A 400V/µs slew rate ensures high performance in video and pulse amplification circuits, while the 400MHz gain- bandwidth product is ideally suited for wideband signal amplification. A settling time of 140ns also makes the HA-2540 an excellent selection for high speed Data Acquisition Systems. Refer to Application Note AN541 and Application Note AN556 for more information on High Speed Op Amp applications. Pinout HA-2540 (CERDIP) TOP VIEW Features • Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 400V/µs • Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 140ns • Wide Gain Bandwidth (AV ≥ 10). . . . . . . . . . . . . . 400MHz • Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MHz • Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 8mV • Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . 6nV/√Hz • Output Voltage Swing . . . . . . . . . . . . . . . . . . . . . . . ±10V • Monolithic Bipolar Construction Applications • Pulse and Video Amplifiers • Wideband Amplifiers • High Speed Sample-Hold Circuits • Fast, Precise D/A Converters For a lower power version of this product, please see the HA-2850 datasheet. NC NC NC -IN +IN V- NC NC NC NC V+ OUTPUT NC NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HA1-2540-5 0 to 75 14 Ld CERDIP F14.3 Data Sheet July 2003 FN2897.5 HA-2540 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Output Current . . . . . . . . . . . . . . 33mARMS Continuous, 50mAPEAK Operating Conditions Temperature Range HA-2540-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 Maximum Internal Power Dissipation (Note 1) Maximum Junction Temperature (Ceramic Package) . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175oC for the ceramic package, and below 150oC for the plastic package. By using Application Note AN556 on Safe Operating Area Equations, along with the thermal resistances, proper load conditions can be determined. Heat sinking is recommended above 75oC. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15V, RL = 1kΩ , CL < 10pF, Unless Otherwise Specified PARAMETER TEMP (oC) MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 25 - 8 15 mV Full - 13 20 mV Average Offset Voltage Drift Full - 20 - µV/oC Bias Current 25 - 5 20 µA Full - - 25 µA Offset Current 25 - 1 6 µA Full - - 8 µA Input Resistance 25 - 10 - kΩ Input Capacitance 25 - 1 - pF Common Mode Range Full ±10 - - V Input Noise Current (f = 1kHz, RSOURCE = 0Ω) 25 - 6 - pA/√Hz Input Noise Voltage (f = 1kHz, RSOURCE = 0Ω) 25 - 6 - nV/√Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) 25 10 15 - kV/V Full 5 - - kV/V Common-Mode Rejection Ratio (Note 4) Full 60 72 - dB Minimum Stable Gain 25 10 - - V/V Gain Bandwidth Product (Notes 5, 6) 25 - 400 - MHz OUTPUT CHARACTERISTICS Output Voltage Swing (Notes 3, 10) Full ±10 - - V Output Current (Note 3) 25 ±10 ±20 - mA Output Resistance 25 - 30 - Ω Full Power Bandwidth (Notes 3, 7) 25 5.5 6 - MHz TRANSIENT RESPONSE (Note 8) Rise Time 25 - 14 - ns Overshoot 25 - 5 - % Slew Rate 25 320 400 - V/µs Settling Time: 10V Step to 0.1% 25 - 140 - ns 2 HA-2540 POWER REQUIREMENTS Supply Current Full - 20 25 mA Power Supply Rejection Ratio (Note 9) Full 60 70 - dB NOTES: 3. RL = 1kΩ, VO = ±10V. 4. VCM = ±10V. 5. VO = 90mV. 6. AV = 10. 7. Full power bandwidth guaranteed based on slew rate measurement using: . 8. Refer to Test Circuits section of the data sheet. 9. VSUPPLY = +5V, -15V and +15V, -5V. 10. Guaranteed range for output voltage is ±10V. Functional operation outside of this range is not guaranteed. Electrical Specifications VSUPPLY = ±15V, RL = 1kΩ , CL < 10pF, Unless Otherwise Specified (Continued) PARAMETER TEMP (oC) MIN TYP MAX UNITS FPBW Slew Rate2πVPEAK ---------------------------= Test Circuits and Waveforms FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE FIGURE 2. SETTLING TIME TEST CIRCUIT VIN 900 100 VOUT-+ NOTES: 11. AV = +10. 12. CL ≤ 10pF. A B Vertical Scale: A = 0.5V/Div., B = 5.0V/Div. Horizontal Scale: 50ns/Div. Vertical Scale: Input = 10mV/Div.; Output = 50mV/Div. Horizontal Scale: 20ns/Div. 0.001µF 1µF 0.001µF 1µF 2kΩ 5kΩ 500Ω 200Ω V+ V- - + PROBE MONITOR OUTPUT INPUT SETTLE POINT NOTES: 13. AV = -10. 14. Load Capacitance should be less than 10pF. Turn on time delay typically 4ns. 15. It is recommended that resistors be carbon composition and the feedback and summing network ratios be matched to 0.1%. 16. SETTLE POINT (Summing Node) capacitance should be less than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor. 3 HA-2540 Schematic Diagram OUTPUT R3 R24 R13 QP28 QP18 QP19 QP17 QP22 QP6 QP5 QP25 QP3 QP4 R6 R7 R8 R9 QN1 QN2 R11 R12 R14 R25 V+ R10 QN14 QN20 QN15 QN25 QN29 V+R21 R22 QP23 QN21 + INPUT - INPUT Z1 DZ1 DZ2 QP8 QN9 QN7 QN10 QN13 R4 R5 C2 V+ R19 R18 QN16 QN12 R17 R16 R15 QP11 C1 RC2 V- V- V- R23 R1 R2 Typical Applications FIGURE 3. WIDEBAND SIGNAL SPLITTER FIGURE 4. BOOTSTRAPPING FOR MORE OUTPUT CURRENT AND VOLTAGE SWING Refer to Application Note AN541 For Further Application Information. HA-2540 + 200 V+ V- 2K 2K OFFSET ADJUST - NOTE: With one HA-2540 and two low capacitance switching diodes, signals exceeding 10MHz can be separated. This circuit is most useful for full wave rectification, AM detectors or sync generation. NOTES: 17. Used for experimental purposes. CF ≅ 3pF. 18. C1 is optional (0.001µF → 0.01µF ceramic). 19. R5 is optional and can be utilized to reduce input signal amplitude and/or balance input conditions. R5 = 500Ω to 1kΩ. HA-2540 V+ V- CF (NOTE 17) C1 (NOTE 18) 1K 1K R5 10K R1 4K R2 4K SIGNAL OUT 0.1µF R3 4K R4 4K (NOTE 19) -+ 4 HA-2540 Typical Performance Curves FIGURE 5. CLOSED LOOP FREQUENCY RESPONSE FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUENCY FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 8. NORMALIZED AC PARAMETERS vs TEMPERATURE FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE FREQUENCY (Hz) C LO S E D L O O P G A IN (d B ) 100 1K 10K 100K 1M 10M 100M -10 10 30 40 50 60 70 80 90 100 0 20 FREQUENCY (Hz) O U TP U T V O LT A G E S W IN G (V P -P ) 1K 10K 100K 1M 10M 100M 0 4 8 12 16 20 24 28 VS = ±15V VS = ±10V VS = ±5V O U TP U T V O LT A G E S W IN G (V P -P ) RESISTANCE (Ω) 0 200 400 600 800 1K 1.2K 0 4 8 12 16 24 28 20 TEMPERATURE (oC) N O R M A LI ZE D P A R A M ET ER S R EF ER R ED T O VA LU ES A T 25 o C -80 -40 0 40 80 120 160 SLEW RATE BANDWIDTH 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 SETTLING TIME (ns) O U TP U T V O LT A G E S TE P (V ) 0 8040 120 160 200 240 -10 -8 -6 -4 -2 2 4 6 8 10 10mV 1mV 10mV 1mV 0 TEMPERATURE (oC) -80 -40 0 40 80 120 160 0 4 8 12 16 24 28 20 S U P P LY C U R R E N T (m A ) VS = ±15V VS = ±5V 5 HA-2540 FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUENCY FIGURE 13. BROADBAND NOISE (0.1Hz TO 1MHz) FIGURE 14. COMMON MODE REJECTION RATIO vs FREQUENCY FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUENCY FIGURE 16. OPEN LOOP GAIN/PHASE vs FREQUENCY Typical Performance Curves (Continued) TEMPERATURE (oC) -80 -40 0 40 80 120 160 0 2 4 6 8 12 14 10 IN P U T B IA S C U R R E N T (µA ) BIAS CURRENT OFFSET VOLTAGE 0 1 2 3 4 6 7 5 |V IO | O FF S E T V O LT A G E (m V ) 0 5 10 15 20 25 100 1K 10K 100K10 0 10 20 30 40 50 N O IS E V O LT A G E (n V /√H z) N O IS E C U R R E N T (p A /√H z ) VOLTAGE CURRENT NOISE RSOURCE = 0Ω , VS = ±15 NOISE FREQUENCY (Hz) +40µV +20µV +10µV 0µV -10µV -20µV -30µV -40µV +30µV Vertical Scale: 10mV/Div. Horizontal Scale: 50ms/Div. FREQUENCY (Hz) 1K 10K 100K 1M 10M 0 20 40 60 80 100 120 VS = ±15, RL = 1K C M R R (d B ) FREQUENCY (Hz) 1K 10K 100K 1M P S R R (d B ) 0 20 40 60 80 100 POSITIVE SUPPLY NEGATIVE SUPPLY 10M FREQUENCY (Hz) 100 10K 100K 1M 10M 100M1K -10 0 20 40 60 80 100 O P E N L O O P G A IN (d B ) 225 180 135 90 45 0 GAIN PHASE P H A S E (D E G R E E S ) 6 HA-2540 Die Characteristics DIE DIMENSIONS: 62 mils x 76 mils x 19 mils 1575 µmx 1930µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (Powered Up): V- TRANSISTOR COUNT: 30 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-2540 V+ OUTPUT V- +IN-IN - IN + IN 7 8 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com HA-2540 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E S1 b2 b A e M c1 b1 (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 14 14 8 Rev. 0 4/94