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BB/RF/layout Training Session Gary Hsu Bientec 2 Typical PCB structure (1/3) 20 24 18 12 L1 L2 L3 Ln-2 Ln-1 Ln 12 20 24 12 12 16 8 18 88 5 16 8 8 N>=8 4 4 4 4 Unit: mil Bientec 3 Typical PCB structure (2/3) · Multi-Layer Structure Number of layers: 6 Total thickness (measured on solder resist): 860um +/-10% Layer 1 copper thickness----------------------------------------------------0.7mil Epoxy 1 thickness (rcc)------------------------------------------------------2.0mil Er=3.7 Layer 2 copper thickness----------------------------------------------------1.4mil Epoxy 2 thickness (Prepreg FR4)--------( 1080 x 2 ) ---------------5.5mil Er=4.2 Layer 3 copper thickness----------------------------------------------------1.4mil Epoxy 3 thickness (Core FR4)---------------------------------------------12.0mil Er=4.2 Layer 4 copper thickness----------------------------------------------------1.4mil Epoxy 4 thickness (Prepeg FR4)-------- -( 1080 x 2 ) -------------------5.5mil Er=4.2 Layer 5 copper thickness----------------------------------------------------1.4mil Epoxy 5 thickness (rcc)------------------------------------------------------2.0mil Er=3.7 Layer 6 copper thickness----------------------------------------------------0.7mil Bientec 4 Typical PCB structure (3/3) Dielectric (Prepreg) 1)RCC (Resign Coated Copper): 65um,80um (excluding copper thickness) 2)LDP (Laser Drill Prepreg) (FR-4) 3.4mil (1X1086); 3.2mil (1X1067) 3)Normal Prepreg (FR-4): 2.8mil (1X1080); 3.0mil (1X1080H) 4)High Tg Prepreg (FR-4): 3.0mil (1X1080); 2.5mil (1X106) 5)Halogen free Prepreg: 2.4mil (1X1080) Core material: 1)FR-4 Normal material: Tg 140º, Dk 4.3(1MHz), High Tg material: Tg >160º, Dk 4.1(1MHz) 2)Rogers RO4350/RO4403: Tg>280º, Dk 3.5(1GHz) 3)Hitachi MCL-LX-67/GXA-67N: Tg>175, Dk 3.7(1MHz) Bientec 5 Typical PCB Design Rules PCB track width Vbat line : 2mm for Vbat to power amplifier Others depend on Max. current Ground line : 0.3mm, 0.2mm at least Power signal line : 0.3mm, 0.2mm, or less BB signal line : 0.1mm I/Q signal line : 0.1mm Control signal line : 0.1mm 13M signal line : 0.2mm Audio signal line : 0.2mm (0.3mm for HP) IF signal line : 0.1mm RF signal line : derived from 50ohm control impedance Standard Clearance: 0.15mm Minimum Clearance: 0.1mm (4mil) RF line clearance is two times as RF line track at least Bientec 6 Layout- VH structure Bientec 7 PCB Layer 1+2+3 Bientec 8 PCB Layer 4+5+6 Bientec 9 PCB Layer 7+8 Bientec 10 Power supply PA V battery GND Bientec 11 Criterion Descriptions 0. Floor plan Define the areas of RF, BB, LCD, battery connector , antenna connector , phone jack connector, screw hole and test point. It could also be depended the phone factor fix already. 1. Shielding Pay attention to constructive details, e.g. all of shielding room should have the holes on it to avoid the heat flow destroy itself when placed on the PCB except for the way of shielding room is built with housing together. 2. Interfaces Evaluate the RF, IF and BB, respectively if needed. 3. Determine signal and ground-layers Decide the am ount of layers and PCB-structured. 4. Determine 50O -lines M ark them in schematic and calculate them via the RF tool e.g. LinCal/ADS. 5. Detect critical lines M ark them in the schematic 6. Detect lines with high current M ark them in the schematic and calculate them 7. Define filtering unit Draw them in the schem atic 8. Determine the pads for (back-up) capacitors around the devices Draw them in the schem atic 9. Define testing points Place them together on the PCB to easily design the fixture. Layout Procedure Bientec 12 Criterion Descriptions 10. Create com ponent-puzzle Place them on the layout (recomm ended at a scale of >5:1) and their spacing between themselves should be able to be soldered, changed, plugged and so forth. 11. Define separate grounds / ground-islands M ark them in the schematic 12. Start to layout from the areas of highest frequency and sensitive parts Determine via and ground areas roughly 13. Layout from the first critical line Set the priorities, e.g. RF > IF > digital signal lines > DC lines with high current density M ake them as short as possible and don’t be parallel with other critical lines causing in the cross talking as less as possible. 14. Create special ground areas Fill up the whole ground-planes after the com plete layout has been done! Determine the heating-drops in order to avoid the soldering problem s 15. Delete isolated ground-planes 16. Determine labelling if necessary M ark the testing-poin ts, jumper, connectors, importan t signal-lines, areas, and so on. 17. Check the layout and com pare with the size of sh ielding room and housing M ake foils of the layer and check lines, via, and mechanic before sending the make the real layout. 18. Assemble the PCB and Housing M ake the note and rem odify the unsatisfied defect result and do it again until the design is OK. Layout Procedure PCB check list.xls Bientec 13 ENDCOAX 1 2 C3 C2 C1 L1 L3 L2 C4 Layout-Baluns and tuned circuits Balun Bientec 14 Semi-integrated IF VCO of OM5178: ØThe distance between the IF VCO and IQ signals should be maximised to avoid cross talk. ØFor better phase noise we recommend the higher Q-factor inductors for the resonator. e.g. Coilcraft. ØThe inductor needs to be perpendicular to the capacitors located the input of RXON and TXON in order to avoid the cross coupling. Layout- IF loop filter Bientec 15 From Charge Pump To VCO C1 GND R2 C2 C3 R3 T1 = (R2 ´ C2 ´ C1) / (C1 + C2) ; T2 = R2´ C2 ; T3 = R3´ C3 if C2>> C1>> C3 Film, NPO or ‘Low Distortion’ types are used as the main capacitor in the loop filter. They should have the same ground as the RFVCO to improve the TX phase error from TC or PA. X7R types cause 4-5 dB higher spectral emissions in the critical 400- 600 kHz region. It is mandatory to place the first capacitor in the loop filter by the transceiver ICs as close as possible to the charge pump output. Place the third-order capacitor close to the RFVCO body to suppress the higher frequency noise. Layout-RF loop filter Bientec 16 Capacitors (1/10) The SMT capacitors are usually divided depending on material and/or process. The most important ones are: •MLCC (Multi Layer Ceramic Capacitor) •SLC (Single Layer Capacitor) •Film Chip •Tantalum •Aluminum Bientec 17 Capacitors (2/10) The “ideal” capacitor can be conditioned by the following electrical and physical parameters: •Temperature •Applied AC/DC voltage •Aging •Tolerance due to production •Application frequency range •Size Bientec 18 Capacitors (3/10) Temperature Degree C Bientec 19 Capacitors (4/10) DC Voltage ( V) Bientec 20 Capacitors (5/10) AC Voltage ( Vrms) Bientec 21 Capacitors (6/10) Tolerance in production •Every type of capacitor includes a tolerance due to the mass production, usually indicated in %. The standard values are: Type of capacitor: Related Values of tolerance: vMLCC C0G (general purpose) +/- 0.25pF, +/-0.5pF or 5% vMLCC C0G (for microwave) +/- 0.05pF up to +/-0.1pF vMLCC X7R +/- 10% vMLCC Z5U +/- 20% vMLCC Z5U, Y5V +80, -20% vSLC +/- 0.01pF up to +/-10% vSLD-MLCC +/- 10% vFilm Chip +/- 5%, +/- 10% vTantalum +/- 5%, +/- 10%, +/- 20% Bientec 22 Capacitors (7/10) •In order to improve the characteristic of capacitor vs.waveform distortion and applied DC voltage, a new type of capacitor was introduced. •Usually called Film Chip Capacitor, or Super Low Distortion Capacitor (S LD-MLCC) are special capacitors which reduce the influence from these parameters. Bientec 23 Capacitors (8/10) Comparison among different Types of Capacitors Bientec 24 Capacitors (9/10) Comparison among different Types of Capacitors The SLD type has worse performance then the film chip type on temperature characteristic. SLD type is equal to chip film type on DC bias characteristic Bientec 25 Capacitors (10/10) Go to this website http://www.kemet.com/KEMET/web/homepage/kechome.nsf/vabypagename/spicesoft to have a quick simulation what the value of the capacitor is correspond with the range of frequency If you need a quality system, you should know what kind of capacitor is more suitable for your specific application! Bientec 26 Herewith below is the LO VCO checklist: ØThe VCO ground should have a good grounding effect with PCB through via holes between the inner layers and the layer where the VCO is placed. ØThe partition areas with a series of via holes at the min. distance should be designed for each VCOs, e.g. TXVCO, RXVCO and VTCXO so as to provide the maximum isolation among them. ØThe RFVCO should be kept as far as possible from the PA output to decrease the phase error. ØRFVCO should be placed at the other side where TXVCO is placed since both VCO are working at same time. Due to the SAR consideration, TXVCO and PA should be placed at the opposite side of human ear side. Layout- LO VCO Bientec 27 Layout- signal lines -1 Herewith below are the signal lines checklist: ØThe signal line path from the PA output and RF SAW filter to antenna should be kept as short as possible in case that output power of PA is limited. Also, the path of signal line from PA should be kept on the top layer. If necessary, it should be totally surround by ground and carefully calculated its impedance 50 ohm in the inner layers. Besides, it should also have the clean space above and below among the inner layers. ØThe higher frequency is required, the shorter the lines are needed. Hence, the path of PCS band should be considered with at the first priority to be layouted. Try to keep the short distance for PCS receive part since the receive sensitivity in PCS part is less than 2 dB more than GSM. Bientec 28 ØThe track should be designed at 50 ohm RF impedance for the input and output of PA, output of RXVCO, input and output TXVCO, the RX path before the Balun. ØIf the RF and Audio signal line should go to the inner layer due to the limitation of top and bottom area, the line should be protected well by up, down and surrounding ground. ØThe transmission lose of 50 ohm signal line can be reduced in terms of removing the ground area at its bottom layer. The distance between the 50 ohm and its second bottom ground layer can increase its Q value. Layout- signal lines-2 Bientec 29 Layout- signal lines-3 Ø VCTXO provides the reference signal for system. Hence, the layout of 13 MHz of VCTXO should be totally protected against the interference from DC and other signal sources. Bientec 30 Ø The width of all of control line should be as small as possible in order to eliminate spurious in band. The state of art to have the smallest width is 4 mil with quality. In order to improve the quality in mass production, it is strongly recommend that the track width should have 5 mil at least. Please also check your local PCB manufacturer whose capabilities on it. Ø Since the key pads are connected directly to BB so that all of control lines should be routed into the inner layers to avoid the interference, otherwise the copper foil unfortunately could be applied on them. If Vbat is also shown up on top layer, please put into the middle layer and protect it well totally. Ø 39pF /10pF and 100 ohm should be closely added around the pin RXON/TXON of transceiver IC to suppress the noise. Herewith below are the control lines checklist: Layout- Control lines- 1/3 Bientec 31 ØAll of de-coupling capacitors, e.g. the value of 8.2pF for DCS, 39pF for GSM, 100nF for DC noise suppression should be closely located to the devices e.g. the ICs and VCOs. Also, their sequence placed around the devices is 8.2pF, 39pF, and 100nF, respectively. If needed, the 100 nF can be a little bit adjusted far away from the devices depended on the limitation of PCB area. ØThe track from VCHARGE to the pin VBAT/G in PMUxxxx should have the width at least 30 mil in order to suffer a big current sink up to 1A or depend on the charging method. ØThe track from VBAT/G to the pin 5 and 7 in BGY28x or Hitachi PA should have the width 40 mil at least in order to suffer a big current sink from 1 to 2A (180 mA x 8 =1.44 A). However, the bigger width, the less value of line impedance. Hence, the capacitor for PA can use the small value and still remain the same performance by using of the bigger width, for instance phase error. Herewith below are the control lines checklist: Layout- Control lines- 2/3 Bientec 32 ØThe track from VBAT/G to Buzzer should also have width 25 mil since it has up to 70 mA consumption as soon as the ring is coming. ØAbove DC tracks should be layouted by using of fish-like topology. ØRXON/ TXON lines from BAI to TC are not allowed to overlay the PA power supply (VBAT) and the line VCC-SYN is not allowed to be routed in parallel to the PA power supply (VBAT) because of in-band spurious. Layout- DC lines Bientec 33 ØThe VCC-SYN can not be supplied as same DC source from VBATT (TX-PA). ØThe area where DC line to PA from the inner layer to top or bottom layer should be placed more via. ØAll of DC lines for TC IC should be totally isolated with PA DC line by ground and don’t go in parallel with PA DC line. ØAll of regulators supplied for TC IC should be closely placed around TC IC. In the real layout, they could be placed around TC IC or together with the area of PA control loop Layout- DC lines Bientec 34 Phone Jack and Vsave Battery ØPhone Jack and Vsave Battery should be placed closely the PMU or BAI, respectively. If the Phone Jack should be placed at the top of PCB fortunately, its lines connected with either the PMU or the BAI should be far away from the PA to avoid the interference. Vibrator The vibrator should not be placed on the PCB directly since it leads more or less attenuation of the vibrator mechanism, meaning that it should be mounted with the housing without a rubber. Layout- Phone Jack and Vibrator Bientec 35 Micbias track -has to be routed as far as possible from the other lines -has to be completed inside the baseband shielding area Components All of components should be closed placed the MCP or microphone or earpiece shown in the left diagram. Layout- Audio Bientec 36 In red --> What you have to suppress In blue --> What you have to modify (only an example) In yellow --> What you have to had (connection to main ground by one point) Layout- Microphone Ground Bientec 37 Layout- Audio Sysol2 Scale 1 Bad Audio Layout Bientec 38 It is strongly recommend that the plastic case is metalised inside over the entire area for better EMI immunity and SAR. The public are now are aware of technology pollution. Layout-shielding rooms example Bientec 39 Between RFVCO and TC has the min. distance. Between PA and RFVCO has the max. distance There is +/-3dB for PA input margin from TC Between PA and Antenna test port has the min. distance. Layout- Sysol2 RF component placement example Bientec 40 Layout- the best placement example Duplexer PA PMU TC TXVCO MCP MemoryCharger IC