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首页 VHDL 语言

VHDL 语言.ppt

VHDL 语言

heroreborning
2010-11-07 0人阅读 举报 0 0 暂无简介

简介:本文档为《VHDL 语言ppt》,可适用于高等教育领域

PROGRAMMABLELOGICDESIGNWITHVHDLEricDeng(haitao)FieldApplicationsEngineerCypressSemiconductoredxcypresscomPROGRAMMABLELOGICDESIGNWITHVHDLEricDeng(haitao)FieldApplicationsEngineerCypressSemiconductoredxcypresscomObjectivesObjectivesYouwilllearnenoughaboutVHDLto:DesignefficientcombinatorialandsequentiallogicDesignstatemachinesandunderstandimplementationtradeoffsDesignusingmultilevelhierarchyIdentifyhowVHDLwillsynthesizeandfitintoaPLDorCPLDObjectives(contd)Objectives(contd)YouwilllearnenoughabouttheWarpsoftwareto:CompileandsynthesizeVHDLdesignsforprogrammablelogicdevicesTargetPLDsCPLDsSimulatetheresultingdevicefunctionalityinNovaUsethereportfiletodetermineoperatingfrequency,setuptime,clocktooutputdelay,anddeviceresourceusageAgendaAgendaVHDLDesignDescriptionsTheEntity,Ports,Modes,TypesExercise#TheArchitecture,ArchitectureStylesVHDLStatements,CombinatorialLogicProcesses,SignalsVsVariablesVHDLOperatorsOverloadingInferencingVHDLIdentifiersExercise#MORNINGBREAKUsingWarpExercise#RegisteredLogicImplicitMemoryLUNCHExercise#StateMachinesandStateEncodingExercise#AFTERNOONBREAKHierarchicalDesignsExercise#MiscellaneousTopicsSummaryandConclusionWhatisVHDLWhatisVHDLVHSIC(VeryHighSpeedIntegratedCircuit)HardwareDescriptionLanguageVHDLisaDesignDescriptionLanguageVHDLisaDesignDocumentationLanguageVHDLisaSimulationLanguageItisanIEEEStandardLanguage(IEEE)WhyUseVHDLWhyUseVHDLVeryFastTimetoMarketAllowsdesignerstoquicklydevelopdesignsrequiringtensofthousandsoflogicgatesormoreProvidespowerfulhighlevelconstructsfordescribingcomplexlogicSupportsmodulardesignmethodologyandmultiplelevelsofhierarchyOnelanguagefordesignandsimulationAllowscreationofdeviceindependentdesignsthatareportabletomultiplePLDvendorsAllowsusertopickanysynthesistool,vendor,ordeviceVHDLDesignDescriptionsVHDLDesignDescriptionsVHDLdesigndescriptionsconsistofanENTITYdeclarationandanARCHITECTUREbodyTheENTITYdeclarationdescribesthedesignIOTheARCHITECTUREbodydescribesthecontentorfunctionofthedesignEveryarchitectureneedsanentitysoitiscommontorefertothemtogetherasanENTITYARCHITECTUREPAIRTheEntityTheEntityA“BLACKBOX”TheENTITYdescribestheIOoftheblackboxBLACKBOXrstd:clkq:coExampleEntitydeclarationExampleEntitydeclarationENTITYblackboxISPORT(clk,rst:INstdlogicd:INstdlogicvector(DOWNTO)q:OUTstdlogicvector(DOWNTO)co:OUTstdlogic)ENDblackboxWhatdoesitallmeanPortsPortsTheEntity(“BLACKBOX”)hasPORTSPORTSarethepointsofcommunicationPORTSareusuallythedevicepinsPORTShaveanassociatedname,mode,andtypePortModesPortModesAport’sMODEindicatesthedirectionthatdataistransferred:INDatagoesintotheentityonlyOUTDatagoesoutoftheentityonly(andisnotusedinternally)INOUTDataisbidirectional(goesintoandoutoftheentity)BUFFERDatathatgoesoutoftheentityandisalsofedbackinternallyEntityIEEETypesIEEETypesEveryportontheentityhasaTypeThetypeisalwayscheckedduringanassignmentorcomparisonBITaportoftypebitthatcanonlytakevaluesof''or''BITVECTORagroupingofbits(eachcanbe''or'')ENTITYtypeexampleISPORT(a:INBITb:OUTBITVECTOR(TO)ascendingrangec:OUTBITVECTOR(DOWNTO)descendingrangeENDtypeexampleb<=""Note:<=isanassignmentc<=""doublequotes(“”)usedforvectorsThismeansthat:b()=''c()=''b()=''c()=''b()=''c()=''b()=''c()=''INTEGERusefulasindexholdersforloops,constants,arithmeticfunctions,orsimulationmodelingBOOLEANcantakevalues‘TRUE’or‘FALSE’ENUMERATEDhasuserdefinedsetofpossiblevalueseg:TYPEtrafficlightIS(red,yellow,green)IEEETypes(contd)IEEEIEEEApackagecreatedtosolvethelimitationsoftheBITtypeNinevaluesinsteadofjusttwo(''and'')AllowsincreasedflexibilityinVHDLcoding,synthesis,andsimulationSTDLOGICandSTDLOGICVECTORareusedinsteadofBITandBITVECTORwhenamultivaluedlogicsystemisrequiredSTDLOGICandSTDLOGICVECTORmustbeusedwhentristatelogic(Z)isrequiredTobeabletousethisnewtype,youneedtoaddlinestoyourcode:LIBRARYieeeUSEieeestdlogicALLIEEETypesIEEETypesSTDLOGICandSTDLOGICVECTORarenowtheindustrystandardlogictypefordigitaldesignAllvaluesarevalidinaVHDLsimulator,howeveronly:‘’Hard‘’‘’Hard‘’‘Z’HighImpedance‘L’Weak‘’(likeresistorpulldown)‘H’Weak‘’(likeresistorpullup)‘’Don’tcarearerecognizedforlogicsynthesisEntityDeclarationExampleEntityDeclarationExampleLIBRARYieeeUSEieeestdlogicALLENTITYblackboxISPORT(clk,rst:INstdlogicd:INstdlogicvector(DOWNTO)q:OUTstdlogicvector(DOWNTO)co:OUTstdlogic)ENDblackboxExercise#:TheEntityExercise#:TheEntityWriteanentitydeclarationforthefollowing:PortDisabitbus,inputonlyPortOEandCLKareeachinputbitsPortADisabitbidirectionalbusPortAisabitbus,outputonlyPortINTisanoutputPortASisanoutputalsousedinternallymydesignd:oeclkad:a:intasExercise#:SolutionExercise#:SolutionLIBRARYieeeUSEieeestdlogicALLENTITYmydesignISPORT(d:INstdlogicvector(DOWNTO)oe,clk:INstdlogicad:INOUTstdlogicvector(DOWNTO)a:OUTstdlogicvector(DOWNTO)int:OUTstdlogicas:BUFFERstdlogic)ENDmydesignInthispresentation,VHDLkeywordsarehighlightedinbold,CAPITALSHowever,VHDLisnotcasesensitive:clock,Clock,CLOCKallrefertothesamesignalTheArchitectureTheArchitectureArchitecturesdescribewhatisintheblackbox(iethefunctionorbehaviorofentities)DescriptionscanbeeitheracombinationofStructuraldescriptionsInstantiationsofbuildingblocks(placementofcomponentsjustlikeaschematicandtheirconnections)BehavioraldescriptionsAlgorithmic(or“highlevel”)descriptions:IFa=bTHENstate<=stateBooleanequations:x<=(aORb)ANDcBehavioralArchitectureExampleBehavioralArchitectureExampleENTITYblackboxISPORT(a,b:INstdlogicvector(DOWNTO)y:OUTstdlogicvector(DOWNTO))ENDblackboxARCHITECTUREexampleOFblackboxISBEGINy<=aANDbENDexamplexInputANDgate:Thisexampleshowshowtodrivethedevicepins(theentityports)Howdowehandleinternalsignals(ornets)thatdonotconnectdirectlytothedevicepinsSignalsSignalsTypicallyusedtorepresentwires(ornets)EntityPortsareaspecialtypeofsignalLikeports,theyhaveanameandtype(however,thereisnomode)SignalsaredeclaredinsidethearchitecturebeforetheBEGINForExample,tocreateaninternalbitbus:ARCHITECTUREsignalexampleOFblackboxISSIGNALcount:stdlogicvector(DOWNTO)BEGIN<ManyVHDLStatements>ENDsignalexampleLet’slearnsomebasicVHDLstatements…CombinatorialLogicCombinatorialLogicTherearemanywaystodescribecombinatorialcircuitsInthenextfewslides,wewilltakealookatsomeexamplesofhowtodescribecombinatoriallogicYoushouldreferbacktotheseslidesforsomeideaswhenyoustartwritingyourfirstdesignsVHDLStatementExamples()BooleanEquationsVHDLStatementExamples()BooleanEquationsAllstandardBooleanoperatorsaresupportedinVHDLAND,OR,NOT,XOR,XNOR,NANDForexample,amultiplexerisshownbelowx<=(aANDNOT(s())ANDNOT(s()))OR(bANDNOT(s())ANDs())OR(cANDs()ANDNOT(s()))OR(dANDs()ANDs())VHDLStatementExamples()WITHSELECTWHENVHDLStatementExamples()WITHSELECTWHENAssignmentbasedonaselectionsignalWHENclausesmustbemutuallyexclusive(alldifferent)Alwaysuse“WHENOTHERS”tocoverunspecifiedcasesOnlyonereferencetothesignal,onlyoneassignmentoperator(<=)WITHselectionsignalSELECTsignalname<=valueWHENvalueofselectionsignal,valueWHENvalueofselectionsignal,valuenWHENvaluenofselectionsignal,valuexWHENOTHERSVHDLStatementExamples()WITHSELECTWHENVHDLStatementExamples()WITHSELECTWHENThesamemultiplexerwesawearliercouldalsobedescribedasfollows:WITHsSELECTx<=aWHEN“”,meanswhens=“”bWHEN“”,cWHEN“”,dWHENOTHERSVHDLStatementExamples()WITHSELECTWHENVHDLStatementExamples()WITHSELECTWHENTherecanbemultipleconditionsoneachline:WITHsSELECTx<=aWHEN””|“”|“”,bWHEN""|"",‘|’means“or”inthiscasecWHENOTHERSVHDLStatementExamples()WHENELSEVHDLStatementExamples()WHENELSESignalisassignedavaluebasedonconditionsAnysimpleexpressioncanbeaconditionPrioritygoesinorderofappearanceOnlyonereferencetothesignal,onlyoneassignmentoperator(<=)AlwaysendwithELSEtocoverunspecifiedconditionssignalname<=valueWHENconditionELSEvalueWHENconditionELSEvaluenWHENconditionnELSEvaluexVHDLStatementExamples()WHENELSEVHDLStatementExamples()WHENELSEThesameexamplemultiplexercouldalsobedescribedasfollows:x<=awhen(s=“”)elsebwhen(s=“”)elsecwhen(s=“”)elsedVHDLStatementExamples()WHENELSEVHDLStatementExamples()WHENELSEWhatisthedifferencebetweenWITHSELECTWHENandWHENELSEWITHSELECTWHENallowsonlyonecontrolsignalWHENELSEsupportsmanydifferentcontrolsignalsExample:Apriorityencoderj<=wwhen(a=‘’)elsexwhen(b=‘’)elseywhen(c=‘’)elsezwhen(d=‘’)else‘’VHDLStatementsVHDLStatementsTherearetwotypesofstatements,ConcurrentandSequentialConcurrentStatements(meansinparallel)Concurrentstatementsare“executed”concurrently(atthesametime)Theexampleswehaveseensofarareallconcurrentstatements:BooleanEquationsWHENELSEWITHSELECTWHENTheorderofconcurrentstatementsisnotimportantTheorderofconcurrentstatementsTheorderofconcurrentstatementsForexample,supposewehadthefollowinglinesofcode:x<=aORbORcy<=xWHEN(e=‘’)ELSE‘’Thiswillproduceexactlythesameresultas:y<=xWHEN(e=‘’)ELSE‘’x<=aORbORcTheorderthatyouwritethestatementsmakesnodifference,becausetheyareconcurrent(workinginparallel)VHDLStatements(cont)VHDLStatements(cont)SequentialStatements(meansinseries)SometimesweneedtomodelcomplexfunctionsInthatcase,wecanusean“algorithm”oramodeltodescribethefunctionThisisdonewithSequentialStatementsWithSequentialstatements,theORDERofthestatementsisimportant(examplelater)Therefore,weuseaprocesstomarkthebeginningandendofablockofsequentialstatementsEachcompletedprocessisconsideredtobeonebigconcurrentstatement(therecanbemanyprocessesinsideonearchitecture)WhatisaVHDL“Process”WhatisaVHDL“Process”Processesareeitherawakeorasleep(activeorinactive)AprocessnormallyhasasensitivitylistWhenasignalinthatsensitivitylistchangesvalue,theprocesswakesupandallofthesequentialstatementsare“executed”Forexample,aprocesswithaclocksignalinitssensitivitylistwillbecomeactiveonchangesoftheclocksignalAttheendoftheprocess,alltheoutputsareupdatedandtheprocessgoesbacktosleepuntilthenexttimeasignalchangesinthesensitivitylistTheProcess:AnExampleTheProcess:AnExamplemux:PROCESS(a,b,s)BEGINIFs=''THENx<=aELSEx<=bENDIFENDPROCESSmuxTheprocessmuxissensitivetosignalsa,b,andsThatmeansthatwheneveranyofthosesignalschangesvalue,theprocesswakesup,thesequentialstatementsareexecutedandtheoutputxisupdatedNote:Thelogiccouldberegistered(synchronous)orcombinatorialNote:Theorderofthesignalsinthesensitivitylistisnotimportantx(DOWNTO)sa(DOWNTO)b(DOWNTO)CombinatorialLogicusingSequentialStatementsCombinatorialLogicusingSequentialStatementsWehavealreadylookedatsomeexamplesofcombinatoriallogicusingConcurrentStatementsLet’stakealookathowtocreatecombinatoriallogicwithsequentialstatementsSequentialStatementExamples()IFTHENELSESequentialStatementExamples()IFTHENELSEForexample,atomulitplexercouldbedescribedasfollows:mux:PROCESS(a,b,c,d,s)BEGINIFs=“”THENx<=aELSIFs=“”THENx<=bELSIFs=“”THENx<=cELSEx<=dENDIFENDPROCESSmuxAnytimeyouwanttouseIFTHENELSE,thenyouMUSTuseaprocess,becauseitisasequentialstatementHowcantheorderofsequentialstatementsmakeadifferenceHowcantheorderofsequentialstatementsmakeadifferenceex:PROCESS(a,b)BEGINIFa=‘’THENc<=‘’ifaandbareENDIFboth‘’thenIFb=‘’THENc<=‘’bhaspriorityENDIFsoc<=‘’ENDPROCESSexex:PROCESS(a,b)BEGINIFb=‘’THENc<=‘’ifaandbareENDIFboth‘’thenIFa=‘’THENc<=‘’ahaspriorityENDIFsoc<=‘’ENDPROCESSexSequentialStatementExamples()CASEWHENSequentialStatementExamples()CASEWHENAnotherwaytodescribethesametomux:mux:PROCESS(a,b,c,d,s)BEGINCASEsISWHEN""=>x<=aWHEN""=>x<=bWHEN"”=>x<=cWHENOTHERS=>x<=dENDCASEENDPROCESSmuxAnytimeyouwanttouseCASEWHEN,thenyouMUSTuseaprocess,becauseitisasequentialstatementANoteaboutProcessesSignalAssignmentANoteaboutProcessesSignalAssignmentTakealookatthefollowingpieceofcodeWhichcircuitdoyouthinkwillbesynthesizedPROCESS(clock)BEGINIFrisingedge(clock)THENb<=aaftertherisingclockedge,agoestobc<=baftertherisingclockedge,bgoestocENDIFENDPROCESSaclockcbaclockORSignalAssignmentinProcessesSignalAssignmentinProcessesInsideprocesses,signalsarenotupdatedimmediatelyInstead,theyarescheduledtobeupdatedThesignalsarenotactuallyupdateduntiltheENDPROCESSstatementisreachedTherefore,onthepreviousslide,tworegisterswillbesynthesized(c<=bwillbetheoldb)Insomecases,theuseofaconcurrentstatementoutsidetheprocesswillfixtheproblem,butthisisnotalwayspossibleSohowelsecanwefixthisproblemVariablesVariablesWhenaconcurrentsignalassignmentoutsidetheprocesscannotbeused,thepreviousproblemcanbeavoidedusingavariableVariablesarelikesignals,BUTtheycanonlybeusedinsideaPROCESSTheycannotbeusedtocommunicateinformationbetweenprocessesVariablescanbeofanyvalidVHDLdatatypeThevalueassignedtoavariableisavailableimmediatelyAssignmentofvariablesisdoneusingacolon(:),likethis:c:=aANDbUsingVariablesvsSignalsUsingVariablesvsSignalsSolutionusingavariablewithinaprocess:cPROCESS(clock)VARIABLEb:stdlogicBEGINIFrisingedge(clock)THENb:=athisisimmediatec<=bthisisscheduledENDIFENDPROCESSaclockNativeOperators(IEEE)NativeOperators(IEEE)LogicaldefinedfortypeBIT,BITVECTOR,BOOLEANAND,NANDOR,NORXOR,XNORNOTRelationaldefinedfortypesBIT,BITVECTOR,INTEGER=(equalto)=(notequalto)<(lessthan)<=(lessthanorequalto)>(greaterthan)>=(greaterthanorequalto)NativeOperators(continued)NativeOperators(continued)ArithmeticdefinedfortypeINTEGER(addition),*(multiplication)(subtraction)ConcatenationdefinedforSTRINGASTRINGisanysequenceofcharactersstdlogicvectorisanexampleofaSTRINGNote:NoneoftheseoperatorsweredefinedtosupportstdlogicorstdlogicvectortypesbecauseinIEEE,stdlogicdidnotexistyetHowcanwefixthisproblemOverloadedOperatorsOverloadedOperatorsInVHDL,anynativeoperatorcanbeoverloaded(meansredefined)toacceptanyotherVHDLtypeThisisveryusefulForexample:SIGNALcounter:stdlogicvector(DOWNTO)counter<=counterthenative''operatorsupportsintegersonly,butwecanoverloadittoacceptstdlogicvectorsalsoThestdarithpackagefromCypressdefinesoverloadedlogicaloperators(AND,OR,NOT,etc,)forthestdlogicandstdlogicvectortypesTogetthecompilertorecognizestdlogicandtooverloadtheoperatorsyouneedtoaddlinestothestartyourVHDLfile:LIBRARYieeeUSEieeestdlogicalladdthestdlogictypeLIBRARYcypressUSEcypressstdarithalladdoverloadedoperatorsVHDLIdentifiersVHDLIdentifiersIdentifiersareanyuserdefinedlabels,signalnames,portnames,entitynamesetcVHDLhassomerestrictionsonidentifernames:Letters,digits,andunderscoresonly(firstcharactermustbealetter)ThelastcharactercannotbeanunderscoreTwounderscoresinsuccessionarenotallowedUsingreservedwordsisnotallowedExamplesthatarelegal:txclk,ThreeStateEnable,selD,HITExamplesthatarenotlegal:txclk,BB,large#num,entity,clkExercise#:ArchitectureDeclarationofaComparatorExercise#:ArchitectureDeclarationofaComparatorTheentitydeclarationisasfollows:LIBRARYieeeUSEieeestdlogicALLENTITYcompareISPORT(a,b:INstdlogicvector(TO)aeqb:OUTstdlogic)ENDcompareWriteanarchitecturethatcausesaeqbtobeassertedhighonlywhenaisequaltobMultiplesolutionsexistLookbackatthemuxexamplesExSolution:possiblesolutionsExSolution:possiblesolutionsConcurrentstatementsolutionusingaconditionalassignment:Concurrentstatementsolutionusingbooleanequations:ARCHITECTUREarchcompareOFcompareISBEGINaeqb<=''WHENa=bELSE''ENDarchcompareARCHITECTUREarchcompareOFcompareISBEGINaeqb<=NOT((a()XORb())OR(a()XORb())OR(a()XORb())OR(a()XORb()))ENDarchcomparepossiblesolutions(contd)possiblesolutions(contd)Solutionusingaprocesswithsequentialstatements:ARCHITECTUREarchcompareOFcompareISBEGINcomp:PROCESS(a,b)BEGINIFa=bTHENaeqb<=''ELSEaeqb<=''ENDIFENDPROCESScompENDarchcompareAggregatesandSubscriptsAggregatesandSubscriptsTheaggregateassignmentjoinssignalstogetherGoodforcreatingabusfromseveralsinglebitsConcatenationoperatorcanbeusedaswellSamenumberofarrayelementsonbothsidestmp<=(a,b,c,d)calledanaggregatetmp<=abcdconcatenationoperatorSignalscanbeextractedfromlargervectorsGoodforgroupingoutputsasan“alias”Sizesonbothsidesmustmatchrw<=ctrl()ce<=ctrl()oe<=ctrl()highcount<=count(DOWNTO)Exercise#:TheSchematicExercise#:TheSchematicExercise#Exercise#UseWarptocompiletheVHDLdesigndescript

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